KR100188142B1 - Memory access method for the fast synchronization of convolutional deinterleaver - Google Patents

Abstract

The present invention relates to a memory access method for fast synchronization of a convolutional deinterleaver applied to a forward error correction system (FEC system), which is one of the signal receivers in a digital television. Each circular buffer is assigned one or more pibuffer buffers, and includes a RAM 73 for storing data and a write address generator for generating column- and row-oriented addresses for determining space for writing on the RAM 73. For a convolutional deinterleaver comprising a 71 and a read address generator 72 for generating column and row addresses for determining a space for reading on the RAM 73 by inputting a simultaneous signal SYNC. When the synchronization signal SYNC inputted to the read address generator 72 is activated, the memory circuit is configured to transfer the read address generator 72 to the RAM 73. The mapping relation between the circular buffer allocated to the storage space of the RAM 73 and the target buffer is changed by changing the output column direction and row direction addresses, and the order of the target buffer to which the read operation is performed in the RAM 73 is changed. The present invention relates to a memory access method for fast synchronization of a convolutional deinterleaver.

Description

Memory Access Method for Fast Synchronization of Convolutional Deinterleaver

1 is a block diagram of a general signal receiver of a digital television;

2 shows a memory structure of a block interleaver,

3 illustrates a convolutional interleaving-deinterleaving operation process,

4 is a block diagram of a GI Digisigner receiver;

5 is a block diagram illustrating a general memory circuit for a convolutional deinterleaver.

6 is a block diagram illustrating a configuration of a memory circuit for a convolutional deinterleaver according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

71: write address generator 72: lead address generator

73: ram

The present invention relates to a convolutional deinterleaver, and more specifically, to fast synchronization of a convolutional deinterleaver applied to a forward error correction system (FEC sysyem), one of the signal receivers in digital television. The present invention relates to a memory access method.

Recent developments in digital video signal compression technology have made it possible to transmit large amounts of video signals in narrow bands. When a compressed video signal is transmitted through a noisy transmission line, an error due to noise occurs, and even if the error is not large at the time of reception, it may develop into a non-negligible error when decompression is performed. Transmission requires very low error probability.

In a broadcasting system such as digital television, even if an error occurs, retransmission is impossible, and thus, a lot of forward error correction (FEC) technology is used to enable correct error correction even when there is a certain amount of error.

Hereinafter, with reference to the accompanying drawings will be described in the prior art.

FIG. 1 is a block diagram of a general signal receiver of a digital television, FIG. 2 shows a memory structure of a block interleaver, and FIG. 3 shows a convolutional interleaving-deinterleaving operation process. Fig. 5 is a block diagram of a general memory circuit for a convolutional deinterleaver.

Referring to FIG. 1, a general signal receiver of a digital television is connected to an antenna 11, a tuner 12, a demodulator 13, a forward error correction decoder 14, and a demultiplexer 15 which receive broadcast waves in sequence. The demultiplexer 15 is connected to a video decoder 16 for a video signal and an NTSC (NTSC) encoder 17 in turn, while an audio decoder 18 and an audio for an audio signal are connected. The digital to analog converter 19 is connected.

In the above configuration, the demodulator 13 and the forward error correction decoder 14 have different structures depending on the transmission medium, i.e., whether it is a direct broadcast satellite (DBS), a cable broadcast or a terrestrial broadcast. The specifications required are different, and in the case of satellite broadcasting or cable broadcasting, different specifications are used by broadcasting companies in Korea.

Typically, forward error correction systems used in receivers of digital televisions include Viterbi decorders (or Trellis decorders), Reed-Solomon decorders and Deinterleavers. It consists of.

Next, a block deinterleaver and a convolutional deinterleaver used as the deinterleaver will be described.

Referring to FIG. 2, there is shown a memory structure of a block interleaver, which is the simplest type of interleaver.

The block interleaver has a depth I = 5 and spanN = 15.

As shown in FIG. 3, the block interleaver is an array-type RAM (Random Accerr Memory), which has I rows and N columns, and requires I × N memory space.

The symbols coded by the forward error correction coding technique are written in the column direction, and in the read operation, the symbols are performed in the row direction, resulting in a mixed order of the symbols.

That is, data (X1, X2, X3, ... X75) is written to the RAM in the column direction during the write operation, and data (X1, X16, X31, X46, X61, X2, ... X75) in the row direction during the read operation. Is read from the RAM.

The symbols out of order by the block interleaver are transmitted through the communication channel, and then the correct order is found by the block deinterleaver. The block deinterleaver has the same structure as the block interleaver except that it writes in the row direction and reads data in the column direction.

To convert a channel with memory to a channel without memory, the depth I must be greater than the channel memory length, and the span N of the block interleaver is the code memory length of the forward error correction coding, i.e. Must be greater than the number of symbols used for coding.

Referring to FIG. 3, there is shown an operation process of a convolution interleaving-deinterleaver as another widely used interleaving-deinterleaving method. The convolutional interleaver has an advantage of using only one quarter of the memory as compared to the block interleaver.

3 shows the operation of the convolutional interleaver-deinterleaver with depth I = 5 and span N = 15.

In the convolutional interleaver, the coded symbols are alternately input to five First In First Out (FIFO) buffers (or shift registers), and the outputs are alternately alternated from the five fifo buffers. The first picobuffer sends the output directly without storage, and the next picobuffer has 3 more symbols.

In this way, the adjacent two symbols can fall far through the convolutional interleaver. The convolutional deinterleaver on the receiver side also operates in the same way, and differs from the convolutional interleaver in that input and output are performed in a direction in which the number of symbols decreases.

The depth must be larger than the channel memory, and the span N = I × J of the interleaver must be larger than the code memory. In the above, J is the number of bits of symbols input and output at one time.

Figure 4 shows a block diagram of the receiver of a Digital Insturment (GI) Digicipher system that is expected to be adopted by US cable television companies as the transmission method.

The receiver of the GI digitizer system is an antenna 21 for receiving broadcast waves, a demodulator 22, a convolutional deinterleaver 23, a Viterbi decoder 24, a block deinterleaver 25, and a lead- The Solomon decoder 26 and the derandomizer 27 are sequentially connected.

The convolutional deinterleaver 23 is located at the front end of the Viterbi decoder 24 in the receiver of the GI Digicipher system configured as described above, and both the depth and span are 31 and one symbol. The size of is 2 bits.

The convolutional deinterleaver 23 that comes in front of the Viterbi decoder 24 has a relatively small size (7 bits) because the code memory of the Viterbi decoder 24 is very small (minimum memory requirement). Is less than 1 Kbits), in this case the problem is synchronization time, not cost.

The convolutional deinterleaver 23 of the receiver has different results depending on which PB buffer the symbol is input to, and therefore requires proper synchronization.

When a convolutional deinterleaver is in front of a lead-solo-moon decoder, such as Zenith's Vestigial Side Band (VSB) system or the European Digital Television Broadcasting (DVB) system. Synchronization can be easily achieved by finding a predetermined synchronization word (also known as a synchronization word, sync word, or frame marker or header) in a data sequence and writing it to a predetermined buffer.

However, when the convolutional deinterleaver 23 is located in front of the Viterbi decoder 24, unlike the Reed-Solomon decoder, since the sync word is not preserved by the coding, the method of finding the sync word cannot be solved.

As described above, when the convolutional deinterleaver 23 is used in front of the Viterbi decoder 24, there is an ambiguity of which bit to be input to which pibuffer.

The combination of various possible ambiguities can lead to a very diverse number of states of input at the front of the Viterbi decoder, of which only one is correct. The method of solving this ambiguity assumes the state of a particular input and applies the input to the Viterbi decoder to determine if the data is valid. Otherwise, the state of the input must be changed and try again. The same process is repeated until the input data is considered valid.

Whether the data is valid can be determined from the renormalization rate, the path metric increasing rate, the bit error rate, and the like.

Therefore, in the conventional convolutional deinterleaver, the time of IN is delayed as a normal delay of the convolutional deinterleaver so that the output of the changed state comes out when the state is changed. This will be described with reference to FIG. 5.

5 shows a block diagram of a general memory circuit for a convolutional deinterleaver.

Referring to FIG. 5, a general memory circuit for a convolutional deinterleaver includes a RAM 63 for inputting data and a column for determining a space for writing on the RAM 63 by inputting a synchronization signal SYNC. A write address generator 61 for generating a direction and a row direction address, and a read address generator for generating column and row direction addresses for determining a space for reading on the RAM 63 by inputting a synchronization signal SYNC. It consists of 62.

In the above configuration, the RAM 63 uses N × M dual-port RAM. A plurality of buffered buffers are allocated to the storage space of the RAM 63.

Looking at the operation, the input data (INPUT) comes in one side of the RAM (63), the output data (OUTPUT) comes out the other side, the write address generated by the write address generator 61 and the read address generator 62 ( The storage space of the RAM 63 is designated by a write address and a read address.

The write address or read address comprises a column direction and a row direction address, wherein one of the pipe buffers to be allocated on the RAM 63 is selected by the column direction address, and the row address of the selected pipe buffer is selected by the row direction address. The specific storage space is selected.

In FIG. 5, the input data INPUT and the output data OUTPUT change states together in response to the synchronization signal SYNC.

If the synchronization signal SYNC is activated to change the state of the convolutional deinterleaver, the column addresses of the write address generator 61 and the read address generator 62 are changed so that the other PIP buffer on the RAM 63 is changed. It has the same effect as choosing. In this case, the data already stored in the RAM 63 are no longer valid.

However, the conventional memory circuit for the conventional convolutional deinterleaver has a long synchronization time because it has to wait for the time of IN, which is the delay time of the convolutional deinterleaver, in order for the output of the state changed by the synchronization signal SYNC to come out. There are disadvantages. Therefore, an object of the present invention for solving the above-described problems is to provide a memory access method for fast synchronization of a convolutional deinterleaver so that an output thereof is immediately output when the state of the convolutional deinterleaver is changed by a synchronization signal. To provide.

A memory access method of the present invention for achieving the above object is a memory device for storing data by assigning a plurality of circular buffers to a specific area and one or more PIP buffers to each circular buffer, and writing on the memory device. A write address generator for generating column and row direction addresses for determining a space to be used; and a read for generating column and row direction addresses for determining a space for reading on the memory device by inputting a synchronization signal SYNC. It is composed of a memory circuit for a convolutional deinterleaver composed of an address generator. When the synchronization signal SYNC input to the lead address generator is activated, the column and row addresses inputted from the read address generator to the memory device are changed. Change the mapping relationship between the circular buffer and the buffer buffer allocated to the memory space of the memory device. The order of the encapsulated buffer to be read operation in a memory device carried is characterized in that to change.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

6 is a block diagram illustrating a memory circuit for a convolutional deinterleaver according to an embodiment of the present invention.

As shown in FIG. 6, a memory circuit for a convolutional deinterleaver according to an embodiment of the present invention includes a RAM 73 that receives input data INPUT on one side and outputs output data OUTPUT on the other side; A write address generator 71 having an output terminal connected to the RAM 73 and a synchronization signal SYNC are input, and a read address generator 72 having an output terminal connected to the RAM 73.

In the above configuration, the RAM 73 uses N-M dual-port RAM, but the technical scope of the present invention is not limited thereto. A plurality of circular buffers are allocated to the storage space of the RAM 63, and one or more buffered buffers are assigned to each circular buffer. In the above configuration, each circular buffer is the same size.

Looking at the operation, the input data (INPUT) comes in on one side of the RAM (73), the output data (OUTPUT) comes out on the other side, the write address generated by the write address generator 71 and the read address generator (72) The storage space of the RAM 63 is designated by a write address and a read address.

The write address or read address is composed of a column direction and a row address, and one of the circular buffers allocated on the RAM 73 is selected by the column direction address, and the row address in the selected circular buffer is set by the row direction address. The specific storage space is selected.

In FIG. 5, the input data INPUT and the output data OUTPUT change states together in response to the synchronization signal SYNC.

If the synchronization signal SYNC input to the read address generator 72 is activated in order to change the state of the convolutional deinterleaver, the column address generated by the read address generator 72 is changed to the RAM 73. Another picobuffer on the screen is selected.

That is, the output of the state of the deinterleaver is obtained from the data stored in the RAM 73 by the changed column address of the read address generator 72, and the data stored in the RAM remains valid even though the state is changed. . The output of which the state of the deinterleaver is changed in the RAM 73 is obtained because the mapping between the circular buffer and the buffer buffer inside the RAM 73 is converted by the input column direction address.

As a result, in the embodiment according to the present invention, when the synchronization signal SYNC is activated, only the read address of the read address generator 72 is changed regardless of the write address generator 71, and accordingly, the circular buffer in the RAM 73 is changed. The order of the target buffers in the RAM 73 is changed by changing the mapping relation between the target buffers and the target buffer.

Next, the memory access problem according to the embodiment of the present invention is expressed as program code similar to the C language as follows.

In the program code, constants are explained.

If you describe the variable,

Offset [f]: Starting address of circular buffer containing f-fi buffer

i [f]: Light address on the circular buffer containing the f pipo buffer,

j [f]: Represented as the read address on the circular buffer containing the f-fipo buffer, f, g, and h are arbitrary variables.

Next, the program code is described in more detail. The first six lines specify the initial state. for (;;) represents an infinite loop, and the next four lines represent read and write to RAM 73 by synthesizing the read and write addresses.

The address consists of the sum of the offset indicating the starting address of the circular buffer and the position (i or j) in the circular buffer. f = (f + 1)% I; indicates that f changes sequentially and reads and writes to another pipe buffer. In this case, even if the sync signal SYNC is activated, f does not affect the write order.

Therefore, f does not determine to which buffer to read and to write, but to which circular buffer to perform the write and read operation.

Two lines from if (f == 0) indicate that i increments by one period. Line 4 from if (SYNC) indicates that h and j change instead of f when the SYNC signal is activated. h is for remembering the state that the synchronization signal is changing, j is not necessary for writing because it is necessary to make the address when reading data.

When the sync signal SYNC is activated, f does not change and the value of j and other internal registers is changed to read the correct data in the changed state without changing the writing order.

The next four lines from else indicate that j changes when the sync signal SYNC is not activated. g determines what type of buffer is used. That is, since f is a circular buffer, it may not change even when the synchronous signal SYNC is activated, and g determines which PIB buffer is activated, and when the synchronous signal SYNC is activated, the order is changed by stopping the process for a moment. .

In this way, the order of the buffers is changed without changing the order of the circular buffers, that is, only the read order is changed without changing the write order, thereby saving the synchronization time by outputting correct data as soon as the synchronization status is changed.

As described above, in the embodiment of the present invention, when the state of the convolutional deinterleaver is changed by the synchronization signal by changing the write order without changing the read order, a corresponding output of the convolutional deinterleaver is immediately released. A memory access method for synchronization can be provided.

Claims (4)

A plurality of circular buffers are allocated to a specific area, and each circular buffer is assigned one or more buffered buffers to generate a memory device for storing data, and to generate column and row addresses for determining space for writing on the memory device. And a memory circuit for a convolutional deinterleaver comprising a write address generator and a read address generator for generating a column and row direction address for determining a space for reading on the memory device by inputting a synchronization signal SYNC. When the synchronization signal SYNC input to the read address generator is activated, the column address inputted from the read address generator to the memory device is changed to change the mapping relationship between the circular buffer and the buffer buffer allocated to the memory space of the memory device. The order of the buffered buffers in which the read operation is performed in the memory device is changed. Memory access method for fast synchronization of the convolutional deinterleaver, characterized in that. The method of claim 1, wherein the plurality of circular buffers are the same size. The memory access method of claim 1, wherein the memory device is a RAM capable of reading and writing. The memory access method of claim 1, wherein the synchronization signal SYNC is input only to the read address generator and not to the write address generator.