KR100187748B1 - Electrically-erasable, electrically-programmable read-only memory cell and method of making thereof - Google Patents

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Description

Electrically erasable, electrically programmable read only memory cell and method of manufacturing the same

1 is a plan view of a small portion of a semiconductor chip having a memory cell in accordance with one embodiment of the present invention.

2A-2E are front views of the semiconductor device of FIG. 1, taken along the lines a-a, b-b, c-c, d-d, and e-e of FIG.

3 is an electrical schematic of the cells of FIGS. 1 and 2A-2E.

4a to 4d are front views of the device of FIGS. 1 and 2a to 2e corresponding to FIG. 2a in successive fabrication steps.

5 is a plan view of a small portion of a semiconductor chip having a memory cell according to the second embodiment.

6A-6B are front views of the cross section of the semiconductor device of FIG. 5, taken along the lines a-a and b-b of FIG.

FIG. 7 is a top view of a device similar to the top view of FIG. 1 taken along line a-a but with a tunnel window across the source and drain regions.

* Explanation of symbols for main parts of the drawings

10 cell 11 silicon substrate

12: word line / control gate 13: bit line

14 thermal silicon oxide layer 15 source region

16: drain region 17: floating gate

18: transition region 19: tunnel region

20 dielectric film 21 field oxide region

22: oxide separation region 22a: bird's beak

23: trench 31: nitride

34: oxide-nitride-oxide film

This application is assigned to pending Texas Instruments Incorporated and is assigned to U.S. Patent Application No. 07 / 274,718 (continued, currently abandoned) in US Patent Application No. 07 / 056,196, in particular Application No. 07 / 219,528, Patent Application No. The contents described in 07 / 219,529 and patent application 07 / 219,530 are described.

BACKGROUND OF THE INVENTION The present invention relates to semiconductor memory devices, in particular floating-gate type of electrically erasable and electrically programmable ROM (read only memory) and a method of manufacturing the same.

EPROM, or electrically programmable ROM, is a field-effect device with a floating-gate structure.

Typically, EPROM floating-gates apply appropriate voltages to the source, drain, and control gates of each cell, and high currents through the source-drain paths. Is generated and the floating gate is charged by the high temperature electrons, thereby making it programmable. The EPROM type of device is usually erased by ultraviolet light, which requires a device package with a quartz window on the semiconductor chip. Packages of this type are more expensive than conventional plastic packages used for other storage devices such as DRAM (dynamic constant speed call storage devices). For this reason, EPROMs are generally more expensive than plastic package devices. EPROM devices and methods of fabrication of this type are described, for example, in US Pat. No. 3,984,822; 4,142,926; 4,142,926; 4,258,466, 4,376,947; 4,326,321; 4,326,321; 4,313,362; 4,373,248 and the like. U.S. Patent No. 4,750,024 shows that EPROM is manufactured by a method similar to Patent No. 4,258,466, but a split-gte structure in which part of the floating gate and part of the control gate is separated from the channel region by a thin dielectric. Have

EEPROMs or electrically erasable, electrically programmable ROMs are manufactured by a number of processes and usually require larger cells than standard EEPROMs. The structure and manufacturing process are usually more complicated. EEPROM arrays can be mounted in opaque plastic packages that can reduce package costs. Nevertheless, EEPROM arrays are more expensive on a per-bit basis due to larger cell sizes and complex manufacturing processes compared to EPROM. The split-gate structure of US Pat. No. 4,258,466 has been used in EEPROM arrays, because even if one or more floating gates are over-erased, the structure is not capable of performing read, program and erase operations. This is because the memory cells or cells involved in the channel region under the floating gate are electrically charged, thereby making sure that the state of charge becomes stable.

Compared to EPROM arrays, EEPROM arrays require a wider range of voltages to be applied to bitlines for programming, reading and erasing. Because the bitlines are connected to many cells in an array other than the programmed, read, and erased cells, the wide range of voltages is inadvertently caused by one or more other cells. The possibility of being programmed or erased is increased. This problem is evident in so-called virtual-grounded arrays such as those described in US patent application Ser. No. 07 / 274,718.

Since the cells are not individually erased, the flash EEPROM has the advantage that the size of the cell is smaller than that of the standard EEPROM. Instead, the array of cells is erased in bulk.

Currently available flash EEPROMs require at least two external power supplies, one for programming and erasing and the other for reading. Typically, a 12-volt power supply is used for programming and erasing and a 5-volt voltage supply is used during read operation. However, it is desirable to use a single relatively low-voltage supply for both programming, erase and read operations. For example, on-chip charge pump technology can be used to generate high-voltage from a 5-volt supply when an array of memory cells is designed to be programmed and erased by drawing relatively small currents. Typically, cells designed for Fowler-Nordheim tunneling used for programming and erasing require relatively little current compared to the current required when programming using hot-electron.

Pending US patent application Ser. No. 07 / 219,528; The EEPROMs described in 07 / 219,529 and 07 / 219,530 provide an external power source for the chip by a device requiring a single relatively low voltage (around + 5-volt), thus facilitating the manufacture and reduction of the EEPROM. It provides a greatly improved structure and method for producing a cell having a size. The devices of the present invention use Fowler-Nordheim tunneling to erase and program. However, the devices of the present invention require a split-gate, which is over-eaased by a floating-gate without read, erase, and program operations that can adversely affect it. Be sure to Unfortunately, the split-gate structure requires additional sacrificial space in the integrated circuit board compared to the space required by conventional stacked-gate structures.

As methods have been developed to eliminate the problems associated with over-erasing of floating gates, there is a need for a structure that eliminates the need for split gate space. At the same time, non-split-gate structures have the advantage of self-aligning embedded bitline and process structures. These advantages include reduced cell size and improved coupling to the floating gate of the voltage applied to the control gate. It would also be desirable to provide a memory that can be packaged in an electrically opaque, electrically programmable and inexpensive opaque plastic package. Each memory cell must be designed to scale to smaller sizes, such as technology improvements in processing that allow for a reduction in size. Preferably, non-volatile memory uses a single low-voltage external supply for programming, erasing, and reading. This memory device is also suitable for programming in circuit or on board.

According to one embodiment of the present invention, an electrically erasable PROM, or EEPROM, is constructed using one transistor structure without a split-gate structure that requires a portion of the control gate and a floating gate portion to be disposed over the channel region. The floating-gate transister may have a small self-aligned tunnel window located above the source away from the channel region, or the tunnel may be located above the source near the channel region. EEPROM devices have a contact-free cell layout that improves ease of manufacture and reduces cell size. The device has a bitline (source / drain region) embedded under a relatively thick silicon oxide, allowing good connection of the control gate voltage to the floating gate. Programming and erasing is accomplished using a tunnel window region that allows the use of relatively small currents drawn from the charge-pump source for programming and erasing. The tunnel window has a dielectric thinner than the remainder of the floating gate, allowing Fowler-node Haim tunneling. By using a dedicated drain and ground line, rather than a virtual-ground circuit layout, and using thick oxide to separate the bit lines of adjacent cells, the floating gate extends to adjacent bit lines and isolation regions. Can be. Therefore, this structure has a good capacitive ratio for connecting the control gate voltage to the floating gate during write and erase operations.

New features believed to be features of the invention are set forth in the appended claims. The objects and advantages of the invention as well as the invention are best understood by reference to the following description of specific embodiments of the invention when read in conjunction with the accompanying drawings.

Referring now to FIGS. 1, 2A-2E and 3, an electrically erasable, electrically programmable memory cell 10 is shown formed on one side of a silicon substrate 11. will be. Only a very small portion of the substrate is shown in the figure, and it can be seen that these cells are part of an array of many such cells. The plurality of wordline / control gates 12 are formed by a second level of polycrystalline silicon (polysilicon) strip extending along one side of the substrate 11, and the bitlines 13 are formed on the side of the substrate. It is formed under the thick thermal silicon oxide layer 14 in the interior. These embedded bit lines 13 create source and drain regions 16 and 16 for the respective cells 10. The floating gate 17 for each of the cells is formed by a first level of polysilicon layer extending over the associated bitline 13 through the channel region between the source region 15 and the drain region 16. The edges of the two horizontal or X-direction floating gates 17 for the cell match the edges of the word line 12.

A tunnel region 19 for programming and erasing is formed over the source 15 portion of each cell, and the source 15 portion is opposite the channel region. Alternatively, the tunnel region 19 is formed as shown in FIGS. 5 and 6a, where the tunnel window is located above the source portion 15 near the channel region. The structures of FIGS. 5 and 6a are also described in pending US patents 07 / 219,528 and 07 / 219,530. The silicon oxide in the tunnel window 19 is about 100 kW thinner than the dielectric film 20 about 350 kW in the channel. When using this structure, programming and erasing can be performed at relatively low externally-applied voltages. The coupling between layers 12 and 17 allows the floating gate 17 and the source 15 or substrate to extend outward beyond the bitline 13 and the separated thick oxide isolation regions 22. It is better compared with the bond between (11). Therefore, most of the programming / erase voltage applied between the control gate 12 and the source 15 will appear between the floating gate 17 and the source 15. The cell 10 is called cantact-free in that source / drain contact is not needed near the cell at all.

7 shows another embodiment of the present invention. The structure of FIG. 7 allows, for example, the window 19 to be used to allow programming using the window 19 over the source 15 and erasing using the window 19 over the drain 16. 15) and the structure above the drain region 16, except that the structure is similar to that of FIG.

In Figures 1 and 2b, region 21 is used to separate the cells from each other in the Y-direction. This area 21 is a thick field oxide area similar to the area 21 of the pending US patent application Ser. No. 07 / 219,530 described above, or the area 21 is as shown in FIGS. 5 and 6b, and is described above. It may be replaced with a trench 23 implanted with a P-type impurity as described in US Pat. No. 07 / 219,528. As is known, trench 23 is filled with an oxide not shown. A strip 22 of LOCOS thick field oxide separates the bitline 13 between the cells in the X-direction. Note that the array of cells is not virtual-grounded-circuit. That is, there are two bit lines 13 or column lines (one for the source and one for the drain) for each column (Y-direction) of the cells, one bit line is dedicated ground and the other One is the data input / output and sense lines.

The EEPROM cells of FIGS. 1, 2A-2E, and 3 are about + 15V to + 20V charged-pump-generate with respect to the source 15 of the selected cell 10. The voltage is programmed to Vpp. For example, in FIG. 3, when cell 10a is selected to be programmed, the selected word line 12, denoted WL1, becomes + Vpp, and the selected source, denoted SO, is grounded. Since the selected drain 16 (indicated by D0 in this example) is floating under this programming condition, there is little or no current through the source-drain passage. Fowler-nodeheim tunneling through tunnel oxide 19 (having a thickness of about 100 μs) charges the floating gate of selected cell 10a, resulting in a threshold of about 3V to 6V after a programming pulse of about 10msec in length. It generates a shift in the voltage (vt).

The selected cells of FIGS. 1, 2A-2E and 3 show a voltage Vee (internally-generated) of about -10V on the selected wordline / control gate 12 and the source 15 or bitline. It is erased due to the application of a voltage of about + 5V on (13). The drain 16 (the other bit line 13) is floating. During the erase operation, since the control gate 12 becomes negative with respect to the source 15, electrons flow from the floating gate 17 to the source 15. During the erase operation, care must be taken not to over erase the cell. One way to prevent over erasure is to apply a continuous erase pulse to the device to check to ensure that no threshold voltage of any cells falls below a predetermined minimum threshold voltage between erase operations. Another method is to reinject electrons into the floating gate of some over-erased cell.

Other methods for erasing may include (1) applying a large negative voltage of about -18V to the selected control gate 12 having 0V on the selected source 15, or (ii) the selected source 15 Applying a voltage of about + 13V to cause the selected drain 16 to float, and connecting the selected control gate 12 to a reference potential or 0V. The use of the latter method can avoid the lack of negative voltage supply.

When a flash erase is performed (all cells 10 are erased at the same time), all the drains 16 in the arrays of FIGS. 1, 2a through 2e and 3 are floating, and all Source 15 is at potential Vdd and all wordline / control gates 12 are at potential -Vee.

In order to prevent a write-disturb state during the programming example (where cell 10a is programmed), all sources of unselected cells, such as cell 10b on the same wordline WL1 in FIG. 15 is maintained at a voltage Vb1 in the voltage range of about +5 to + 7V. The drain 16 of an unselected cell, such as cell 10b, is floating, preventing source-drain current from flowing. The voltage Vb1 applied to the source 15 does not become large enough that the electric field across the tunnel oxide 19 of the cell comprising the exemplary cell 10b is sufficient to start electron tunneling and charge the floating gate 17. Do not let it.

Another condition to be prevented is deprogramming, or bitline-stress, associated with the high electric fiedl across the programmed tunnel's tunnel oxide when the source of the cell is at a potential near Vb1. )to be. To prevent this bit line stress condition, the unselected wordline / control gates WL0 and WL2 in FIG. 3 are maintained at voltages in the range of about +5 to + 10V, so that the tunnel of each unselected programmed cell The electric field across the oxide 19 is reduced. Since a programmed cell such as cell 10c has a potential of about -2 to -4V on the floating gate, the voltage Vb1 on source S1 of such cell 10c is +5 to + 7V. When in range, the electric field across the tunnel oxide tends to deprogram the cell, but the electric field is reduced by a voltage in the range of + 5V to + 10V on wordline WL2. However, the word line / control gate is not large enough to change the threshold voltage Vt in a cell having no charge on the floating gate.

The cell described above can be read at low voltage. For example, a row of cells is read by applying + 3V on the selected wordline / control gate, 0V across all other wordline / control gates, 0V across the source, and + 1.5V across the drain. In this state, the source-drain path of the cell is conducted by the cell in the erased state (the cell with zero charge on the floating gate). That is, it stores logic 1. The programmed cell (programmed in the high voltage threshold state and having negative charge on the floating gate) is not conductive. That is, it stores logic 0.

Methods of manufacturing the devices of FIGS. 1 and 2A through 2E will be described with reference to FIGS. 4A through 4D. The starting material is a slice of P-type silicon in which the substrate 11 is made up of very small portions. This slice is about 15.24 cm (6 inches) in diameter, but the portion shown in Figure 1 is only a few microns wide. Multiple process steps are performed to fabricate transistors around the array, and these steps are not discussed herein. For example, a memory device is a complementary field-effect type with N-wells and P-wells formed in a substrate as part of a conventional process for making peripheral transisters. Can be The first step associated with the cell array of the present invention is to apply oxide and silicon nitride films 30 and 31, as shown in FIG. 4A, to become channel regions, tunnel regions, sources, drains, and bit lines 13. Patterning these films using a photoresist to leave nitride thereon, forming a thick field oxide region 22 ((21) when oxide separation other than trench 23 is used). Expose areas to be exposed. Boron implantation in a dosage of about 8 × 10 ¹² cm ⁻¹ is performed to make the P + channel stop below the field oxide 22 (possibly (21)). The field oxide then grows to a thickness of about 9000 kPa by exposure to steam at about 900 ° C. for several hours. Thermal oxide grows at the bottom of the nitride 31 edge, producing a bird's beak instead of a sharp transition.

Referring now to FIG. 4B again, in the region where nitride 31 is removed and bitline 13 is formed, arsenic implantation is used as an implant mask to make source / drain regions and bitlines. The photoresist is used at a dose of about ⁶ × ^{10 15} cm ⁻² at 135 KeV. The other thermal oxide 14 is then [heavily-doped and lightly-doped silicon region to create an oxide layer 14 over the source / drain regions and bitline 13. At the same time it grows on the N + buried bitline with a thickness of about 2500 to 3000 microns over the N + buried bitline, during which time the thermal oxide on the channel region grows due to the different oxidation that occurs when exposed to oxidation. This oxidation is carried out in steam at about 800 to 900 ° C. In the transition region where the Buds beak 22a is formed, the edge of the originally formed thermal oxide masks arsenic implantation so that the concentration is low, and the grown oxide in this region is the growth of the oxide 14 or oxide 22. Less than

Referring to FIG. 4C, the window 19 is open at the oxide in the transition zone 18. This is done by using a photoresist as a mask, etching through the oxide of the transition region 18 in bare silicon, and then by regrowth of the thin oxide for the tunnel window 19. While oxidizing the tunnel window 19, the gate oxide 20 grows to about 350 GPa. Optionally, self-aligned N-type implantation (eg, arsenic or phosphorous) in tunnel window 19 may be used for improved field plate breakdown voltage. Tunnel window 19 acts as a mask during injection.

Because of the curved surface of the transition region 18, the width of the tunnel window 19 is controlled by varying the time to etch through the transition region 18.

The N ⁺ doped N ⁺ first polysilicon layer is now applied to the side of the silicon slice. The first level polysilicon is defined to leave an elongated strip in the Y-direction using a photoresist, a portion of which becomes the floating gate 17. The edges of the polysilicon strips are coated with oxide using standard sidewall oxide processes. An oxide or oxide-nitride-oxide coating 34 is then applied to insulate the floating gate 17 from the control gate 12. The second polysilicon layer is deposited and N + doped and patterned in the X-direction to create the witherline / control gate 12 using photoresist. At the same time as the wordline / control gate 12 is determined, the edges of the first level polysilicon are etched, so that the extended X-direction edges of the floating gate are self-aligned with the edges of the control gate. It is to be noted that the figures are not drawn to scale, and in particular the thickness of the first and second polysilicon layers is generally much thicker than the thickness of the oxide layers 19 and 20.

When junction separation is used for the isolation region 23, the self-aligned ion implantation step is a mask for making the isolation region 23. It is carried out using stacked polysilicon-1 and polysilicon-2 layers. For this purpose, boron is injected into a dosage of about 10 ¹² cm ⁻² at about 70 KeV. After annealing and oxidation, this implantation produces a P + region underneath the region 23 which is very similar to the channel-stop implantation underneath the field oxide region 21.

The advantage of placing the tunnel window on the opposite side of the source from the drain as described above is that the alignment of the mask when manufacturing is considerably less than the method described in the aforementioned application. Incidentally, an important advantage is that for the P junction, the field plate breakdown voltage of the junction between the buried N + region and the substrate is improved due to the fact that the overlapping oxide on both sides of the N + is thicker than the tunnel oxide thickness of 100 kPa. . Incidentally, the overall cell size is reduced because the alignment to the tunnel does not need to be taken into account. Tunnel oxides of 100 μs may have a width less than the minimum specification allowed by conventional design schemes. In addition, the cells may be bar-shrink or scale at redesign.

Although the present invention has been described with reference to the illustrated embodiments, this description is not meant to be construed in a limiting sense. In addition to various modifications of the illustrated embodiment of the present invention, other embodiments of the present invention will become apparent to those skilled in the art with reference to this description. Therefore, it is to be understood that the appended claims may cover any such modifications or embodiments that fall within the true scope of the invention.

Claims (22)

In an electrically-erasable, electrically-programmable floating-gate memory cell, each region is a heavily-doped region of conductivity type opposite to the material underlying the semiconductor body, each region being a semiconductor body. Buried beneath a relatively thick layer of silicon oxide on the surface, the source region being separated from the drain region on the semiconductor body face by a channel region, and the memory cell being separated in one direction from adjacent cells by the field oxide region; A source region and a drain region formed in the semiconductor body surface, over the channel region, and extending to the silicon oxide over the source region, the silicon oxide over the drain region, and the field oxide region adjacent to the source and drain region, Crab from the channel region on the semiconductor body surface A floating gate separated by a bit insulator, the floating gate extending over the tunnel region, separated from the source region by the tunnel insulator, the thickness of the tunnel insulator in the tunnel region being the thickness of the gate insulator in the channel region A thinner tunnel region over the source region, and a control gate extending along the semiconductor body surface above the floating gate and the source and drain regions and separated from the floating gate by an insulator coating. Memory cell. 2. The memory cell of claim 1 wherein the tunnel region is on the channel side of the source region. The memory cell of claim 1, wherein the tunnel region is over the source region at the intersection of the thick layer of silicon oxide and the field oxide. 2. The drain region of claim 1, wherein the tunnel region is above the source region at the intersection of the thick layer of silicon oxide and the field oxide, and the second tunnel region is the drain region at the intersection of the thick layer of silicon oxide and the field oxide. Memory cell, characterized in that above. The memory cell of claim 1, wherein the semiconductor body is silicon and the source and drain regions are N + type. The memory cell of claim 1, wherein the floating gate and the control gate are polycrystalline silicon layers. The memory cell of claim 1, wherein the silicon oxide is thicker than the gate insulator coating in the channel region. 2. The memory cell of claim 1, wherein the control gate is an elongated wordline portion extending along the semiconductor body surface. The memory cell of claim 1, wherein the control gate is aligned with an edge of the floating gate. 2. The memory cell of claim 1, wherein no contact is formed between the source or drain region and a conductor layer on top of the cell vicinity. The memory cell of claim 1, wherein the tunnel region is adjustable by oxide etching. 2. The memory cell of claim 1, wherein the tunnel region is self-aligned. The memory cell of claim 1, wherein the memory cell is separated from the cells in different directions by a field oxide region. The memory cell of claim 1, wherein the cell is separated from the cells in the other direction by a doped region under the trench. A method for fabricating an erasable, electrically programmable floating gate array cell comprising in-plane column lines and row lines on a surface of a semiconductor body, the method comprising: forming a layer of an oxide-resistant material on the face of a semiconductor body; Applying and patterning the layer such that the channel region of the face and the source and drain regions of the face are covered, the first field oxide to produce a first field oxide where the face is not covered by the oxidation-resistant material. Growing an oxide film on the surface, selectively implanting impurities into the surface to create a source and drain region along the regions of the column lines, to form a thick thermal oxide film on the source and drain region Growing a second field oxide on the surface, the first and second fills Growing a gate oxide film on the face above the channel region to a first thickness thinner than de oxide, and then opening a window in the gate oxide film above the tunnel region, and onto the second field oxide above the source region. Regrowing a gate oxide in the window to a second thickness considerably thinner than the first thickness to provide an adjacent tunnel window, applying a first conductive layer on the face, over the channel region and over the second field oxide; Patterning the first conductive layer to overlap and leave a floating gate that partially overlaps the first field oxide, and overlapping and conductive to the first conductive layer to create a gate over the floating gate And applying a second conductive layer onto the face insulated from the surface. 16. The method of claim 15, wherein the tunnel window is on the channel side of the second field oxide above the source region. 16. The method of claim 15, wherein the tunnel window is between the first field oxide and the second field oxide over the source region. 16. The device of claim 15, wherein the tunnel window is between the first field oxide and the second tunnel oxide over the source region, and a second tunnel window is over the second field oxide and the second field oxide over the drain region. Characterized in that it exists between. 16. The method of claim 15, wherein the semiconductor body is P-type silicon and the impurity is N-type silicon. The method of claim 15 wherein the first and second layers are polycrystalline silicon. 16. The method of claim 15, wherein the first thickness is thicker than the second thickness and the thicknesses of the first and second field oxides are thicker than the first thickness. The method of claim 15, wherein the impurities are separately injected into the area under the tunnel window.