KR100186532B1 - Hdtv high speed channel equalizer - Google Patents

Abstract

The present invention relates to a high-speed channel equalizer for HDTV which enables to update the tap coefficients of the channel equalizer at the received symbol period.

According to the present invention, since the channel equalizer uses a coefficient updating circuit smaller than the number of taps of the equalizer and uses only one entrance when downloading the updated coefficient to the filter, the channel equalizer operates at the same processing speed as the input data. In the channel equalizer for removing noise included in the input signal in consideration of the fact that the channel equalizer converges or becomes very late, the first storage unit stores the input data shifted by a predetermined unit and delayed. An error calculator for calculating an error based on a machine calculated coefficient and data stored in the first storage unit, and a second storage for storing the input data corresponding to the error calculation time while calculating the error in the error calculator. A new coefficient is updated using data stored in the second storage unit and an error value calculated by the error calculator. And a multiplication unit for multiplying the updated coefficient and the data stored in the first storage unit, and an adder for adding operation results of the multiplication unit.

Description

High-Speed Channel Equalizer for HDTV

1 is a block diagram of a general digital filter.

2 is a block diagram of the coefficient storage unit of FIG.

3 is a block diagram of a conventional channel equalizer using the filter of FIG.

4 is a signal transmission format of HDTV.

5 is a block diagram of a high-speed channel equalizer for HDTV according to the present invention.

6 is a block diagram of the filter of FIG.

7 is a block diagram of a converging / diffusing checker of FIG.

8 is a configuration diagram of the error processing unit in FIG.

9 is a diagram showing a range of errors according to each state in the present invention.

* Explanation of symbols for main parts of the drawings

11 filter 11a memory for data

11b: delay memory 11c: coefficient update unit

11d: multiplier 11e, 12b: adder

12: error detection unit 12a: decision unit

13: convergence / divergence checker 13a: squared part

13b: average value output section 13c, 13d: comparison section

14: error processing unit 14a: shifter

The present invention relates to a channel equalizer for HDTV, and more particularly, to a high-speed channel equalizer for HDTV, which enables the tap coefficient of the channel equalizer to be updated at a received symbol period.

Digital filters, which are commonly used, are modeled and used as linear systems as shown in FIG.

The digital filter modeled in this way has a huge size of 1 chip with 8 bits of data and 288 taps when the filter coefficient is 10 bits.

FIG. 1 shows a Finite Impulse Response (FIR) filter, which is a representative digital filter. The input data (din) is input to a data memory (1-1 ─ 1-N) consisting of successive flip-flops, and the system clock is shifted. Each time it is transitioned, it continues to shift in the direction of the arrow on the right.

And the data (din, ₁ , din, ₂ , ..., din, _n ) stored in the data memory (1-1-1-N) 1) and the counting memory (2- The filter coefficients (C ₀ , C ₁ , .........., C _n-1 ) stored in 2 ─ 2-N are multiplied by the multiplier (3-1 ─ 3-N) The total n filter taps are added by the adder 4 and then output.

At this time, an address signal indicating the number of taps from the coefficient memory 2-1 ─ 2-N externally to load the value of the filter coefficient Cin into the counting memory 2-1 ─ 2-N. ) And the coefficient (Cin) are entered.

That is, the digital filter uses the coefficient (Cin) and the address to filter out the filter coefficients (C ₀ , C ₁ , ....., C _n-1 ) for each tap input externally and shifts the data for each tap ( din, ₁ , din, ₂ , ...... din, _n ), and then adds the results of all taps.

On the other hand, for adaptive filtering, two counting memories 2-1 to 2-N are configured in parallel as shown in FIG. 2, and then a working bank is formed using a bank select signal bs1. It is divided into and shadow banks.

That is, if the coefficient Ck1 currently stored in the memory 2a is output through the multiplexer MUX1 by the bank selection signal bs1, the memory 2b is defined as a shadow bank and externally provided by the address and the coefficient Cin. In this case, the memories 2a and 2b receive an address through the address decoder 2c. If the coefficients of (C ₁ , ₂ , C ₂ , ₂ ,... C _n-1 , ₂ ) are changed to the new coefficients for all n taps, the bank selection signal bs1 is inverted. Change the shadow bank.

That is, this time, the memory 2b becomes a working bank, and the coefficients Ck and 2 stored in the memory 2b are outputted through the multiplexer MUX1 by the bank selection signal bs1, and the memory 2a is a shadow bank. It is possible to update to new coefficients (C ₁ , ₂ , C ₂ , ₂ ,... C _n-1 , 2) from the outside.

In this way, the filter coefficients can be updated without affecting the current filter operation. When the update is completed, the coefficient bank is changed to operate the filter using the new coefficients.

FIG. 3 shows a channel equalizer according to the Least Mean Square (LMS) algorithm using the filter of FIG. 1. In the channel equalizer, the coefficients of the channel equalizer are updated and equalized in the same period as theoretically input data. The data should be output at the same time.

However, in the actual hardware design, there should be a coefficient updater 5 for coefficient calculation and update, and a channel equalization filter 6 for equalizing the actual input data using the coefficients passed from the coefficient updater 5. There is a control unit 7 which controls the operation of the channel equalization filter 6 and the coefficient updating unit 5 and the data in the coefficient updating unit 5 and the coefficient memories 5a, 5b, and the like.

In the above, the coefficient updater 5 cannot make the coefficient calculation and update as fast as the data input speed.

This is because the channel equalizer must update the coefficients for all filter taps as shown in the following equation (1), because in the actual circuit, there is only one set of coefficient calculation unit 5c for coefficient update of the coefficient updater 5. .

Here, C _k is the coefficient of the k-th tap of the filter, △ is the step size which is a factor used when updating the filter coefficients, error is an error signal input from the outside, din, _k is the k-th tap This is the data stored in.

That is, in order to satisfy the above formula (1), the coefficient updater 5 must be equal to the number of taps of the channel equalizer, but it is difficult to do so in a hardware design.

Therefore, the coefficient updater 5 stores the necessary section among the input data of the equalizer in the data storage memory 5a, and then outputs the data at a speed as slow as the number of taps of the equalizer, unlike the channel equalization filter 6. Input it to the filter 5d.

The remaining coefficient updater 5 then updates the coefficients using the output of the filter 5d and operates the filter 5d with the updated coefficients.

That is, the data is processed at a slow speed in order to satisfy the condition of Equation (1).

The total tap coefficient of the channel equalizer calculated in this way is downloaded to the shadow bank of the channel equalization filter 6 according to the bank selection concept shown in FIG. 2, and the bank selection signal is changed if it is changed to a new coefficient across all taps. The inversion is performed to switch the working bank and the shadow bank of the filter of the channel equalization filter 6.

Accordingly, the channel equalization filter 6 operates with the updated coefficient.

Meanwhile, according to the HDTV standard of the GA (Grand Alliance), the HDTV transmission system uses VSB (Vestigial Sideband), which is transmitted in the format shown in FIG.

In addition, since the conventional channel equalizer operates in the same concept as in FIG. 3, the channel equalizer coefficient of one tap per symbol is updated. Therefore, due to the limitation of the operation speed of the channel equalizer, the actual channel equalizer of FIG. The data (260416 / n) obtained by dividing the data response total data (260416 symbols) used for the coefficient update of the equalizer by the number of taps n of the channel equalizer cannot be exceeded.

That is, if n = 256 taps, 1017 pieces of data are used for coefficient update of the channel equalizer among data of one frame.

As described above, in the conventional channel equalizer, a coefficient update circuit smaller than the number of taps of the equalizer is used, and the channel equalizer operates at the same processing speed as the input data because only one gate is used to download the updated coefficient to the filter. Because of this, there was a disadvantage that the convergence of the channel equalizer or very late.

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and an object of the present invention is to converge at high speed by using a filter with a built-in coefficient update function so that coefficient updates are made at the same processing speed as data for all taps of the equalizer. To provide a high-speed channel equalizer for HDTV.

A feature of the present invention for achieving this object is a filter having a coefficient update function for updating coefficients of input data and error signals by itself, an error detector for obtaining an error signal from the output of the filter, and the error detector. A hunting / diffusion checking unit for checking convergence and divergence from the error signal output of the output unit and outputting a convergent or diverging signal, and shifting down the error signal of the error detection unit by a predetermined bit according to the converged signal output of the convergence / diffusion checking unit An HDTV high-speed channel equalizer comprising an error processing unit for outputting an error signal having a smaller magnitude than the error signal to the filter.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram of a high-speed channel equalizer for HDTV according to the present invention, and includes a filter 11 having a coefficient update function and an error detector 12 for obtaining an error signal from the output of the filter 11. And a convergence / divergence checking unit 13 for outputting a convergence or divergence signal by checking convergence and divergence from the error signal output of the error detection unit 12, and a convergence signal of the convergence / divergence checking unit 13; An error processor 14 outputs an error signal having a smaller magnitude than the error signal inputted by a predetermined bit shift down of the error signal of the error detector 12 according to the output.

As shown in FIG. 6, the filter 11 includes a data memory 11a in which input data is sequentially stored, and a delay memory for delaying the input data by a delay clock when calculating an error signal. A coefficient updating unit 11c for performing coefficient updating using the data output of the delay memory 11b and an input error signal error, and a coefficient updated by the coefficient updating unit 11c; And a multiplier 11d for multiplying the corresponding output data of the data memory 11a, and an adder 11e for adding the outputs of the respective multipliers 11d.

In addition, the error detection unit 12 includes a decision unit 12a for outputting the decision data from the output of the filter 11, the output of the filter 11 and the decision of the decision unit 12a. And an adder 12b for adding an data output and outputting an error signal.

As shown in FIG. 7, the convergence / difference checking unit 13 calculates a square unit 13a for obtaining a square of an error signal input from the error detector 12 and outputs the square unit 13a. The average value output section 13d comprising an adder 13b and a memory 13c accumulating and outputting the mean square error and the output of the average value output section 13d are compared with a set reference value to output the average value. If the output of the unit 13d is smaller than the reference value, the output is enabled by the comparator 13e for outputting the converged signal and the output of the first converged signal of the comparator 13e, and the output of the average value output part 13d. Is compared with the set reference value and is larger than the reference value, and comprises a comparator 13f for outputting the divergence signal as an initialization signal of the filter 11.

In addition, the error processing unit 14 includes a one-bit shifter 14a for shifting down an error signal input by the convergence signal diverging unit 13 as shown in FIG. 8. .

In the present invention configured as described above, the coefficient update unit 11c of the filter 11 includes data delayed by the delay according to the error signal of the filter and the error signal calculation process outside the filter, that is, the input data is the data memory 11a. The new filter coefficient is calculated using the data stored in the delay memory 11b.

The output of the coefficient updater 11c is multiplied by the corresponding data output of the data memory 11a by the multiplier 11d, and then added by the adder 11e to finally output the equalized data.

On the other hand, the error detector 12 adds the output of the filter 11 and the decision data output of the decision unit 12a by the adder 12b to obtain an error signal.

The error signal is input to the convergence / ideal checking unit 13 and used for checking convergence and divergence.

That is, the convergence / difference checking unit 13 takes the square of the error signal from the square unit 13a and inputs it to the average value output unit 13d.

Accordingly, the average value output section 13d accumulates the output of the square section 13a in the memory 13c through the adder 13b, and then takes the average value and outputs it to the comparison sections 13e and 13f.

Accordingly, the comparison unit 13e compares the set reference value with the output of the average value output unit 13d and outputs a converged signal when the output of the average value output unit 13d is smaller than the reference value.

When the converged signal is output, the error processor 14 shifts down the error signal input from the error detector 12 by the 1-bit shifter 14a and outputs the shifted signal.

When shifting down in this manner, the error signal changes to a small size as shown in (c) of FIG. 9, and the lower 1-1 bits are ignored in the original error signal of (b).

9 (a) shows the range of error signals inputted from the filter 11, (b) shows the range of error signals inputted to the filter 11 in the normal state, and (c) shows convergence. The range of the error signal to be input to the filter 11 in the state is shown.

In this part, since the channel equalizer operates more accurately only when the equation (1) shown in the conventional description is performed as in the following equation (2), this method is used in the existing channel equalizer.

However, the channel equalizer of the present invention operates at a much higher speed than the conventional channel equalizer. Therefore, in the converged state, the step equalizer must be processed as Δ / 2 ¹ in the coefficient update process as shown in Equation 3 below. 11) it is to update the coefficients of the error processing unit 14 to shift down one bit error as an error / ²¹ in the equalizer as the following expression (4) based on the outside.

This can bring about an effect of Δ / 2 ^{1 in} a situation where the channel equalizer has converged without increasing the amount of calculation and the size of the circuit inside the filter 11.

In addition, the performance degradation according to the implementation methods of Equations (3) and (4) is compensated because the channel equalizer of the present invention operates at a much higher speed than the conventional channel equalizer.

On the other hand, the comparison section 13f compares the set reference value with the output of the average value output section 13d and outputs a divergence signal when the output of the average value output section 13d is larger than the reference value.

At this time, the comparator 13f is enabled by the first converged signal output of the comparator 13e so as to output an divergence signal only after the convergence signal of the comparator 13e is outputted at least once, and thus emits a divergence signal. Will print.

In other words, if the channel equalizer starts to operate and converges, then there is a change in the HDTV receiving channel and the channel equalizer exits from the converged state instantaneously. The operating method changes from Eq. (4) to Eq. (3), which is the reverse process of Eq. (4), and converges again at a high speed. However, in case of an unexpected situation, the divergence / diffusion checking unit 13 diverges. Will output a signal.

Once it is detected that the channel equalizer is in the diverging state, this signal is input to the initialization signal of the filter 11, and the coefficient of the center tap becomes 1.0 by the operation of the coefficient updater 11C inside the filter 11. After the remaining tap coefficients are initialized to 0.0, the equalization operation is performed again.

The converging / diffusing checking unit 13 operates only in the field sync period among the HDTV transmission frames of FIG.

Because this interval is a training sequence interval, which data is received from the receiver is determined in advance so that an accurate average value can be calculated.

As described above, the present invention has a smaller size than the existing channel equalizer, so that the coefficients of all taps of the channel equalizer are updated all at once with the same period as the input data, so that the convergence speed is fast and stable even when the reception channel changes. .

Claims (4)

A channel equalizer for removing noise included in an input signal, comprising: a first storage unit for storing delayed input data shifted by a predetermined unit, and calculating an error based on a calculated coefficient and data stored in the first storage unit An error calculation unit, a second storage unit for storing the input data corresponding to an error calculation time while the error calculation unit calculates an error, data stored in the second storage unit, and an error value calculated by the error calculation unit A coefficient updating unit for updating new coefficients using a multiplier, a multiplication unit for multiplying the updated coefficients with the data stored in the first storage unit, and an adder for adding operation results of the multiplication unit, respectively. group. The high-speed channel equalizer of claim 1, wherein the error calculator comprises a shifter for shifting down a fixed bit. The high-speed channel equalizer of claim 1, wherein the channel equalizer further comprises a state checker that determines whether an output state of the adder is in an divergent state or a convergent state. Storing delayed input data while shifting input data input by a predetermined unit to a first storage unit having a plurality of memories; calculating an error based on a calculated coefficient and data stored in the first storage unit; Storing the input data in a second storage unit in correspondence with a time for calculating an error, updating a coefficient using data stored in the second storage unit and an error value calculated in the error calculator; And multiplying the updated coefficient by the data stored in the first storage unit, and adding the multiplied values to the channel equalization method of the high-speed channel equalizer for the HDTV.