KR0185601B1 - Inter data communication processor - Google Patents

Abstract

1. Fields to which the invention described in the claims belong

The present invention relates to a data communication circuit for data transmission between two processors having different processing speeds.

2. Technical problem to be solved by the invention

The use of dual-port RAM improves the impact on other circuits by affecting the basic tasks of processors or by simultaneously reading and writing the same address, resulting in an instantaneous increase in power consumption.

3. Summary of Solution to Invention

The transmission and reception modes of the first and second processors for communicating through the first and second memories having a single input / output port are correspondingly selected, respectively. 2 Generates read and write addresses for accessing the memory. Also, data storage states of the first and second memories are detected from the change of the read and write addresses, and the first and second processors are detected, and one of the read and write addresses is selected according to the data storage states of the first and second memories. The first and second memories are applied to the first and second memories, respectively, and the data on one of the data buses of the first and second processors are selected and provided to the first and second memories according to the selected mode. In addition, the operation mode of the first and second memories is controlled by the selected transmission / reception mode and the read and write addresses, and the data output from the memory in the read mode is selected to be provided on the data bus commonly provided to the first and second processors. To apply.

4. Important uses of the invention

The processing speed in a system is used to transfer data between different processors without affecting their basic tasks.

Description

Interprocessor data communication circuit

1 is a diagram showing an application example of an interprocessor data communication circuit according to the present invention;

2 is a block diagram of an interprocessor data communication circuit according to the present invention;

3 is a detailed circuit diagram of the mode selection circuit 200 in FIG. 2.

4 is a detailed circuit diagram of the first address generation circuit 202 of FIG.

5 is a detailed circuit diagram of the second address generation circuit 204 of FIG.

6 is a detailed circuit diagram of the status display circuit 206 in FIG.

FIG. 7 is a detailed circuit diagram of the first address selection circuit 208 of FIG.

FIG. 8 is a detailed circuit diagram of the second address selection circuit 210 of FIG.

9 is a detailed circuit diagram of the data selection circuit 212 of FIG.

FIG. 10 is a detailed circuit diagram of the memory control circuit 220 of FIG.

11b of FIG. 11a and FIG. 2 is an operation timing diagram of the first and second memories 214 and 216. FIG.

12A and 12B are timing diagrams of data transmission and reception operations of the present invention.

* Explanation of symbols for main parts of the drawings

100: CPU 102: data communication circuit

104: DSP 200: mode selection circuit

202 and 204: first and second address generating circuits 206: state detection circuit

208, 210: first and second address selection circuits 212: data selection circuits

214, 216: first and second memory 218: output selection circuit

The present invention relates to a data communication circuit between processors, and more particularly, to a circuit for data transfer between two processors having different processing speeds.

In general, in a system such as a voice mailing system (VMS), two processors having different processing speeds in one system need to transfer data without being affected by their basic job. For example, processors having such a relationship in a system include a central processing unit (CPU) and a digital signal processor (DSP).

As such, dual port RAMs have been used to transfer data between two processors having different processing speeds without being affected by their basic tasks. The two ports of the dual port RAM are controlled independently of each other by separate address inputs and control inputs.

However, when using dual port RAM as described above, IC chip size is not only large, and there is no interrupt or flag signal to inform read / write status of dual port RAM. By doing so, there is a problem that the communication speed is lowered or the processing speed of other tasks is affected. In addition, when simultaneously reading and writing the same address for the dual port RAM, power consumption increases instantaneously, which causes a bad effect on other circuits using the same power supply.

Accordingly, an object of the present invention is to provide a data communication circuit between processors that can perform data communication without affecting each task without using dual port RAM between two processors having different processing speeds.

Another object of the present invention is to provide an interprocessor data communication circuit capable of improving communication efficiency by notifying two processors of a read / write state of a memory.

The circuit of the present invention for achieving the above objects has a memory area of a certain size, each of the first and second memory having a single input and output port, and two of the first and second processors having different processing speeds A mode selection circuit for selecting the transmission and reception modes of the first and second processors corresponding to each other according to the mode signal applied from one, and the first and the second requests at the request of the processor selected as the transmission mode among the first and second processors. A first address generation circuit for generating a read address for reading data from the two memories, and a write for writing data to the first and second memories at the request of a processor selected as a reception mode among the first and second processors; A second address generating circuit for generating an address and a data storage state of the first and second memories from the change of the read address and the write address to detect the first and second buffers; A state detection circuit for notifying the processor, first and second address selection circuits for selecting one of a read address and a write address according to the data storage states of the first and second memories and applying them to the first and second memories, respectively; A data selection circuit which selects data on one of the data buses of the first and second processors and applies it to the first and second memories in response to the selected mode, and operates in the read mode of the first and second memories; An output selection circuit for selecting data to be output from one memory to be applied to a data bus commonly provided to the first and second processors, and the first, And a memory control circuit for controlling the operation mode of the second memory and for controlling the output selection circuit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the following description, it should be noted that like elements in the drawings represent like reference numerals wherever possible. Also, in the following description, numerous specific details such as specific circuit configurations, number of bits or bytes, frequency, logic states, etc. are shown to provide a more general understanding of the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

First, the embodiment of the present invention is an example that is applied to the case of data communication between the CPU and the DSP as a processor having different processing speeds. FIG. 1 shows an example of transferring data through the data communication circuit 102 between the CPU 100 and the DSP 104 in this way.

2 is a block diagram of a data communication circuit 102 according to the present invention for data communication between the CPU 100 and the DSP 104 as described above. Unlike the dual port RAM used in the related art, FIG. The first and second memories 214 and 216 have a single input / output port, that is, one data input terminal DIN and one data output terminal DO. In addition, the configuration of FIG. 2 illustrates a case where the first and second memories 9214 and 216 use a RAM having a memory area of 64 words, respectively, and control logic for the RAM enable terminal RAMEN and the write enable terminal WE. Use general purpose RAM that requires only logic. Therefore, in the embodiment of the present invention, data is written or read in the first and second memories 214 and 216 in units of one word, that is, 16 bits, and the address is applied in 6 bits.

The mode selection circuit 200 selects one of the transmission / reception mode and the test mode corresponding to each other of the CPU 100 and the DSP 104 by the transmission / reception mode signal TX / RX and the test mode signal TEST applied from the CPU 100. Selects and generates a CPU select signal CPU_SEL and a DST read select signal DSP_RD_SEL accordingly. The transmit / receive mode signal TX / RX is applied low when the DSP 104 is in transmit mode and the CPU 100 is in receive mode, and is high when the CPU 100 is in transmit mode and the DSP 104 is in receive mode. Is approved. The test mode signal TEST is applied high when the test mode for testing the first and second memories 214 and 216 is performed by the CPU 100, and when data is transmitted and received between the CPU 100 and the DSP 104. Is applied low.

The first address generating circuit 202 reads a 7-bit read address RA [] for reading data from the first and second memories 214 and 216 at the request of a processor selected from the CPU 100 and the DSP 104 in the transmission mode. 6: 0]. The first address generating circuit 202 selects and inputs the CPU read signal CPU_RD or the DSP read signal DSP_RD by the DSP read select signal DSP_RD_SEL, and the read address RA [6: 0] by the input CPU read signal CPU_RD or the DSP read signal DSP_RD. ]. The CPU read signal CPU_RD is a signal for the CPU 100 to read data from the first and second memories 214 and 216. The DSP read signal DSP_RD is a signal for the DSP 104 to read data from the first and second memories 214 and 216. This signal is for reading.

The second address generation circuit 204 writes a 7-bit write address WA [for writing data to the first and second memories 214 and 216 according to a request of a processor selected from the CPU 100 and the DSP 104 in the reception mode. 6: 0]. The second address generating circuit 204 selects and inputs the CPU write signal CPU_WR and the DSP write signal DSP_WR by the DSP read select signal DSP_RD_SEL, and writes the write address RA [6: 0] by the input CPU write signal CPU_WR or the DSP write signal DSP_WR. ]. The DSP write signal DSP_WR is a signal for the DSP 104 to write data to the first and second memories 214 and 216. The CPU write signal CPU_WR is for the CPU 100 to write data to the first and second memories 214 and 216. Signal to write.

The state detection circuit 206 stores the data storage states of the first and second memories 216 and 218 from the change of RA6, which is the most significant bit of the read address RA [6: 0], and WA6, which is the most significant bit of the write address WA [6: 0]. The first and second ready signals RDY1 and RDY2, the flag signals RDY_FLG, and the interrupt signal RDY_INT are generated according to the transmission / reception mode signals TX / RX. The first and second ready signals RDY1 and RDY2 are signals indicating data storage states of the first and second memories 214 and 216, respectively, and the flag signal RDY_FLG is read to the processor in the receiving mode of the CPU 100 or the DSP 104. A signal for notifying the start, and the interrupt signal RDY_INT is a signal for notifying the write start to the processor in the transmission mode of the CPU 100 or the DSP 104.

The first address selection circuit 208 has a six-bit read address RA [5: 0], a six-bit write address WA [5: 0], and a six-bit address SA [5: 0] on the address bus of the CPU 100. ] Is selected by the test mode signal TEST and the first preparation signal RDY1 and applied to the first memory 214.

The second address selection circuit 210 sets one of the read address RA [5: 0], the write address WA [5: 0], and the address SA [5: 0] of the CPU 100 to the test mode signal TEST and the second preparation. The signal is selected by the signal RDY2 and applied to the second memory 216.

The data selection circuit 212 is configured to select one of the data bus SD [15: 0] of the CPU 100 and the data bus DSP_BUS [15: 0] of the DSP 104 in response to the mode selected among the transmission, reception, and test modes. Data on the data bus is selected and applied to the first and second memories 214 and 216. The data selection circuit 211 selects data on one of the data buses SD [15: 0] and data bus DSP_BUS [15: 0] by the CPU selection signal CPU_SEL and the DSP write signal DSP_WR.

The memory control circuit 220 controls the operation modes of the first and second memories 214 and 216 and the output selection circuit 218 according to the selected song and reception mode and the read address and the write address. The memory control circuit 220 includes the CPU selection signal CPU_SEL, the DSP read selection signal DSP_RD_SEL, the read address RA6, the write address WA6, the CPU read signal CPU_RD, the DSP read signal DSP_RD, the CPU write signal CPU_WR, the DSP write signal DSP_WR, and the CPU 100. The first and second RAM enable signals RAMEN1 and RAMEN2 and the first and second write enable signals WE1 and WE2 are generated by the address bus SA6 and the test mode signal TEST. The first RAM enable signal RAMEN1 and the first write enable signal WE1 are signals for controlling the first memory 214, and the second ram enable signal RAMEN2 and the second write enable signal WE2 are used to control the second memory 216. This signal is for

The output selection circuit 218 selects the 16-bit data output from one of the first and second memories 214 and 216 in the read mode by the read select signal RD_SEL to select the CPU 100 and the DSP 104. It is applied on the data bus DO [15: 0], which is provided in common. The output selection circuit 218 uses a multiplexer. When the read select signal RD_SEL is applied low, the output select circuit 218 selects data output from the first memory 214 and when the read select signal RD_SEL is applied high, the second memory ( 216) select the data to be output.

3 is a detailed circuit diagram of the mode selection circuit 200 in FIG. 2 and includes an inverter 300, an end gate 302, and an ora gate 304.

4 is a detailed circuit diagram of the first address generation circuit 202 of FIG. 2 and includes a multiplexer 400 and a counter 402.

FIG. 5 is a detailed circuit diagram of the second address generation circuit 204 in FIG. 2 and includes a multiplexer 500 and a counter 502.

FIG. 6 is a detailed circuit diagram of the state display circuit 206 of FIG. And a multiplexer 642. The clock signal CLK has a frequency of 16 MHz.

FIG. 7 is a detailed circuit diagram of the first address selection circuit 208 of FIG. 2 and includes multiplexers 700 and 702.

FIG. 8 is a detailed circuit diagram of the second address selection circuit 210 of FIG. 2 and includes multiplexers 800 and 802.

9 is a detailed circuit diagram of the data selection circuit 212 in FIG. 2 and includes a latch circuit 900 and a multiplexer 902.

FIG. 10 is a detailed circuit diagram of the memory control circuit 220 of FIG. 2. The inverters 1000, 1002, 1010, 1012, and 1026, the multiplexers 1004, 1006, 1014, 1016, and 1024, and the demultiplexers 1008 and 1018 are illustrated in FIG. And OA gates 1020, 1022, 1028, and 1030.

In FIGS. 4 through 10, the multiplexers 400, 500, 642, 700, 702, 800, 802, 902, 1004, 1006, 1014, 1016, 1024 select and output a signal input to the input terminal A when the signal applied to the selection terminal S is Roy. When the signal applied to the terminal S is high, the signal input to the input terminal B is selected and output. In addition, the demultiplexers 1008 and 1018 output the input signal through the output terminal Q0 when the signal input to the selection terminal S is low, and output the input signal when the signal input to the selection terminal S is low, the output terminal Q1. Output through The unsigned POR is a signal for initializing the counters 402 and 502 and the flip-flops 602, 604, 610, 612, 618, 624, 632, 638 and 642 as low power-on reset signals.

Hereinafter, an operation example of FIGS. 2 to 10 according to the present invention will be described in detail.

First, the operation mode of the present invention is a mode for transferring data from the DSP 104 to the CPU 100, a mode for transferring data from the CPU 100 to the DSP 104, and first and second memories 214 and 216. It is divided into test mode for testing. The operation mode is divided by the signal transmission / reception mode signal TX / RX and the test mode signal TEST, and is selected by the mode selection circuit 200. These signals can be set by recording in the initialization register of the CPU 100. Hereinafter, each operation mode will be described separately.

First, the case where the first and second memories 214 and 216 are tested by the CPU 100 will be described. In this case, the CPU 100 generates the test mode signal TEST high, and writes data to the first and second memories 214 and 216, and then reads the data, thereby directly testing the first and second memories 214 and 216. .

The CPU 100 selects one of the first and second memories 214 and 216 through the memory control circuit 220 by the most significant bit SA6 of the address bus SA [6: 0]. If memory 214 is selected and SA6 is high, second memory 216 is selected. The CPU 100 continuously writes the first and second memories 214 and 216 in word units up to 64 words, respectively, by the CPU write signal CPU_WR applied to the second address generation circuit 204, and then the first address generation circuit. The first and second memories 214 and 216 are tested by reading with the CPU read signal CPU_RD applied to 202. At this time, the operation timing for reading or writing data to the first and second memories 214 and 216 is the same as those in FIGS. 11a and 11b. FIG. 11a shows the operation timing during a write cycle. The operation timing at the read cycle is shown, and the operation timing of the conventional RAM as described above is shown.

Secondly, a case of transferring data from the DSP 104 to the CPU 100 will be described. In this case, the CPU 100 generates the test mode signal TEST low and the transmit / receive mode signal TX / RX high, so that the DSP 104 enters the transmission mode by the mode selection circuit 200 and the CPU 100 receives the reception mode. do.

First, the DSP 104 writes data to be transmitted to the first memory 214 or the second memory 216 every 8 KHz by using the DSP write signal DSP_WR applied to the second address generation circuit 204. At this time, only the first RAM enable signal RAMEN1 of the memory control circuit 220 is enabled until the first memory 214 becomes full, that is, while the write address WA6 is low, and the second RAM enable signal. Since RAMEN2 is kept low, data is written only to the first memory 214. If 64 words are written continuously, the first memory 214 becomes full. Then, as the first preparation signal RDY1 of the state detection circuit 206 becomes high, the flag signal RDY_FLG also becomes high and is applied to the CPU 100 to notify the CPU 100 of the full state of the first memory 214. When the DSP 104 continuously writes to the first memory 214 and writes the 65th write, the write address WA6 automatically becomes high. Therefore, the second RAM enable signal RAMEN2 is enabled to write data to the second memory 216. Will be. Accordingly, since the DSP 104 only needs to write unconditionally without counting the number of words to be written, the burden can be reduced. In general, since the DSP 104 is slower than the CPU 100, the DSP 104 only needs to be written unconditionally.

The CPU 100 reads by the flag signal RDY_FLG of high as the first preparation signal RDY1 or the second preparation signal RDY2 becomes high. Even if the CPU 100 does not know which of the first and second memories 214 and 216 to read, there is no burden because the internal read address RA [5: 0] is automatically assigned. When the CPU 100 reads all of the first memory 214, the read address RA6 becomes high and the first reset signal RST1 of the state detection circuit 206 falls low due to the clock signal CLK, causing the read address WA6 to become high. Makes the first ready signal RDY1 held low to low.

In this case, since the first and second ready signals RDY1 and RDY2 of the state detection circuit 206 are initially low, the address is first designated by the write address WA [5: 0], and then the first ready signal when the write address WA6 becomes high. RDY1 becomes high and from this point on, the first memory 214 is ready to be read.

As shown in FIG. 12, the operation timing chart when transferring data from the DSP 104 to the CPU 100 is as shown in FIG. 12A.

Third, a case of transferring data from the CPU 100 to the DSP 104 will be described. In this case, the CPU 100 generates the test mode signal TEST low and the transmit / receive mode signal TX / RX low, so that the CPU 100 enters the transmission mode by the mode selection circuit 200 and the DSP 104 enters the reception mode. do. At this time, the basic operation is the same as the second.

First, when the CPU 100 selects the operation mode and writes data for 64 words, the flag signal RDY_FLG of the state detection circuit 206 becomes high. The DSP 104 periodically polls the flag signal RDY_FLG and if it is active high, the DSP 104 considers the data to be filled in the first memory 214 or the second memory 216, and then reads data every 8 KHz. I'm going.

In this case, the CPU 100 may write data to the second memory 216 even while the DSP 104 accesses the first memory 214. At this time, since the speed of reading by the DSP 104 is slow, the CPU 100 can continue to perform other tasks after writing all the data to the first and second memories 214 and 216. When the DSP 104 reads all data stored in the first and second memories 214 and 216, the state detection circuit 206 informs the CPU 100 that the first and second memories 214 and 216 are empty. Interrupt signal RDY_INT is generated. The CPU 100 then starts writing data again from then on.

As shown in FIG. 12, the operation timing diagram when data is transferred from the CPU 100 to the DSP 104 is shown.

As described above, the present invention enables data communication between two processors having different processing speeds without affecting each task without using dual port RAM, as well as providing two read / write states to the memory. It is an advantage to improve the communication efficiency by notifying the processor.

Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications can be made without departing from the scope of the present invention. In particular, although the embodiment of the present invention illustrates the case of transferring data between the CPU and the DSP, it is applied without special modification between two processors having different processing speeds. Therefore, the scope of the invention should not be defined by the described embodiments, but should be understood as equivalents of the claims and the claims.

Claims (8)

An interprocessor data communication circuit for transferring data between two first and second processors having different processing speeds, comprising: first and second memory means each having a constant size memory area and having a single input / output port; Mode selection means for selecting the transmission and reception modes of the first and second processors corresponding to each other by a mode signal applied from one of the first and second processors, and transmission of the first and second processors. A first address generating means for generating a read address for reading data from the first and second memory means according to a request of a processor selected as a mode, and a request of a processor selected as a reception mode among the first and second processors; Second address generating means for generating a write address for writing data to said first and second memory means; State detection means for detecting a data storage state of the first and second memory means from the change of the write address and informing the first and second processors, and one of the read address and the write address to the first and second memory. Data of one of the first and second address selecting means selected according to the data storage state of the means and applied to the first and second memory means, and the data buses of the first and second processors corresponding to the selected mode. A data selection means for selecting data on a bus and applying it to the first and second memory means; and selecting data output from one memory means operated in a read mode among the first and second memory means. Output selection means for applying on a data bus commonly provided to a second processor, the selected transmission / reception mode and the read address and write address. And memory control means for controlling the operation modes of said first and second memory means and controlling said output selection means. The inter-processor data communication circuit according to claim 1, wherein said state detecting means detects a full state and an empty state of said first and second memory means. 3. The method of claim 2, wherein the first and second address selecting means selects the write address when the memory means corresponding to each of the first and second memory means indicates an empty state. An interprocessor data communication circuit for selecting a read address. 4. The interprocessor data communication circuit according to claim 3, wherein said first and second memory means are RAM. An interprocessor data communication circuit for transferring data between a CPU and a DSP having different processing speeds, the first and second memory means each having a predetermined size memory area and having a single input / output port, and applied from the CPU. Mode selection means for selecting one of a transmission, reception mode, and a test mode corresponding to each other of the CPU and the DSP by the mode signal, and the first and the second according to a request of a processor selected as a transmission mode among the CPU and the DSP. First address generating means for generating a read address for reading data from the memory means, and a write address for writing data to the first and second memory means at the request of a processor selected as a reception mode among the CPU and DSP; Second address generating means for generating a first address, and the first and second memos from the change of the read address and the write address. Status detection means for detecting a data storage state of the means and informing the CPU and DSP, and one of the read address, the write address, and the address on the address bus of the CPU according to the data storage state of the first and second memory means. First and second address selecting means for selecting and applying the first and second memory means to the first and second memory means, respectively, and selecting data on one data bus of a data bus of a CPU and a DSP corresponding to the selected mode. Data selection means applied to the second memory means and data output from one memory means operated in the read mode among the first and second memory means are selected to be provided on the data bus commonly provided to the CPU and DSP. The first and second memory means are moved by the output selection means to be applied, the selected transmission and reception mode and the read address and write address. A control mode, and inter-processor data communication circuit comprising: a memory control means for controlling the output selection means. 6. The inter-processor data communication circuit as claimed in claim 5, wherein said state detecting means detects a full state and an empty state of said first and second memory means. 7. The method of claim 6, wherein the first and second address selecting means selects the write address when the memory means corresponding to each of the first and second memory means indicates an empty state. And selecting an address on the address bus of the CPU according to the control signal of the CPU when the read address is selected and the test mode is selected. 8. The interprocessor data communication circuit according to claim 7, wherein said first and second memory means are RAM.