KR0184054B1 - Method for forming of metal level interconnections in semiconductor device - Google Patents
Method for forming of metal level interconnections in semiconductor device Download PDFInfo
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- KR0184054B1 KR0184054B1 KR1019950031900A KR19950031900A KR0184054B1 KR 0184054 B1 KR0184054 B1 KR 0184054B1 KR 1019950031900 A KR1019950031900 A KR 1019950031900A KR 19950031900 A KR19950031900 A KR 19950031900A KR 0184054 B1 KR0184054 B1 KR 0184054B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
본 발명을 위한 반도체 장치의 금속배선층 형성방법은 하부배선층을 가지는 기판 상에 절연막을 형성시키는 단계와, 상기 절연막을 패터닝하여 상기 하부배선층을 노출시키는 접촉창을 형성하는 단계와, 상기 접촉창과 상기 절연막 상에 제1도전층을 형성시키는 단계와, 상기 제1도전층 상에 식각선택성이 큰 저점도물질을 상기 접촉창이 매립되도록 증착하여 저점도 물질층을 형성하는 단계와, 상기 저점도물질층을 상기 접촉창 내에만 잔류되도록 이방성식각하되 상기 절연막 상의 제1도전층도 식각하여 상기 접촉창 상부 측에 오버행된 부위를 제거하는 단계와, 상기 저점도물질층을 제거하고 상기 접촉창을 통해 상기 제1도전층과 접촉되게 상기 절연막 상에 제2도전층을 형성시키는 단계를 포함한다.A method for forming a metal wiring layer of a semiconductor device according to the present invention includes forming an insulating film on a substrate having a lower wiring layer, patterning the insulating film to form a contact window exposing the lower wiring layer, and forming the contact window and the insulating film. Forming a low viscosity material layer by forming a first conductive layer on the first conductive layer, depositing a low viscosity material having high etch selectivity on the first conductive layer so that the contact window is buried, and forming the low viscosity material layer; Anisotropically etching so as to remain only in the contact window, but also etching the first conductive layer on the insulating layer to remove a portion overhanging the upper side of the contact window, removing the low-viscosity material layer, and removing the low viscosity material layer through the contact window. And forming a second conductive layer on the insulating layer in contact with the first conductive layer.
Description
제1도는 종래의 반도체장치의 금속배선층 형성방법을 설명하기 위한 도면.1 is a view for explaining a metal wiring layer forming method of a conventional semiconductor device.
제2도와 제3도는 본 발명에 의한 반도체장치의 금속배선층 형성방법을 설명하기 위한 도면.2 and 3 are views for explaining a method for forming a metal wiring layer of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10, 20, 30 : 반도체기판 11, 21, 31 : 절연막10, 20, 30: semiconductor substrate 11, 21, 31: insulating film
12, 22, 32 : 하부금속배선층 13, 23, 33 : 금속층간절연막12, 22, 32: lower metal wiring layer 13, 23, 33: interlayer insulating film
14, 24, 34 : 접촉창 15, 25, 25', 35, 35' : 하부장벽금속층14, 24, 34: contact window 15, 25, 25 ', 35, 35': lower barrier metal layer
16, 26, 36 : 상부금속배선층 17, 27, 37 : 상부장벽금속층16, 26, 36: upper metal wiring layer 17, 27, 37: upper barrier metal layer
28, 28', 38, 38' : 저점도물질층28, 28 ', 38, 38': Low viscosity material layer
본 발명은 반도체장치의 금속배선층 형성방법에 관한 것으로, 특히 미세한 선폭을 갖는 반도체장치의 다충 금속배선층에서 하부금속층과 상부금속층을 연결시키기 위한 접촉창(contact hole)의 개구부 폭을 넓혀 종횡비가 감소되도록 하여 상부금속층의 단차피복성(step coverage)이 향상되도록 하는 것에 적당하도록 한 반도체장치의 금속배선층 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring layer of a semiconductor device. In particular, in a multi-ply metal wiring layer of a semiconductor device having a fine line width, the width of an opening of a contact hole for connecting a lower metal layer and an upper metal layer is reduced to reduce an aspect ratio. The present invention relates to a method for forming a metal wiring layer of a semiconductor device, which is suitable for improving step coverage of an upper metal layer.
다층의 금속배선층을 갖는 반도체장치에서 상부금속배선층과 하부금속배선층은 접촉창을 통하여 서로 연결되며, 접촉창에 있어서 홀 개구부의 폭과 높이의 비율인 종횡비가 작을수록 상부금속층의 단차피복성이 우수해지고,이로 인하여 배선의 전기전도도가 커져서 신뢰성이 향상된다.In a semiconductor device having a multi-layered metal wiring layer, the upper metal wiring layer and the lower metal wiring layer are connected to each other through a contact window, and the smaller the aspect ratio, which is the ratio of the width and height of the hole opening, in the contact window, the better the step coverage of the upper metal layer. As a result, the electrical conductivity of the wiring increases, thereby improving reliability.
제1도는 종래의 반도체장치의 금속배선층 형성방법을 설명하기 위한 도면으로, 종래의 반도체 장치의 금속배선층 형성방법의 일실시예로 2층 금속배선층의 형성단계를 도시한 도면이다.FIG. 1 is a view for explaining a method for forming a metal wiring layer of a conventional semiconductor device, and illustrates a step of forming a two-layer metal wiring layer as an embodiment of the method for forming a metal wiring layer of a conventional semiconductor device.
종래의 반도체장치의 금속배선층 형성방법에서는, 우선, 제1도의 (a)와 같이, 반도체기판(10) 상의 절연막(11) 위에 형성된 하부금속배선층(12)의 상면에 금속층간절연막(13)을 형성시킨 후에, 금속층간절연막(13)을 사진식각하여 접촉창(14)을 형성시킨다.In the conventional method of forming a metal wiring layer of a semiconductor device, first, as shown in FIG. 1A, an intermetallic insulating film 13 is formed on the upper surface of the lower metal wiring layer 12 formed on the insulating film 11 on the semiconductor substrate 10. After the formation, the metal interlayer insulating film 13 is photo-etched to form the contact window 14.
이때, 하부금속배선층(12)은 절연막(11)의 접촉창(도시하지 않음)을 통하여 반도체기판(11)에 형성된 배선영역(도시되지 않음)과 접촉하고 있다.At this time, the lower metal wiring layer 12 is in contact with a wiring region (not shown) formed in the semiconductor substrate 11 through a contact window (not shown) of the insulating film 11.
이어서 제1도의 (b)와 같이, 접촉장(14)과 금속층간절연막(13)위에 텅스텐티타늄(TiN)등을 증착하여, 금속층간절연막(13) 위에서는 2000Å 정도의 두께를 갖는 접촉창(14)의 저면에서 500Å 정도의 두께를 갖는 하부장벽금속층(15)을 형성시킨다.Subsequently, as shown in FIG. 1 (b), tungsten titanium (TiN) or the like is deposited on the contact field 14 and the intermetallic insulating film 13, and a contact window having a thickness of about 2000 microseconds is formed on the intermetallic insulating film 13 ( At the bottom of 14), the lower barrier metal layer 15 having a thickness of about 500 mm 3 is formed.
이어서 제1도의 (c)와 같이, 하부장벽금속층(15) 위에 상부금속배선층(16)을 형성한다.Subsequently, as shown in FIG. 1C, the upper metal wiring layer 16 is formed on the lower barrier metal layer 15.
그리고 제1도의 (d)와 같이, 상부금속배선층(16) 위에 텅스텐타늄(TiW) 및 질화티타늄(TiN)를 500Å 정도의 두께로 증착하여 상부장벽금속층(17)을 형성시킨다.As shown in FIG. 1D, the upper barrier metal layer 17 is formed by depositing tungsten titanium (TiW) and titanium nitride (TiN) on the upper metal wiring layer 16 to a thickness of about 500 kV.
그러나 종래의 반도체장치의 금속배선층 형성방법에서는 하부장벽금속층을 형성시키기 위한 증착 공정에서 금속층간절연막 위에 텅스텐티타늄(TiW) 또는 질화티타늄(TiN)등을 약 2000Å 정도의 두께가 되도록 증착해야만 접촉창의 저면에 약 500Å 정도의 두께가 증착되므로, 금속층간절연막 위의 하부장벽금속층의 두께가 접촉창 저면의 하부장벽금속층의 두께보다 두껍게 형성되게 되며, 이로 인하여 접촉창에서 상부 모서리에 발생되는 오버행에 의해 상부금속배선막의 단차피복성이 열화로 반도체장치의 동작 불량이 발생되었다.However, in the conventional method of forming a metal wiring layer of a semiconductor device, a tungsten titanium (TiW) or titanium nitride (TiN) or the like is deposited on the interlayer dielectric layer to have a thickness of about 2000 kW in the deposition process for forming the lower barrier metal layer. Since the thickness of about 500Å is deposited on the upper layer, the thickness of the lower barrier metal layer on the interlayer dielectric film is made thicker than the thickness of the lower barrier metal layer on the bottom of the contact window. Deterioration of the step coverage of the metal wiring film has caused a malfunction of the semiconductor device.
즉, 종래의 반도체장치의 금속배선층 형성방법에서는 접촉창 위에 텅스텐티타늄(TiW)등을 증착하여 하부장벽금속층을 형성하면, 접촉창의 상부 모서리에 텅스텐티타늄(TiW)등으로 형성된 하부장벽금속층의 낮은 단차피복성에 의해 오버행(over hang)(제1도의 (b)에서 ⓐ부위)이 발생되어서, 접촉창에서의 종횡비는 하부장벽 금속층의 형성 이전보다 크게되며, 이는 하부장벽금속층의 위에 알루미늄(Al)등의 금속을 스퍼터링(sputtering) 또는 화학기상증착(CVD;chemical vapor deposition)으로 형성하는 상부금속배선층의 오버행(제1도의 (c)에서 ⓑ부위)을 발생시켜서 상부금속배선층의 단차피복성을 악화시켰으며, 또한 접촉상의 측벽 하부 및 저면에서는 알루미늄 등의 금속이 증착되지 못하게 되어(제1도의 (c),(d)에 도시됨) 상부금속배선막이 부분적인 단선이 형성되었다.That is, in the conventional method of forming the metal wiring layer of the semiconductor device, when the bottom barrier metal layer is formed by depositing tungsten titanium (TiW) on the contact window, the lower step of the lower barrier metal layer formed of tungsten titanium (TiW) on the upper edge of the contact window An overhang (a part in (b) of FIG. 1) is caused by the coating property, so that the aspect ratio in the contact window is larger than before the formation of the lower barrier metal layer, which is made of aluminum (Al) or the like on the lower barrier metal layer. Deterioration of the step coverage of the upper metallization layer was caused by generating an overhang of the upper metallization layer (area in (c) of FIG. 1) to form the metal of the metal by sputtering or chemical vapor deposition (CVD). In addition, metals such as aluminum cannot be deposited on the bottom and bottom of the sidewalls of the contact phase (as shown in (c) and (d) of FIG. 1), thereby forming a partial disconnection of the upper metal wiring film. All.
이러한 상부금속배선층의 부분적인 단선은 반도체장치의 금속배선에 있어서, 전기전도도 감소 및 접촉창 측벽 하부모서리에서의 일렉트론 마이그레이션(electro mihgation)현상에 위한 상부금속배선층의 완전 단선 등에 따른 반도체장치의 신뢰성 악화 및 동작특성 불량 등의 문제를 유발하게 되었다.Partial disconnection of the upper metal interconnection layer deteriorates the reliability of the semiconductor device due to reduction in electrical conductivity and complete disconnection of the upper metal interconnection layer for electro mihgation at the lower edge of the contact window sidewall in the metal interconnection of the semiconductor device. And problems such as poor operation characteristics.
본 발명은 이러한 문제를 해결하기 위하여 안출된 것으로, 반도체 장치의 금속 배선막 형성에 있어서, 접촉창의 형성방법을 개선하여 상부금속배선층의 단선 방지 및 단차피복성이 향상되도록 하는 것이 그 목적이다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to improve the method of forming a contact window in forming a metal wiring film of a semiconductor device so as to prevent disconnection of the upper metal wiring layer and to improve step coverage.
본 발명에 의한 반도체 장치의 금속배선층 형성방법은 하부배선층을 가지는 기판상에 절연막을 형성시키는 단계와, 상기 절연막을 패터닝하여 상기 하부배선층을 노출시키는 접촉창을 형성하는 단계와, 상기 접촉창과 상기 절연막 상에 제1도전층을 형성시키는 단계와, 상기 제1도전층 상에 식각선택성이 큰 저점도물질을 상기 접촉창이 매립되도록 증착하여 저점도물질층을 형성하는 단계와, 상기 저점도물질층을 상기 접촉창 내에만 잔류되도록 이방성식각하되 상기 절연막 상의 제1도전층도 식각하여 상기 접촉창 상부 측에 오버행된 부위를 제거하는 단계와, 상기 저점도물질층을 제거하고 상기 접촉창을 통해 상기 제1도전층과 접촉되게 상기 절연막 상에 제2도전층을 형성시키는 단계를 포함한다.The method for forming a metal wiring layer of a semiconductor device according to the present invention includes forming an insulating film on a substrate having a lower wiring layer, patterning the insulating film to form a contact window exposing the lower wiring layer, and forming the contact window and the insulating film. Forming a low viscosity material layer by forming a first conductive layer on the first conductive layer, depositing a low viscosity material having high etch selectivity on the first conductive layer so that the contact window is buried, and forming the low viscosity material layer; Anisotropically etching so as to remain only in the contact window, but also etching the first conductive layer on the insulating layer to remove a portion overhanging the upper side of the contact window, removing the low-viscosity material layer, and removing the low viscosity material layer through the contact window. And forming a second conductive layer on the insulating layer in contact with the first conductive layer.
이하, 첨부된 도면을 참조하여 본 발명에 의한 반도체 장치의 금속배선층 형성방법을 설명한다.Hereinafter, a method for forming a metal wiring layer of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.
제2도는 본 발명의 일 실시예에 의한 반도체 장치의 금속배선층 형성방법을 설명하기 위한 도면이다.2 is a view for explaining a method for forming a metal wiring layer of a semiconductor device according to an embodiment of the present invention.
본 발명의 일 실시예에 의한 반도체장치의 금속배선층 형성방법은, 우선, 제2도의 (a)와 같이, 반도체기판(20) 상의 절연막(21) 위에 형성된 하부금속배선층(22)의 상면에 금속층간절연막(23)을 형성시킨 후에, 금속층간절연막(23)을 사진식각하여 접촉창(24)을 형성시킨다.In the method for forming a metal wiring layer of a semiconductor device according to an embodiment of the present invention, first, as shown in FIG. 2A, a metal is formed on the upper surface of the lower metal wiring layer 22 formed on the insulating film 21 on the semiconductor substrate 20. After the interlayer insulating film 23 is formed, the contact interlayer 24 is formed by photolithography of the metal interlayer insulating film 23.
이때, 하부금속배선층(22)은 절연막(21) 내의 접촉창(도시되지 않음)을 통하여 반도체기판(20)에 형성된 배선영역(도시되지 않음)과 접촉되어 있다.In this case, the lower metal wiring layer 22 is in contact with a wiring region (not shown) formed in the semiconductor substrate 20 through a contact window (not shown) in the insulating film 21.
이어서, 제2도의 (b)와 같이 접촉창(24)과 금속층간절연막(23) 표면에 텅스텐티타늄(TiW) 또는 질화티타늄(TiN)등을 증착하여, 금속층간절연막(23) 위에는 2000Å 정도의 두께를 갖고 접촉창(24)의 저면에서 500Å 정도의 두께를 갖는 하부장벽금속층(25)을 형성시킨다. 이 때, 하부장벽금속층(25)은 접촉창(24)의 상부 모서리에 오버행(ⓐ')이 형성된다.Subsequently, as shown in FIG. 2B, tungsten titanium (TiW) or titanium nitride (TiN) is deposited on the contact window 24 and the intermetallic insulating film 23, and on the intermetallic insulating film 23, about 2000 microseconds is deposited. A lower barrier metal layer 25 having a thickness and having a thickness of about 500 mm 3 at the bottom of the contact window 24 is formed. At this time, the lower barrier metal layer 25 is formed with an overhang ⓐ 'at the upper edge of the contact window 24.
그리고, 제2도의(c)와 같이, 접촉창(24)내의 하부장벽금속층25')위에 잔재하는 저점도 물질층(28')을 제거한다. 이어서, 제2도의 (f)아 같이 하부장벽금속층(25) 상에 하부장벽금속층(25)과의 식각선택성이 크고 낮은 점도를 가진 물질을 접촉상(24)이 매립되도록 증착하여 전점도물질층(28)을 형성시킨다.As shown in FIG. 2C, the low-viscosity material layer 28 'remaining on the lower barrier metal layer 25' in the contact window 24 is removed. Subsequently, as shown in (f) of FIG. 2, a material having a high etch selectivity with a low barrier metal layer 25 and a low viscosity on the lower barrier metal layer 25 is deposited so that the contact phase 24 is buried, thereby forming the entire viscosity material layer. (28) is formed.
이때, 저점도물질층(28)은 하부장벽금속층(25)과의 식각선택비가 3 내지 4인 포토레지스트를 1㎛이하의 두께로 도포하므로써 형성된다.In this case, the low viscosity material layer 28 is formed by applying a photoresist having an etching selectivity of 3 to 4 with the lower barrier metal layer 25 to a thickness of 1 μm or less.
이어서, 제2도의 (d)와 같이, 저점도물질층(28)을 접촉창(24)내에만 잔류되도록 이방성식각한다. 이 때, 금속층간절연막(23) 위의 하부장벽금속층(25)도 식각 되도하여 500Å 정도의 두께가 남도록 한다. 그러므로, 접촉창(24)의 상부모서리에서 발생되는 하부장벽금속층(25)의 오버행(제2도의 (b)와 (c)도에서 ⓐ'부위)도 식각된다. 그러므로, 금속층간절연막(23) 상의 하부장벽금속층(25')은 오버행이 제거되어 접촉창(24)의 개구폭이 증가되므로 종횡비 감소된다. 또한, 접촉창(24) 내의 하부장벽금속층(25') 위에 저점도물질층(28')이 잔재므로 하부장벽금속층(25)의 오버행(제2도의 (b)와 (c)도에서 ⓐ'부위) 식각시 접촉창(24) 저면의 하부장벽금속층(25')이 손상되는 것을 방지한다.Subsequently, as shown in FIG. 2D, the low viscosity material layer 28 is anisotropically etched so as to remain only in the contact window 24. At this time, the lower barrier metal layer 25 on the interlayer dielectric film 23 is also etched so that a thickness of about 500 kPa remains. Therefore, the overhang of the lower barrier metal layer 25 generated at the upper edge of the contact window 24 (a part in FIG. 2 (b) and (c)) is also etched. Therefore, the lower barrier metal layer 25 'on the intermetallic insulating film 23 is reduced in aspect ratio since the overhang is removed so that the opening width of the contact window 24 is increased. In addition, since the low-viscosity material layer 28 'remains on the lower barrier metal layer 25' in the contact window 24, the overhang of the lower barrier metal layer 25 (a in FIG. 2 (b) and (c) in FIG. Area) prevents damage to the lower barrier metal layer 25 'on the bottom of the contact window 24 during etching.
그리고 제2도의 (e)와 같이, 하부장벽금속층(25') 위에 상부금속배선층(26)을 형성시킨 후에, 상부금속배선층(26) 위에 상부장벽금속층(27)을 형성시킨다. 이때, 접촉창(24)의 종횡비가 감소되므로 상부금속배선층(26)의 단차피복성이 개선된다.As shown in FIG. 2E, after forming the upper metal wiring layer 26 on the lower barrier metal layer 25 ′, the upper barrier metal layer 27 is formed on the upper metal wiring layer 26. At this time, since the aspect ratio of the contact window 24 is reduced, the step coverage of the upper metal wiring layer 26 is improved.
제3도은 본 발명의 다른 실시예에 의한 반도체장치의 금속배선층 형성방법을 도시하는 도면이다.3 is a view showing a metal wiring layer forming method of a semiconductor device according to another embodiment of the present invention.
우선, 제3도의 (a)와 같이, 반도체기판(30)상의 절연막(31) 위에 형성된 하부금속배선층(32)의 상면에 금속층간절연막(33)을 형성시킨 후에, 금속층간절연막(33)을 사진식각하여 접촉창(34)을 형성한다. 그리고, 접촉장(34)과 금속층간절연막(33)의 표면에 텅스텐티타늄(TiW) 또는 질화티타늄(TiN)를 증착하여, 금속층간절연막(33) 위에는 2000Å 정도의 두께를 갖고 접촉창(34)의 저면에서 500Å 정도의 두께를 갖는 하부장벽금속층(35)을 형성한다. 이 때, 하부장벽금속층(35)은 접촉창(34)의 상부 모서리에 오버행(ⓐ)이 형성된다.First, as shown in FIG. 3A, after forming the interlayer insulating film 33 on the upper surface of the lower metal wiring layer 32 formed on the insulating film 31 on the semiconductor substrate 30, the interlayer insulating film 33 is formed. Photolithography forms a contact window 34. Tungsten titanium (TiW) or titanium nitride (TiN) is deposited on the contact field 34 and the surface of the metal interlayer insulating film 33, and the contact window 34 has a thickness of about 2000 Å on the metal interlayer insulating film 33. On the bottom surface of the lower barrier metal layer 35 having a thickness of about 500Å is formed. At this time, the lower barrier metal layer 35 has an overhang ⓐ at the upper edge of the contact window 34.
그리고, 하부장벽금속층(35) 상에 하부장벽금속층(35)과의 식각선택성이 크고 낮은 점도를 가진 물질을 접촉창(34)이 매립되도록 증착하여 전점도물질층(38)을 형성한다. 상기에서 하부금속배선층(32)은 절연막(31)에 형성된 접촉창(도시되지 않은)을 통하여 반도체기판(31)에 형성된 배선영역(도시되지 않음)과 접촉되며, 저점도물질층(38)은 하부장벽금속층(35)과의 식각선택비가 3 내지 4인 포토레지스트를 1㎛이하의 두께로 도포하므로써 형성된다.In addition, a material having a high etch selectivity and a low viscosity with the lower barrier metal layer 35 is deposited on the lower barrier metal layer 35 such that the contact window 34 is buried to form the full viscosity material layer 38. The lower metal wiring layer 32 is in contact with the wiring region (not shown) formed on the semiconductor substrate 31 through a contact window (not shown) formed in the insulating film 31, the low-viscosity material layer 38 It is formed by applying a photoresist having an etching selectivity of 3 to 4 with the lower barrier metal layer 35 to a thickness of 1 m or less.
이어서, 제3도의 (b)와 같이, 저점도 물질층(38)을 접촉창(34) 내에 잔류하도록 이방성식각한다. 이때, 하부장벽금속층(35)도 금속층간절연막(33)이 노출되도록 식각하는 데, 이에 의해, 접촉창(34)의 상부 모서리에 형성된 하부장벽금속층(35')의 오버행(제3도의 (a)도에서 ⓐ부위)이 제거된다.Subsequently, as shown in FIG. 3B, the low viscosity material layer 38 is anisotropically etched to remain in the contact window 34. At this time, the lower barrier metal layer 35 is also etched to expose the interlayer dielectric film 33, thereby overhanging the lower barrier metal layer 35 ′ formed at the upper edge of the contact window 34 (FIG. Ⓐ part is removed from).
그러므로, 접촉창(34)의 개구폭이 증가되므로 종횡비 감소된다. 또한, 접촉창(34) 내의 하부장벽금속층(35') 위에 저점도물질층(38')이 잔재하므로 하부장벽금속층(35)의 오버행(제3도의 (a)도에서 ⓐ부위) 식각시 접촉창(34) 저면의 하부장벽금속층(35')이 손상되는 것을 방지한다.Therefore, the aspect ratio is reduced because the opening width of the contact window 34 is increased. In addition, since the low-viscosity material layer 38 'remains on the lower barrier metal layer 35' in the contact window 34, the lower barrier metal layer 35 contacts at the time of overhanging (a part in FIG. 3 (a)). The lower barrier metal layer 35 'at the bottom of the window 34 is prevented from being damaged.
그리고 제3도의 (c)와 같이, 접촉창(34) 내의 하부장벽금속층(35') 위에 잔재하는 저점도물질층(38')을 제거한다.As shown in FIG. 3C, the low-viscosity material layer 38 ′ remaining on the lower barrier metal layer 35 ′ in the contact window 34 is removed.
이어서, 제3도의 (d)와 같이, 하부장벽금속층(35') 위에 상부금속배선층(36)을 형성시킨 후에, 상부금속배선층(36) 위에 상부장벽금속층(37)을 형성시킨다. 이 때, 접촉창(34)의 종횡비가 감소되므로 상부금속배선층(36)의 단차피복성이 개선된다.Subsequently, as shown in FIG. 3D, after the upper metal wiring layer 36 is formed on the lower barrier metal layer 35 ′, the upper barrier metal layer 37 is formed on the upper metal wiring layer 36. At this time, since the aspect ratio of the contact window 34 is reduced, the step coverage of the upper metal wiring layer 36 is improved.
본 발명에 의한 반도체장치의 금속배선층 형성방법에서는 하부장벽금속층의 상면에 형성되고 하부장벽금속층과의 식각선택성이 높으면서 낮은 점도를 가진 저점도물질층을 이방성식각하여 제거하면서 금속층간절연막 위의 하부장벽금속층도 식각하여 하부장벽금속층의 두께가 접촉창 저면의 하부장벽금속층의 두께 정도로 되도록 잔재시켜서 상부금속배선층의 장벽기능을 유지하게 하거나 완전히 제거하여 금속층간절연막을 노출시키면서 접촉창 상부 모서리의 오버행도 식각하여 제거함으로써 접촉창의 개구폭 증가에 의한 종횡비를 감소시켜 이후에 형성되는 상부금속층의 단차피복성을 개선하였다.In the method for forming a metallization layer of a semiconductor device according to the present invention, the lower barrier layer is formed on the upper surface of the lower barrier metal layer and is anisotropically removed by removing the low viscosity material layer having a low viscosity while having high etching selectivity with the lower barrier metal layer. The metal layer is also etched so that the thickness of the lower barrier metal layer remains the thickness of the lower barrier metal layer on the bottom of the contact window to maintain or completely remove the barrier function of the upper metal interconnection layer to expose the interlayer dielectric layer and expose the overhang of the upper edge of the contact window. In this case, the aspect ratio caused by the increase in the opening width of the contact window was reduced to improve the step coverage of the upper metal layer formed later.
또한 저점도물질층에 의해 접촉창 상부의 오버행을 제거할 때 접촉창 저면의 하부장벽금속막이 손상되지 않도록 보호되므로 반도체소자의 배선 신뢰성에 영향을 미치지 않게 된다.In addition, when the overhang on the upper portion of the contact window is removed by the low-viscosity material layer, the lower barrier metal film on the bottom surface of the contact window is protected from damage, thereby not affecting the wiring reliability of the semiconductor device.
그리고 접촉창의 상부 모서리에 발생되는 오버행 제거에 의해 접촉창의 개구부 폭이 커지게 되어서, 상부금속층을 형성시키기 위해서 알루미늄(Al)등의 금속을 스퍼터링 또는 화학기상증착 시킬 때에 금속이온이 유입이 우수하게 되어, 접촉창의 측벽 하부 및 저면에서 단선되지 않은 연속적인 상부금속배선층이 형성된다.In addition, the width of the opening of the contact window is increased by removing the overhang generated at the upper edge of the contact window, so that metal ions are excellent inflow when sputtering or chemical vapor deposition of metal such as aluminum (Al) to form the upper metal layer. A continuous upper metal interconnection layer is formed at the bottom and bottom of the sidewall of the contact window that is not disconnected.
즉, 본 발명에 의한 반도체 장치의 금속배선층 형성방법에서는 오버행을 식각하여 접촉창의 개구폭을 크게 하여 종횡비가 감소되도록 하였으며, 이로 인하여 접촉창에서 단선되지 않고 연속적인 상부금속배선층의 전기전도도가 향상되고, 또한 일렉트론 마이그레이션등의 현상을 방지할 수 있으므로, 반도체 디바이스의 동작 신뢰성이 향상된다.That is, in the method for forming a metal wiring layer of the semiconductor device according to the present invention, the aspect ratio is reduced by increasing the opening width of the contact window by etching the overhang, thereby improving the electrical conductivity of the continuous upper metal wiring layer without disconnection from the contact window. In addition, since the phenomenon such as electron migration can be prevented, the operation reliability of the semiconductor device is improved.
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| KR100587594B1 (en) * | 2002-07-12 | 2006-06-08 | 매그나칩 반도체 유한회사 | Method for forming metal wiring semiconductor device |
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