KR0183655B1 - A/d converting data processing circuit - Google Patents

Abstract

According to the present invention, the process of converting an analog signal into a digital signal and storing the predetermined data stored therein is performed independently by using a memory device having a single control pin for reading and storing. A conversion data processing circuit.

In order to improve the data processing speed, the A / D conversion control unit controls the analog signal input to the multiplexer periodically and sequentially in a plurality of channels, and when the selected analog signal is converted into a digital signal in the A / D conversion unit. Outputs a storage address signal stored in the memory unit, and stores and stores the digital signal in order to superimpose and apply the read signal of the central signal processor for storing the digital signal and the stored data. The storage signal of the reading control section and the reading signal of the central signal processing section are inputted to the switching means to control the switching means and apply them to a single control pin of the memory section. In particular, when the A / D converted digital signal is stored in the memory section, the central signal By delaying the read signal of the processing section, data storage and reading are performed independently.

Description

A / D conversion data processing circuit

The present invention relates to an A / D conversion data processing circuit that automatically controls a memory device having a single control pin for storing and reading, and independently processes the storing and reading processing of digital data in which an analog signal is converted into a digital signal. will be.

Using a number of channels (e.g. 16 channels), let's look at the characteristics of the data store when converting an analog signal into a digital signal and then storing and reading it.

First, in the case of a memory device employing a latch circuit, the advantage of selecting each channel is possible. However, after the CPU selects a channel during A / D conversion, the channel selection signal is an A / D converter. Since the A / D conversion is performed after reaching A, the time required for the A / D conversion process becomes long, and the CPU has to wait during the A / D conversion period, which results in low data processing efficiency.

Secondly, in the case of a memory device employing a flip-flop circuit, the path for storing the flip-flop by A / D conversion and the path for reading the stored data from the CPU can be designed to be independent. In order to always read the data of a plurality of channels including the channel to be read first, and then obtain the corresponding data, there is a disadvantage that the processing efficiency of the CPU processing the data is inferior.

Third, when dual port ram is used, the A / D conversion path and the path read by the CPU are completely independent, which improves the data processing efficiency of the CPU. It is difficult to apply economically to the system.

Typically, low-capacity dedicated control systems use inexpensive memory devices with a single storage and readout control pin. When storing and reading data by such a single control pin, the storage path and the path for reading the stored data are not independent, thereby reducing the data processing efficiency by slowing down the processing speed of processing data in the CPU.

The present invention was devised to solve the above problems, and the process of converting and storing analog signals into digital signals using a memory device having a single control pin for reading and storing and reading out predetermined data stored therein are independent. The purpose of the present invention is to provide an A / D conversion data processing circuit having improved data processing speed.

1 is a block diagram of an A / D conversion data processing circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of the storage and reading control unit of FIG. 1.

3 to 5 are timing diagrams of some output stages for explaining data storing and reading processes in the A / D conversion data processing circuit of FIG. 1.

* Explanation of symbols for main parts of the drawings

1: Multiplexer 2: Sampling / holding part (S / H)

3: A / D Converter 4: Memory

5: A / D conversion control unit 6: Central signal processing unit (CPU)

7: storage and reading control unit 8: switching means

An A / D conversion data processing circuit of the present invention for achieving the above object comprises: a multiplexer which sequentially receives analog signals from a plurality of channels to which analog signals are input; An A / D conversion unit converting the analog signal obtained from the multiplexer into a digital signal and outputting a conversion completion signal; A memory unit for storing the digital signal, each having a single control pin and a designated address control pin for reading and storing; Switching means for selecting predetermined input terminals from a plurality of input terminals and outputting the predetermined input terminals to the single control pin for reading / storing the memory unit and the designated address control pin, respectively; The channel selection of the multiplexer and the digital conversion start of the A / D converter are controlled, and a storage address signal for designating a place where the digital signal is stored in the memory unit is input to the input terminal of the switching means to perform periodic and sequential operations. An A / D conversion control unit for controlling an A / D conversion; A central signal processor for inputting a read address signal and a read signal to an input terminal of the switching means to read the digital data stored in the memory unit; The switching means controls the switching means to output the storage address signal from the switching means and the storage signal inputted to the input terminal of the switching means by the switching means so that the digital signal is stored in the memory unit from the conversion completion signal of the A / D converter. And a storage and reading control unit which applies a recognition signal informing the central signal processing unit whether the read signal has been processed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an A / D conversion data processing circuit according to an embodiment of the present invention.

The blocks shown in FIG. 1 include a multiplexer 1, a sampling / holding unit (S / H, 2), an A / D conversion unit 3, a memory unit 4, a control unit 5, and a central signal processing unit. (CPU, 6), the storage and reading control section 7, and the switching means 8 are displayed.

The analog signal output through the channels sequentially selected by the multiplexer 1 is input to the A / D converter 3 via the sampling / hold unit 2. The A / D conversion section 3 converts the analog signal input from the sampling / holding section 2 into a digital signal. This A / D conversion process is controlled by the A / D conversion control unit 5. That is, the A / D conversion control section 5 applies the channel selection signal to the multiplexer 1 to determine the sequential channel selection of the multiplexer 1, and to the A / D conversion section 3 through the selected channel. The A / D conversion start signal is applied to the A / D converter 3 so that the analog signal is A / D converted by the A / D converter 3 according to the input timing. Each control signal output from the A / D conversion control unit 5 is periodically generated so that the analog signal input to the multiplexer 1 is converted into a digital signal in sequence and infinitely repeated, so that continuous analog-to-digital conversion operation is performed. It is set to be made.

The A / D conversion unit 3 performs A / D conversion according to the A / D conversion start signal of the A / D conversion control unit 5, and when the conversion is completed, A / D conversion completion signal S indicating completion of conversion (S). ) Is applied to the storage and reading control unit 7. The storage and read control unit 7 is a single control pin for reading / storing the memory unit 4 so that the data A / D converted from the A / D conversion completion signal S of the A / D conversion unit 3 is stored. Relay control of W / R) and designated address control pin (A). That is, the storage and read control unit 7 applies a switch switching signal to the switching means 8 so that the A / D converted data is stored at a designated address of the memory unit 3, so that the switching means 8 receives the A / D. The storage address signal of the conversion control section 5 is outputted to the designated address control pin A of the memory section 8, and the storage signal of the storage and readout control section 7 is read / stored control pin (W / To R).

Here, the switching means 8 is composed of a first switching means 8a and a second switching means 8b, and the first switching means 8a is a storage address signal and a center signal of the A / D converter 3. One of the read address signals of the processing section 6 is selected and applied to the designated address control pin A of the memory section 4, and the second switching means 8b stores the read address signal of the central signal processing section 6, One of the stored signals of the read control section 7 is selected and applied to the read / store control pins W / R of the memory section 4.

In this selection, when the switch switching signal of the storage and reading control section 7 is not applied, the first switching means 8b sends the read address signal of the central signal processing section 6 to the second switching means 8a. The read signals of the signal processor 6 are selected to be output, respectively, and when the switch switching signal is applied, the first switching means 8a transmits the storage address signal of the A / D conversion controller 5 to the second switching means 8b. Is selected to output the storage signals of the storage and readout control section 7, respectively.

Therefore, the process of converting analog signals into digital signals continuously and storing them, and the data processing process of the central signal processing section 6 for reading the stored predetermined digital data are performed independently. At this time, the central signal processor 6 continuously designates and processes data of a specific address to be read according to its own processing program.

At this time, since the reading process of the central signal processing unit 6 and the storing process of the A / D converted data are performed independently, when the read signal of the central signal processing unit 6 and the storage signal of the A / D converted data are overlapped. May occur. This is because the storage and reading of data is done independently using a single control pin. In order to explain a specific method for preventing data loss or distortion when such an overlapping signal occurs, first, a data processing process of the central signal processing unit 6 in a general small capacity dedicated control system will be described.

The central signal processing unit 6 performs data processing according to a predetermined algorithm. At this time, it is necessary to confirm whether a command issued in each step is processed. In this way, the signal for recognizing the processing of the command is the recognition signal. A simple way of recognizing whether or not command processing is completed is to apply the periodic signal set according to the processing speed of the system to the central signal processor 6 as a recognition signal. That is, it is designed to issue the next command after a predetermined time elapses after the command is issued, and the command processing recognition method receives and recognizes a periodic pulse from a self-equipped pulse generator as a recognition signal.

In the present invention, when the read signal of the central signal processing section 6 and the storage signal for storing the A / D conversion completed data overlap, the storage and reading control section 7 controls the recognition signal confirming the command processing, Data loss is prevented in the data processing of the signal processor 6 and data processing is performed independently.

To illustrate this process, reference is made to FIG. 2, which shows a block diagram of the configuration of the storage and reading control unit 7.

The storage and readout control section 7 is composed of a first short pulse generator 7b, a second short pulse generator 7c and a recognition signal generating means 7a.

Here, the short pulse generators 7b, 7c, and 7d recognize a rising or falling portion of the input signal to generate a pulse having a constant width once. Therefore, the pulse width is set to a predetermined width so that the desired signal processing is achieved for a set period in relation to the processing speed of the system. When the A / D conversion is completed, the A / D conversion completion signal S is applied to the short pulse generators 7b, 7c, and 7d by the A / D conversion unit, and from each of the A / D conversion completion signals S, The short pulse generators 7b, 7c, and 7d generate short pulses for a predetermined period of time.

The first short pulse generator 7b generates a short pulse from the A / D conversion completion signal S and applies it to the switching means 8a and 8b as a switch switching signal. Accordingly, from this switch switching signal, the first switching means 8a transmits its output terminal c to the storage address input terminal a of the A / D conversion control section 5 from the read address signal input terminal b of the central signal processing section 6. Switch, and the second switching means 8a stores its output terminal F from the read signal input terminal D of the central signal processing section 6 and the storage signal input terminal E of the reading control section 7. Change the switch to) and connect it.

The second short pulse generator 7c generates a short pulse from the A / D conversion completion signal S and applies the storage signal to the input terminal E of the second switching means 8a. As a result, the short pulse signal of the second short pulse generator 7c switches the read / store control pins W / R of the memory unit 4 to the storage mode, and simultaneously from the A / D conversion controller 5 The storage address signal of the control unit (A) of the designated address control pin (A) of the memory unit 4 stores the A / D converted digital data at the designated address.

The recognition signal generating means 7a is roughly divided into a third short pulse generator 7d, a pulse generator 7k, and an AND gate 7f.

The pulse generator 7k generally used for data processing recognition of the central signal processing section 6 generates the set pulse at a constant cycle. The period of the pulse and the width of the pulse are set in relation to the data processing speed of the system itself.

When the A / D conversion completion signal S is applied, the third short pulse generator 7d generates a short pulse of low level (logically 0). Therefore, when there is no A / D conversion completion signal S of the A / D conversion section 3, the high level (logically equivalent to 1) output signal of the third stage pulse generator 7d and the output of the pulse generator 7k are provided. Since the pulse is input to the AND gate 7f, the resultant output signal of the AND gate 7f outputs the pulse signal of the pulse generator 7k. Therefore, when there is no A / D conversion completion signal S, the recognition signal is output in accordance with the period of the pulse generator 7k, and the data processing of the central signal processing section 6 is periodically processed.

The signal processing procedure when the read signal sent out to read the data required by the central signal processing unit 6 and the storage signal of the storage and readout control unit according to the A / D conversion completion signal S are overlapped.

In response to the A / D conversion completion signal S, the third short pulse generator 7d outputs a short pulse of the low signal for the set pulse width time, and accordingly outputs a low level signal during this pulse period, As a result, the recognition signal recognized by the central signal processor 6 is blocked. During this period, that is, during the period during which the low level output signal is generated by the third short pulse generator 7d, the A / D-converted digital data completes storage, and after completion of storage, the input terminal of the switching means 8 is completed. The switch is switched to select the read signal and the read address signal which are the command signals of the central signal processor 6, so that the read command of the central signal processor 6 is processed. In this process, since the central signal processing section 6 does not receive the recognition signal, the loss is not generated in the data processing by continuously maintaining the read signal and the read address signal of the central signal processing section 6.

Therefore, the A / D conversion data processing circuit of the present invention described above allows data processing related to storage and reading of data to be independently performed using a memory device having a single control pin for reading / storing, and a data processing process. Even when the storage and the reading overlap, the recognition signal of the central signal processor 6 is delayed to prevent distortion and loss of data.

The data processing process described so far will be described with reference to the signal waveform diagram over time shown in FIGS. 3 to 5.

Each figure shows a channel sequentially selected over time and the waveform of each output stage corresponding thereto.

3 shows that an analog signal is converted into a digital signal and stored.

In the illustrated example, a process of sequentially storing analog signals applied to the multiplexer through 16 channels and storing 16 digital signals corresponding to each channel in the memory unit is shown. The combination of A0 to A3 indicates a designated address of each channel. To indicate.

Next, let's look at the behavior.

When the high level A / D conversion start signal is applied to the A / D conversion section 3, the A / D conversion is started.

The A / D conversion completion signal S is an output signal of the A / D conversion section 3 to indicate that the high signal output is A / D conversion complete. Such A / D conversion is sequentially and continuously processed continuously, and at this time, the switch switching signal generated by the first short pulse generator 7b has a predetermined width from the input high level A / D conversion completion signal S. The pulse signal (low level) is applied to the switching means 8. During the short pulse period from the first short pulse generator 7b, the second switching means 8a selects a storage signal of the storage and reading control section 7, and from the storage signal of this storage and reading control section 7b. The data A / D converted in the A / D conversion unit 3 is stored in the memory unit 4. The read / store single control pin (W / R) recognizes the low signal as the storage signal and the high signal as the read signal.

At this time, the first switching means 8a outputs the storage address signal input terminal of the A / D conversion control section 5 so that the A / D conversion-completed data is stored at the designated address.

4 and 5 show the comparison between the case where the read signal of the central signal processor 6 and the storage signal for storing the A / D converted digital signal do not overlap with the case where they overlap.

In FIG. 4, since the read signal of the central signal processor 6 does not overlap with the stored signal of the storage and read controller 7, the storage of A / D converted data and the read process of the central signal processor 6 are independently processed. do. However, referring to FIG. 5, when the read signal of the central signal processor 6 and the stored signal of the storage and read controller 7 overlap each other, the data read completion according to the read signal of the central signal processor 6 is completed. The short signal generated by the third-stage pulse generator 7d by the A / D conversion completion signal S signal cuts off the output signal of the AND gate 7d for a predetermined period of time. The read signal of (6) is extended. Therefore, when the digital data A / D converted during this period is stored and the third short pulse generator 7d is switched to the high level, the data readout process is performed by the data readout signal of the central signal processor 6. Therefore, the processing of the data is done independently without distortion.

As described above, by providing the A / D conversion data processing circuit according to the present invention, the storage of A / D converted digital data and the reading of the stored data are independently performed by the control of a single read / store control pin. The data processing speed is improved.

Claims (5)

A multiplexer which sequentially receives analog signals from a plurality of channels to which analog signals are input; An A / D conversion unit converting the analog signal obtained from the multiplexer into a digital signal and outputting a conversion completion signal; A memory unit for storing the digital signal, each having a single control pin and a designated address control pin for reading and storing; Switching means for selecting a predetermined input terminal from a plurality of input terminals by a control signal and outputting the predetermined input terminal to the single control pin for reading / storing the memory unit and the designated address control pin, respectively; The channel selection of the multiplexer and the digital conversion start of the A / D converter are controlled, and a storage address signal for designating a place where the digital signal is stored in the memory unit is input to the input terminal of the switching means to perform periodic and sequential operations. An A / D conversion control unit for controlling an A / D conversion; A central signal processor for inputting a read address signal and a read signal to an input terminal of the switching means for reading the digital signal stored in the memory unit; The switching means controls the switching means to output the storage address signal from the switching means and the storage signal inputted to the input terminal of the switching means by the switching means so that the digital signal is stored in the memory unit from the conversion completion signal of the A / D converter. And a storage and readout control unit which applies a recognition signal to the central signal processing unit to indicate whether the readout signal has been processed. 2. The apparatus of claim 1, wherein the switch means comprises: first switching means for selecting and outputting a storage address signal of the A / D conversion controller and a read address signal of the central signal processor in accordance with a control signal of the storage and readout controller; And second switching means for selecting and outputting the stored signal of the storage and readout control unit and the read signal of the central signal processor according to the control signal of the storage and readout control unit. . 2. The apparatus of claim 1, wherein the storing and reading control unit comprises: a first short pulse generator for applying a control signal to the switching means from the conversion completion signal; A second short pulse generator for applying a storage signal from the conversion completion signal to an input terminal of the switching means; And recognition signal generating means for generating the recognition signal and applying the recognition signal to the central processing control unit. 4. The apparatus of claim 1 or 3, wherein the recognition signal generating means comprises: a pulse generator for generating a periodic pulse at a set period; A logic unit which logically compares an output signal of the pulse generator applied to one input terminal with a signal applied to another input terminal and outputs the result to the central signal processor; And a third short pulse generator for generating a short pulse for controlling the signal output from the pulse generator to block output from the logic unit from the conversion completion signal and inputting the short pulse to the logic unit. / D conversion data processing circuit. 5. The A / D conversion data processing circuit according to claim 4, wherein the logic unit is an AND gate, and the short pulse signal of the third short pulse generator is a logic signal that blocks the output of the AND gate.