KR0178227B1 - Pulse Shaping Filter Circuit with Parallel Structure - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a pulse shaping filter circuit for preventing interference between adjacent symbols while limiting the bandwidth of an encoded signal. The present invention relates to N (integer) filter taps for an input digital pulse having a digital symbol rate f. A pulse shaping filter circuit for shaping and filtering by coefficient; N / 2 + 1 filter taps, the filter tap coefficient at the left end centering on the reference tap is 0, and the remaining filter tap coefficients have an even-order filter coefficient among the N filter tap coefficients and the digital symbol rate The first filter 301 for shaping and filtering the input digital pulse f is formed in parallel with the first filter 301 and is composed of N / 2 filter taps, and the filter tap coefficient is an odd number of the N filter tap coefficients. The second filter 302 having a differential filter coefficient and shaping and filtering the input digital pulse having the digital symbol rate f, and the digital signal output in parallel from the first filter 301 and the second filter 302. A parallel / serial conversion section 303 for converting in series is provided.

Description

Pulse Shaping Filter Circuit with Parallel Structure

1 is a schematic block diagram showing a general digital video signal transmission system.

2 is a detailed block diagram of the pulse shaping filter of FIG.

3 is an overall configuration diagram showing an embodiment of the present invention.

4 is a detailed block diagram of a FIR filter according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

301,302: FIR filter 303: parallel / serial conversion part

304: D / A converter 305: low pass filter

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a pulse shaping filter circuit for preventing interference between adjacent symbols, in particular while limiting the bandwidth of an encoded signal.

FIG. 1 is a schematic block diagram illustrating a general digital video signal transmission system.

First, in order to transmit a digital video signal having a wide bandwidth in the same bandwidth as that of an NTSC signal, band compression by the source coding unit 101 is required. In addition, the channel coding unit 102 performs error correction coding on the digital video signal in order to correct or detect a bit error occurring while the band-compressed digital video signal is transmitted through the channel. At this time, since the digital signal sequence to be transmitted is in the form of a pulse sequence in the time domain, the spectrum in the frequency domain has an infinite bandwidth. Thus, the transmission / reception filter for limiting the bandwidth has a band limitation in frequency but causes inter-symbol interference in time. Accordingly, the pulse shaping filter 103 limits the bandwidth of the coded signal and prevents interference between adjacent symbols.

The signal whose bandwidth is limited by the pulse shaping filter 103 is inputted to the modulator 104 to modulate the carrier wave, and the signal modulated by the modulator 104 is removed by the band pass filter 105. Is sent to the receiving end.

FIG. 2 is a detailed circuit diagram of the pulse shaping filter 103 for limiting the bandwidth of an encoded signal and preventing interference between adjacent symbols, and is implemented using a digital finite impulse response (FIR) filter.

In theory, the minimum system bandwidth for avoiding and detecting intersymbol interference with a symbol rate of Rs symbol / s is Rs / 2. Is the form of an ideal pulse shaping filter The type of filter cannot be realized physically, and due to the long delay time, it is difficult to implement it practically because an equalizer of an accurate symbol clock is required for sampling. Therefore, in order to solve this difficulty while minimizing the amount of intersymbol interference, a raised cosine filter is generally used. Equations H (f) and h (f) in the frequency and time domains for the pulse shaping filter are the same as (Formula 1) and (Formula 2), respectively.

Where W is the bandwidth, Represents the minimum Nyquist bandwidth, and the roll off factor is It is defined as and has a value between 0 and 1.

Therefore, the conventional pulse shaping filter 103 inserts 0 into an input digital pulse having a digital symbol rate of f and converts it into a digital pulse of 2f so as to satisfy the Nyquist sampling rate, and the digital pulse train of 2f. Converts the digital signal filtered by the FIR filter 202 and the FIR filter 202, consisting of N (N: integer) taps, to limit the bandwidth of the signal while limiting the bandwidth of the signal. The digital / analog (D / A) converter 203 and the low pass filter 204 for removing noise generated while the digital signal is converted into analog are performed as follows.

First, when a digital pulse having a digital symbol rate of f is input, the zero insertion unit 201 inserts 0 between the input digital pulse and the pulse in order to satisfy the Nyquist sampling rate and converts it into a digital signal of 2f, and then converts it to a FIR. Output to filter 202. The FIR filter 202 filters the digital pulse train of 2f to prevent interference between adjacent symbols while limiting the bandwidth of the digital signal as described above. The digital signal filtered by the FIR filter 202 is converted into analog by the D / A converter 203, and the low pass filter 204 removes noise generated while converting the digital signal into analog and then modulates it. Output to 104.

However, the above-described pulse shaping circuit of the prior art has a problem in that the configuration is complicated, such as 0 must be inserted to satisfy the Nyquist sampling rate, and it can be used only at low speeds.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a pulse shaping filter circuit that operates at a high speed even though a simple configuration using a parallel structure.

The present invention relates to a pulse shaping filter circuit for shaping and filtering an input digital pulse having a digital symbol rate f by N (integer) filter tap coefficients to achieve the above object; N / 2 + 1 filter taps, the filter tap coefficient at the left end of the reference tap being 0, and the remaining filter tap coefficients have filter coefficients of even order terms among the N filter tap coefficients. The first filter for shaping and filtering the input digital pulse, which is f, consists of N / 2 filter taps in parallel with the first filter, and the filter tap coefficients have filter coefficients of odd order terms among the N filter tap coefficients. And a second filter for shaping and filtering the input digital pulse having the digital symbol rate f, and a parallel / serial converter for converting the digital signals output in parallel from the first filter and the second filter in series. It features.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3 is a detailed block diagram showing an embodiment of the present invention. The FIR filter 301 and the FIR filter (N / A + 1 taps) which perform shaping filtering of odd-side pulses of an input digital pulse having a digital symbol rate f are shown in FIG. 301, which is composed of N / 2 taps in parallel, and in FIR filter 302, FIR filter 301, and FIR filter 302, which perform shaping filtering of even-side pulses of an input digital pulse having a digital symbol rate f. Parallel / serial conversion unit 303 for converting the FIR filtered digital signal outputted in series to D / A conversion unit 304 for converting the digital signal converted in series by the parallel / serial conversion unit 303 into analog ), A low pass filter 305 that removes noise generated while the digital signal is converted to analog is performed as follows.

First, referring to FIG. 1, when a digital signal of 2f having 0 inserted therein is input, the conventional FIR filter 202 multiplies each of N filter tap coefficients and adds them again to perform pulse shaping.

Considering this as a concept of parallel structure:

For example, N = 8 and each filter tap coefficient is C0, C1, C2 ,,,,, C7, and the input digital pulse of 2f is x ₀ , 0, x ₁ , 0, x ₂ , 0, x ₃ , 0 If, x ₄ , 0, x ₅ , 0 ,,, the output of the conventional FIR filter 202 will be sequentially as shown in equations 3, 4, 5, and 6.

That is, in the third equation, when x ₀ , 0, x ₁ , 0, x ₂ , 0, x ₃ is input to the conventional FIR filter 202 having n = 8, 0 is input again. Output, the fourth expression is the output of the FIR filter 202 when x ₄ is input again after x ₀ , 0, x ₁ , 0, x ₂ , 0, x ₃ , 0 is input, and the fifth expression is x ₄ is the output of the after FIR filter 202. If again be 0, the input type, the sixth equation x after ₄ and 0 is input when again be x ₅ input illustrates the output of the FIR filter 202 in order.

In the operation as described above, conventionally, 0 is inserted into an input digital signal having a digital symbol rate of f, converted into a digital signal of 2f, and pulse shaping filtering is performed at a speed of 2f.

Accordingly, the present invention, unlike the prior art, does not insert 0, but receives the input digital pulse having the digital symbol rate f as it is, but consists of N / 2 +1 filter taps, and the odd side of the input digital pulse having the digital symbol rate f is A conventional FIR filter is formed by connecting a FIR filter 202 for shaping a pulse and a FIR filter 302 for shaping and filtering the even-side pulse of an input digital pulse having a digital symbol rate f consisting of N / 2 filter taps in parallel. It is possible to double the processing speed while maintaining the same filtering effect as (202).

For example, as shown in FIG. 4, the filter tap consists of N / 2 +1 filter taps (in the case of N: 8), and the filter coefficient of the filter tap existing at the left end of the reference tap is 0, and the rest The filter coefficients consist of the FIR filter 301 of C ₁ , C ₃ , C ₅ , and C ₇ from the left side and N / 2 (if N: 8) filter taps. Connecting the filters 302 having the filter coefficients C ₀ , C ₂ , C ₄ , and C ₆ in parallel produces the same filtering effect as the conventional FIR filter 202.

That is, when the input digital pulses x ₀ , x ₁ , x ₂ , x ₃ , having a digital symbol rate of F are sequentially input to the FIR filters 301, 302, and x ₄ is input again, the FIR filter 301 may generate a third equation. As shown in FIG. 4, the FIR filter 302 outputs the filtered signal at the same speed as the digital symbol rate f.

In addition, if the input digital pulses x ₀ , x ₁ , x ₂ , x ₃ , x ₄ are sequentially input to the FIR filters 301, 302 and x ₅ is input again, the FIR filter 301 may have a digital symbol rate as shown in Equation 5 below. The filtered signal is output at the same rate f, and the FIR filter 302 outputs the filtered signal at the same rate as the digital symbol rate f as in the sixth equation.

Accordingly, the parallel / serial converter 303 converts the digital data output in parallel at the speed of f from the FIR filter 301 and the FIR filter 302 in series to convert the 2f serial digital signal into a D / A converter ( To 304). The digital signal converted in series by the parallel / serial converter 303 is converted into analog by the D / A converter 304, and noise generated while the digital signal is converted into analog is transferred to the low pass filter 305. Is removed by

SR1 and SR2, which are not described in FIG. 4, generally indicate shift registers provided in the digital filter for shifting the input digital data.

As described above, the present invention has the effect of simplifying the configuration of the pulse shaping filter circuit by configuring the FIR filters in a parallel structure and filtering at high speed.

Claims (2)

A pulse shaping filter circuit for shaping and filtering an input digital pulse having a digital symbol rate of f by N (integer) filter tap coefficients, wherein the filter comprises N / 2 + 1 filter taps, A first filter 301 for forming and filtering an input digital pulse having a filter coefficient of an even order term among the N filter tap coefficients and having a filter coefficient of 0, and the digital symbol rate is f; An input digital pulse configured in parallel with one filter 301 and composed of N / 2 filter taps, each filter tap coefficient having a filter coefficient of an odd order term among the N filter tap coefficients, and having a digital symbol rate f. And a parallel / serial conversion unit 303 for serially converting the digital signals output in parallel from the first filter 301 and the second filter 302. Pulse shaping filter circuit. 2. The pulse shaping filter circuit of claim 1, wherein the first filter (301) and the second filter (302) are constituted by finite impulse response (FIR) filters.