KR0177397B1 - Slicing method of semiconductor wafer - Google Patents
Slicing method of semiconductor wafer Download PDFInfo
- Publication number
- KR0177397B1 KR0177397B1 KR1019950043735A KR19950043735A KR0177397B1 KR 0177397 B1 KR0177397 B1 KR 0177397B1 KR 1019950043735 A KR1019950043735 A KR 1019950043735A KR 19950043735 A KR19950043735 A KR 19950043735A KR 0177397 B1 KR0177397 B1 KR 0177397B1
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- wafer
- etching groove
- cutting method
- separation line
- cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
- Processing Of Stones Or Stones Resemblance Materials (AREA)
Abstract
본 발명은 웨이퍼 절단방법에 있어서, 웨이퍼의 분리라인에 식각홈을 형성하고, 분리라인에 식각홈이 형성된 웨이퍼에 물리적인 힘을 가하여 상기 웨이퍼가 절단되도록 한 것을 특징으로 하는 웨이퍼 절단방법에 관한 것이다.The present invention relates to a wafer cutting method comprising forming an etching groove in a separation line of a wafer and applying a physical force to the wafer having the etching groove formed in the separation line to cut the wafer. .
Description
제1도는 본 발명의 웨이퍼 절단방법을 설명하기 위한 도면이다.1 is a view for explaining a wafer cutting method of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 웨이퍼 11 : 불순물층10 wafer 11 impurity layer
12 : 식각홈12: etching groove
본 발명은 웨이퍼(WAFER) 절단방법에 관한 것으로써, 특히 웨이퍼를 절단하여 칩(CHIP)단위로 분리하는 쏘잉(SAWING)공정에서 웨이퍼의 파손을 방지하기에 적당하도록 한 웨이퍼 절단방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer cutting method, and more particularly, to a wafer cutting method suitable for preventing wafer breakage in a sawing process in which a wafer is cut and separated into a chip unit.
종래의 웨이퍼 절단방법은 웨이퍼 상에 칩단위로 나눈 분리라인에 다이아몬드 휠(Diamond Wheel)을 위치시켜, 회전시킴으로써 기계적인 힘을 이용하여 웨이퍼를 절단하였다.In the conventional wafer cutting method, a diamond wheel is placed on a separation line divided by chips on a wafer and rotated to cut a wafer using mechanical force.
그러나 종래의 웨이퍼 절단방법으로는 다이아몬드휠이 회전시 다이아몬드휠과 웨이퍼 사이에 발생되는 마찰에 의한 열로 칩단위로 절단된 웨이퍼에 손상을 주게 되는 문제점이 발생한다.However, in the conventional wafer cutting method, there is a problem in that the diamond wheel is damaged by the heat generated by the friction generated between the diamond wheel and the wafer during the chip damage.
즉, 종래의 웨이퍼 절단방법에서는 다이아몬드휠의 회전조건과 웨이퍼의 절단조건을 규정하여야 하며, 다이아몬드의 기계적인 힘에 의해 웨이퍼상에 손상을 주며, 또한 절단면이 평탄하지 못한 문제점이 발생한다.That is, in the conventional wafer cutting method, the rotation conditions of the diamond wheel and the cutting conditions of the wafer must be defined, which causes damage on the wafer by the mechanical force of the diamond, and also causes a problem that the cut surface is not flat.
본 발명의 웨이퍼 절단방법은 이러한 문제점을 해결하고자 안출된 것으로써, 웨이퍼를 칩단위로 절단시 칩에 손상을 최소한으로 줄이는데 그 목적이 있다.The wafer cutting method of the present invention is devised to solve such a problem, and an object thereof is to reduce damage to a chip to a minimum when cutting a wafer in chip units.
본 발명은 웨이퍼의 분리라인에 식각홈을 형성하고, 식각홈이 형성된 웨이퍼에 물리적인 힘을 가함으로써 웨이퍼가 절단되도록 한 것을 특징으로 하는 웨이퍼 절단방법에 관한 것이다.The present invention relates to a wafer cutting method characterized in that the etching groove is formed in the separation line of the wafer and the wafer is cut by applying a physical force to the wafer on which the etching groove is formed.
제1도는 본 발명의 웨이퍼 절단방법을 설명하기 위한 도면으로, 이하 첨부된 도면을 참고로 하여 본 발명의 웨이퍼 절단방법을 설명하면 다음과 같다.1 is a view for explaining a wafer cutting method of the present invention. Hereinafter, the wafer cutting method of the present invention will be described with reference to the accompanying drawings.
본 발명의 웨이퍼 절단방법은 제1도의 (a)와 같이, 우선 칩단위로 나뉘어진 웨이퍼(10)상의 분리라인에 불활성 가스 또는 실리콘(Si), 산소(O2)를 이용하여 불순물층(11)을 형성한다.In the wafer cutting method of the present invention, as shown in FIG. 1A, an impurity layer 11 is formed by using an inert gas, silicon (Si), or oxygen (O 2 ) in a separation line on a wafer 10 divided into chip units. ).
이때, 불순물층(11)은 웨이퍼의 단층에 있어서, 최소한 디누디드존(DENUDED ZONE) 이상의 깊이로 형성되며, 불순물층은 웨이퍼의 분리라인에 있어서 물리적인 충격에 의해 결정구조가 파괴된 실리콘 격자층이다.At this time, the impurity layer 11 is formed at a depth of at least DENUDED ZONE or more in a single layer of the wafer, and the impurity layer is a silicon lattice layer whose crystal structure is destroyed by physical impact in a separation line of the wafer. to be.
즉, 웨이퍼(A)의 분리라인에 손상을 최대화시키기 위하여 분리라인 상에 불순물 이온주입을 실시한다.That is, impurity ion implantation is performed on the separation line in order to maximize damage to the separation line of the wafer A.
이어서 제1도의 (b)와 같이, 불순물층(11)을 건식식각방법으로 식각을 실시하여 식각홈(12)을 형성한다.Subsequently, as shown in FIG. 1B, the impurity layer 11 is etched by a dry etching method to form an etching groove 12.
이때, 식각홈(12)은 U자의 형태로 형성한다.At this time, the etching groove 12 is formed in the shape of a U.
그리고 제1도의 (c)와 같이, 분리라인에 식각홈(12)이 형성된 웨이퍼에 외부적인 힘을 가하여 웨이퍼(A)가 칩단위로 절단되도록 한다.As illustrated in FIG. 1C, an external force is applied to the wafer on which the etching groove 12 is formed in the separation line so that the wafer A is cut in units of chips.
이때, 실리콘격자의 면방향이 (100)인 웨이퍼일 경우에는 절단면이 면방향이 (100)이 되며, 이 (100)면은 웨이퍼의 결합면중 가장 약한 결합면이기 때문에 균열은 좌우방향이 아닌 상하방향으로 (식각홈이 형성된 지점을 기준으로 상하방향으로)일어난다.In this case, in the case of the wafer in which the plane of the silicon lattice is (100), the cut plane becomes the plane of the plane (100), and since the (100) plane is the weakest bond among the bond planes of the wafer, the crack is not left and right. It occurs in the vertical direction (up and down direction based on the point where the etching groove is formed).
즉, 도면 제1도의 (c)에 표시된 U자의 식각홈의 A부분은 웨이퍼에 가해지는 외부적인 힘에 의해서 파손되기 가장 쉬운 부분으로, 웨이퍼에 외부적인 힘을 가할 경우 웨이퍼의 재료인 실리콘의 면방향으로 균열이 전파되어 웨이퍼가 절단된다.That is, the portion A of the U-shaped etching groove shown in (c) of FIG. 1 is the most easily broken by the external force applied to the wafer. When the external force is applied to the wafer, the surface of silicon, which is the material of the wafer, is The crack propagates in the direction to cut the wafer.
본 발명에 의한 웨이퍼 절단방법에 있어서는, 종래의 웨이퍼 절단방법이 다이아몬드휠의 회전조건 및 웨이퍼의 절단조건 등을 규정하여야 하며, 다이아몬드의 기계적인 힘에 의해 웨이퍼상에 손상을 주며, 절단면이 평탄하지 못하게 되고, 기계적인 마찰에 의해 발생한 열이 칩의 분리라인에 영향을 미치는 것에 비하여 웨이퍼의 특성 즉, 웨이퍼의 실리콘 격자의 면방향을 고려하므로 기계적인 영향을 전혀 받지 않게 된다.In the wafer cutting method according to the present invention, the conventional wafer cutting method must define the rotation conditions of the diamond wheel and the cutting conditions of the wafer, and damages the wafer by the mechanical force of the diamond, and the cutting surface is not flat. Since the heat generated by the mechanical friction affects the separation line of the chip, the mechanical properties of the wafer, that is, the plane direction of the silicon lattice of the wafer are considered, and thus the mechanical influence is not affected at all.
또한 본 발명에 의한 웨이퍼 제조방법에서는 칩의 측면, 즉 분리라인의 절단면이 종래의 비하여 평탄하게 형성되고, 종래 기술에서 웨이퍼의 분리시에 발생되었던 다이아몬드휠과 분리라인 간에 마찰에 의해 발생된 마찰열로 인하여 칩이 손상을 입게 되는 것이 방지되어, 이후의 공정에서 완성되는 반도체 소자 제품의 신뢰성이 향상된다.In addition, in the wafer manufacturing method according to the present invention, the side surface of the chip, that is, the cut surface of the separation line is formed to be flat as compared with the conventional one, and the frictional heat generated by the friction between the diamond wheel and the separation line generated during separation of the wafer in the prior art. This prevents the chip from being damaged, thereby improving the reliability of the semiconductor device product to be completed in a later process.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950043735A KR0177397B1 (en) | 1995-11-25 | 1995-11-25 | Slicing method of semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950043735A KR0177397B1 (en) | 1995-11-25 | 1995-11-25 | Slicing method of semiconductor wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970030403A KR970030403A (en) | 1997-06-26 |
| KR0177397B1 true KR0177397B1 (en) | 1999-04-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950043735A KR0177397B1 (en) | 1995-11-25 | 1995-11-25 | Slicing method of semiconductor wafer |
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| Country | Link |
|---|---|
| KR (1) | KR0177397B1 (en) |
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1995
- 1995-11-25 KR KR1019950043735A patent/KR0177397B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR970030403A (en) | 1997-06-26 |
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