KR0176346B1 - Apparatus for variably controlling the frame number of compressed video data - Google Patents

Abstract

The present invention relates to a control apparatus of a video data frame that is compressed during a video compression process in a videoconferencing system. In particular, the number of frames of video data to be compressed is variably adjusted within a maximum of 30 frames per second and transmitted according to a network transmission rate. An apparatus for controlling a variable number of compressed image data frames in which the amount of data to be processed and the amount of image compressed data generated by compression processing are proportional to each other.

That is, when the magnitude of the quantization coefficient value is greater than or equal to the set quantization coefficient value, the predetermined number of frames of data to be input is made into a high impedance state so that the compression processing section skips the data without compressing the data. The cumulative amount of compressed data can be adjusted according to the low transmission speed, preventing inefficient image compression in the future and preventing loss of the compressed image data stream. do.

Description

Compressed video data frame rate variable control device

1 is a block diagram of the apparatus for controlling a variable number of compressed image data frames according to the present invention.

FIG. 2 is a block diagram of an image compression processing stage shown in FIG.

3 is a block diagram illustrating a configuration of an interface unit in FIG. 2;

4 is a block diagram illustrating a configuration of a control unit in FIG. 3;

5 is a timing diagram of signals generated in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

100: Image A / D (Analog / Digital) conversion processing unit

200: video common format processing stage 300: video compression processing stage

310: interface unit 311: control unit

311a: Quantization Coefficient Comparator 311b: FS Converter

311c: ANDGATE 311d: Frame Count Counter

311e: control signal generator 312: processing unit

313: delay unit 320: compression processing unit

330: BCH coder 400: network connection processing stage

The present invention relates to a control apparatus of a video data frame that is compressed during a video compression process in a videoconferencing system. In particular, the number of frames of video data to be compressed is variably adjusted within a maximum of 30 frames per second and transmitted according to a network transmission speed. An apparatus for controlling a variable number of compressed image data frames such that the amount of data to be compressed and the amount of image compressed data generated by compression processing are proportional to each other.

In general, video communication service systems such as high-definition TV, CATV, video conferencing, video telephony, and video information retrieval system require a large amount of information to be processed and require a broadband transmission line. It is necessary to compress and transmit the image data within.

The video information is provided to the viewer as a series of video screens or frames, and the movement of the scene is represented by a small change between successive frames.

Since video information is provided very quickly at a rate of about 30 frames / second, successive changes between frames appear to be moving naturally in the human eye. The video image is composed of space and time domain information. The space domain information is represented as a change in each frame, and the time domain information is provided as an image, that is, a change existing between frames over time. Changes between neighboring frames or during 1/30 seconds are mostly fine, so the object appears to move naturally.

In a digital imaging system, each frame of an image is sampled pixel by pixel. The sample value representing the brightness of the pixel is quantized to 8 bits per pixel in the black and white image. In a color image, each pixel has three brightness information representing color information, for example, RGB (red, green, blue), and is quantized with 8 bits. Since the image information thus constructed has a very large amount of information, an image compression (or encoding) technique is required for transmission or storage, which mainly uses a method of removing north-north information in a space and time domain.

In general, the redundancy in the spatial domain is due to the small degree of change between adjacent pixels in a frame, and the redundancy in the time domain is due to the slight difference in the movement of objects between adjacent frames.

Such image compression technology may be divided into three stages of compressing and encoding a signal input from various video signal sources into a common intermediate format through a preprocessing process. The compressed image is transmitted through the digital transmission path, received by the receiver, reconstructed into a common intermediate format, and then displayed through post processing.

In this case, the compressed image data is generally compressed by a quantization coefficient value generated by the quantizer. In this case, the quantization coefficient value required for compression is determined according to the remaining data amount state of the transmission buffer memory storing the compressed data. That is, if there is a margin in the capacity of the transmission buffer memory, the quantization coefficient value is output small to increase the compression ratio, and if there is no margin, the quantization coefficient value is output large and the compression ratio is reduced.

However, the buffer capacity is different as described above because the transmission speed of the final output stage, that is, the network connection processing stage, is different.

In other words, when the transmission speed of the network connection processing stage is high, there is a problem in that the change of the input image increases momentarily and the amount of compressed data increases, thereby degrading the quality of the restored image. In addition, when the transmission speed of the network connection part is low, the remaining data capacity of the transmission buffer is continuously increased, thereby increasing the quantization coefficient value. As a result, the amount of image data compressed and input per second becomes larger than the amount of data output per second in the network access processing stage, resulting in inefficient image compression for subsequent input images due to accumulated compressed data. Loss of compressed video data stream may occur at transmission speed.

SUMMARY OF THE INVENTION The present invention is to solve a problem occurring at a low transmission rate among the above problems, and performs image compression by controlling common digital image data input by a quantization coefficient value generated in an image compression processing unit in units of frames. However, it aims to improve the reliability of the image being restored and the system as a whole by providing a device that can process the video compression frame variably within 30 frames per second regardless of the transmission speed in the next network access processing stage. It is done.

In accordance with one aspect of the present invention, there is provided an apparatus for controlling variable number of compressed video data frames, comprising: an image A / D conversion processing stage for inputting an analog video signal, converting it into a digital video signal, and outputting it in units of frames; An image common format processing stage for generating a digital video signal in units of frames input from the stage in a form required for image compression regardless of the format of the first input video signal and outputting 30 frames per second, and outputting from the image common format processing stage. A compressed image data control device comprising a video compression processing stage for inputting data and various signals, compressing the input image data into a compressed video data stream, and transmitting the compressed data stream to a network connection processing stage that is a final output stage in units of frames. The image compression processor is configured to perform the second compression from the image common format processor. An interface unit configured to control and output a frame of data input by 30 frames according to a comparison result between a current quantization coefficient value and a quantization coefficient value preset by a user; A compression processing unit for outputting a quantization coefficient value for data compression to the interface unit according to the remaining data capacity of the transmission buffer which is changed by the transmission speed of the final output stage, and compressing the data frame output through the interface unit; The BCH coder unit checks the error state of the compressed data through the compression processing unit and inserts error correction / detection-capable data to detect the state at the receiver and restore the original image data or to know whether an error is included. It is characterized by including.

The interface unit generates a first frame discrimination signal generated whenever data is output in units of frames by the image A / D conversion processing stage and a second frame generated by receiving the first frame discrimination signal by the video common format processing stage. Inputting a fourth frame discrimination signal with a delayed frame discrimination signal, a quantization coefficient value generated by the compression processor, and a macroblock discrimination signal which is a basic unit of compression processing, to input an output state of the data frame inputted from the image common format processor; A control unit for controlling; The processing unit outputs the data frames that are currently input while the control signal is output from the control unit to a high impedance state so that the compression processing unit does not perform compression processing. If the control signal is not output, the processing unit outputs the data frames to the compression processing unit and compresses them. Wow; And a delay unit for inputting a second frame discrimination signal from the processor to delay the third frame discrimination signal generated by the control signal of the controller and outputting the delayed third frame discrimination signal to the controller and the compression processor.

The control unit may include: a quantization coefficient comparator configured to compare a quantization coefficient value preset by a user with a current quantization coefficient value generated by the compression processor, and to output a skip signal when the current quantization coefficient value is greater than or equal to; An FS converter for outputting one clock of a system clock high whenever a first frame discrimination signal generated by the video A / D conversion processing stage is input; An AND gate which logically multiplies a skip signal which is an output signal of the quantization coefficient comparator and an output signal of the FS converter; Enabled by the first high output signal of the AND gate, the next input high output signal counts the number of frames of data and initializes when it matches the number of frames set by the user. The reset signal is output to the quantization coefficient comparator. A frame number counter for turning off the skip signal; And a control signal generator enabled by the first high output signal of the AND gate and outputting a control signal to the processor until a reset signal is generated at the frame number counter.

Hereinafter, an embodiment of the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of an apparatus for controlling a variable number of compressed image data frames according to the present invention. FIG. 2 is a block diagram of an image compression processor in FIG. 1, and FIG. 3 is a block diagram of an interface unit in FIG. 4 is a block diagram illustrating the configuration of the controller in FIG. 3, and FIG. 5 is a timing diagram of signals generated according to the present invention.

The configuration of the present invention according to FIG. 1 includes an image A / D conversion processing stage 100, an image common format processing stage 200, an image compression processing stage 300, and a network connection processing stage 400. do.

The video A / D conversion processing stage 100 inputs an analog video signal, converts it into a digital video signal, outputs it to the video common format processing terminal 200 in units of frames, and distinguishes a frame of the output video signal. The first frame discrimination signal FS is output to the image common format processor 200 and the image compression processor 300.

The image common format processing unit 200 converts a digital image signal in a frame unit input from the image A / D conversion processing unit 100 into a form necessary for image compression regardless of the format of the first input image signal. D [0: 7]), a recording signal SMCW indicating that data is output to the image compression processing stage 300, and the image A for distinguishing a frame finally output from the image common format processing stage 200. Each time the first frame discrimination signal FS of the / D conversion processing stage 100 is input, the second frame discrimination signal FSI with only one clock high and the first block discrimination signal for distinguishing blocks in the frame A BSI is generated and output to the image compression processor 300.

As shown in FIG. 5, the second frame discrimination signal FSI is output after being delayed for a predetermined time with respect to the first frame discrimination signal FS. This delay is caused by a processing operation in the video common format processing stage 200. That is, each time the high clock of the second frame discrimination signal FSI occurs, the recording signal SMCW is output and the data D [0: 7] is transmitted in units of frames.

The image compression processing unit 300 inputs data and various signals outputted from the image common format processing unit 200 to compress the input image data into a compressed image data stream to make a network connection processing unit on a frame basis ( 400).

The configuration of the image compression processing stage 300 according to FIG. 2 includes an interface unit 310, a compression processing unit 320, and a BCH coder unit 330.

The interface unit 310 may have a first frame discrimination signal FS of the image A / D conversion processing stage 100, a first block discrimination signal BSI of the image common format processing stage 200, and a common format. Data D [0: 7], the recording signal SMCW and the second frame distinguishing signal FSI, the quantization coefficient value Q [0: 4] generated by the compression processor 320, and the compression process. The macroblock discrimination signal MB, which is a basic unit of the input signal, is input to control the output state of the data frame input from the video common format processing terminal 200.

The compression processor 320 compresses a data frame output from the interface unit 310 according to a current quantization coefficient value Q [0: 4], which is a second frame output from the interface unit 310. Processing is performed according to the state of the fourth frame distinguishing signal FSB, which is a delay signal of the distinguishing signal. That is, if the fourth frame distinguishing signal FSB does not match the system clock, that is, neither high nor low, the data frame input at that time is not compressed. Here, the quantization coefficient value Q [0: 4] is a transmission buffer (included in the image compression processing stage 300) which varies according to the transmission speed of the final output stage, that is, the network connection processing stage 400 shown in FIG. Depends on the residual data capacity. In other words, if the residual data capacity of the transmission buffer is small, the size of the quantization coefficient value is small, and if the residual data capacity is large, the size of the quantization coefficient value is large.

The BCH coder 330 checks the error state of the data compressed through the compression processor 320 and inserts error correction / detectable data to detect the state at the receiving end and restore the original image data or error. It is output to the network connection processing stage so as to know whether or not is included.

The configuration of the interface unit 310 according to FIG. 3 includes a controller 311, a processor 312, and a delay unit 313.

The controller 311 may include a first frame discrimination signal FS generated whenever data is output in a frame unit from the image A / D conversion processing stage 100 and the image common format processing stage 200. The fourth frame discrimination signal FSB, which delays the second frame discrimination signal FSI generated by receiving the first frame discrimination signal FS, and the quantization coefficient value Q [0:] generated by the compression processor 320. 4]) and outputting the data frame D [0: 7] input from the image common format processing stage 200 to the processing unit 312 by inputting a macroblock discrimination signal MB which is a basic unit of compression processing. Control the state.

The processing unit 312 makes the data frames D [0: 7] currently input while the control signal CRTL is output from the control unit 311 into three states, and the compression processing unit 320 compresses them. If the control signal CRTL is not output, the signal is output to the compression processor 320 to be compressed.

The delay unit 313 delays the third frame discrimination signal FSE generated by inputting the second frame discrimination signal FSI from the processor 312 and outputs the delayed third frame discrimination signal FSE to the controller 311 and the compression processor 320. do.

As shown in FIG. 5, the third frame discrimination signal FSE is a signal delayed for a predetermined time with respect to the second frame discrimination signal FSI of the image common format processing stage 200, which is the delay unit. It is inputted to 313 and delayed again for a predetermined time. At this time, the delay of the generated second frame discrimination signal FSI is caused by the processing operation in the processing unit 312.

The control unit 311 according to FIG. 4 comprises a quantization coefficient comparator 311a, an FS converter 311b, an AND gate 311c, a frame number counter 311d, and a control signal generator 311e. Include.

The quantization coefficient comparator 311a compares the quantization coefficient value preset by the user with the current quantization coefficient value Q [0: 4] generated by the compression processor 320 to compare the current quantization coefficient value Q [ 0: 4]) outputs skip signal SKIP if it is greater or equal.

At this time, the quantization coefficient value set by the user is adjustable and is selected as a number between 0 and 31.

The FS converter 311b outputs one clock of the system clock high every time the first frame discrimination signal FS generated by the video A / D conversion processing stage 100 is input.

The AND gate 311c logically multiplies the skip signal SKIP which is the output signal of the quantization coefficient comparator 311a and the output signal FSS of the FS converter 311b.

The frame number counter 311d is enabled by the first high output signal of the AND gate 311c and is initialized when the number of frames of data is counted as the next high output signal to match the frame number set by the user. The reset signal RST is output to the quantization coefficient comparator 311a so that the skip signal SKIP is turned off.

The control signal generator 311e is enabled by the first high output signal of the AND gate 311c to the processing unit 312 until a reset signal RST is generated at the frame number counter 311d. Output (CTRL)

Referring to the operation of the present invention made of the above configuration as follows.

The video A / D conversion processing stage 100 receives an analog video signal, converts it to digital, and then outputs it to the video common format processing stage 200 in units of 8-bit frames. At this time, whenever one frame of 8 bits is output, the first frame distinguishing signal FS indicating the time point is output to the image common format processor 200 and the image compression processor 300 at the same timing as that of FIG. . Here, the period of one frame is about 33.333 ms when calculated as an output of 30 frames per second.

Thereafter, the image common format processing stage 200 compresses the image regardless of the signal type at the time of first inputting the digital image data D [0: 7] input from the image A / D conversion processing stage 100 in units of frames. It is made in a common format necessary for the output to the image compression processing stage 300 in units of frames. This is achieved by the first frame discrimination signal FS received from the video A / D conversion processing stage 100. That is, the first frame discrimination signal FS is applied only during the time when the image data is processed in a common format. The second frame discrimination signal FSI is generated by delay. The timing of the second frame discrimination signal FSI is delayed by a predetermined time with respect to the first frame discrimination signal FS as shown in FIG.

As described above, the data generated and output by the image common format processor 200 outputs the recording signal SMCW and the second frame distinguishing signal FSI to the image compression processor 300 whenever one frame is output. In addition, the first block discrimination signal BSI is output whenever each block constituting the frame is output.

Accordingly, the image compression processor 300 compresses the input data in units of frames.

The image data D [0: 7], the recording signal SMCW, the second frame discrimination signal FSI, and the first block discrimination signal BSI, which are input to the image compression processing stage 300, are interface units ( The first frame discrimination signal FS is input to the processing unit 312 in the 310, and is output to the control unit 311 in the interface unit 310.

The processing unit 312 of the interface unit 310 inputs the data D [0: 7] input by the recording signal SMCW in units of frames as the second frame discrimination signal FSI. The output state varies depending on the presence or absence of the control signal CTRL output from the control unit 311 in the interface unit 310. The second frame discrimination signal FSI input to the processor 312 is a third frame discrimination signal FSE slightly delayed by a series of operations in the processor 312. ) Is delayed for a predetermined time. The fourth frame discrimination signal FSB generated thereby is output to the controller 311 and the compression processor 320. The timing state of the third frame discrimination signal FSE and the fourth frame discrimination signal FSB at this time is as shown in FIG. 5.

The operation of the control unit 311 for controlling the data output state in the processing unit 312 is as follows.

First, the controller 311 inputs the first frame discrimination signal FS received from the video A / D conversion processing stage 100 to the FS converter 311b to generate a high clock of the first frame discrimination signal FS. Each time, one clock is generated as shown in FIG. This is output to the AND gate 311c.

In this case, the quantization coefficient comparator 311a receives the quantization coefficient value Q [0: 4] and the macroblock discrimination signal MB generated by the compression processor 320, and the quantization coefficient value preset by the user. Compare. As a result of the comparison, if the current quantization coefficient value Q [0: 4] is smaller than the set quantization coefficient value, the skip signal SKIP is not generated. As a result, the output state of the AND gate 311c also becomes a low state so that the control signal CTRL is not generated in the control signal generator 311e. That is, the data D [0: 7] input to the processing unit 312 is directly transmitted to the compression processing unit 320 and the fourth frame of the recording signal Win, the second block distinguishing signal BSE, and the delay unit 313. It is output along with the distinguishing signal FSB and compressed. As described above, when the quantization coefficient value Q [0: 4] is smaller than the set value, it means that the transmission speed in the network access processing unit 400 is fast, so that the blocking phenomenon does not appear in the restored picture quality.

However, if the transmission speed of the network access processing unit 400 is slow and the quantization coefficient value Q [0: 4] generated by the compression processor 320 becomes large, the quantization coefficient comparator 311a may skip the signal SKIP. ) Will be displayed in a high state. This is logically multiplied by the output signal of the FS converter 311b at the AND gate 311c so that a high signal is output whenever a high signal FSS is generated at the FS converter 311b. At this time, the output of the AND gate 311c generates the same clock as the system clock of one clock of the output signal FSS of the FS converter 311b.

The frame number counter 311d and the control signal generator 311e are enabled by the high signal of the AND gate 311c generated as described above, and the frame number counter 311d is operated by the AND gate 311c. When the high state of the output signal is counted to match the number set by the user, a reset signal RST is generated. In FIG. 5, the number of frames counted by the frame number counter 311d is shown as two. That is, the first high signal output from the AND gate 311c is enabled and counts into two frames starting from the second and counting up to the third.

The control signal generator 311e is enabled by the first high signal of the AND gate 311c to output the control signal CTRL to the processor 312, which is output from the frame number counter 311d. It is turned off by the reset signal RST.

Accordingly, the processor 312 makes the data D [0: 7] input while the control signal CTRL is output to the high impedance state of three states and outputs it to the compression processor 320. At the same time, the third frame discrimination signal FSE for the data which has become the high impedance state is influenced by the control signal CTRL so as to generate a signal that is neither a high state nor a low state as shown by a dotted line in FIG. 5. do. This is delayed by the delay unit 313 to generate the fourth frame discrimination signal FSB, and the compression processor 320 does not perform compression processing on the corresponding frame. That is, compression processing is not performed on two frames input while the control signal CTRL is generated.

As a result, since the compression processing unit 320 skips the compression process for the two frames, the quantization coefficient value is reduced by the compressed image data that is compressed and output.

Accordingly, the quantization coefficient value is maintained within a range of a certain size, and the amount of data compressed according to the transmission speed of the final stage is proportional, so that the loss of the compressed video data stream due to the accumulation of compressed data according to the low transmission speed is reduced. This prevents the blocking phenomenon of the restored image.

As described above, according to the present invention, when the magnitude of the quantization coefficient value is greater than or equal to the set quantization coefficient value, the data of the predetermined number of data frames is made into a high impedance state and the data is not compressed by the compression processor. By skipping, the amount of compressed data accumulated can be adjusted according to the low transmission speed of the final stage, thereby preventing subsequent inefficient image compression and preventing loss of the compressed image data stream. This improves the reliability of the entire system.

Claims (3)

A video A / D conversion processing stage that inputs an analog video signal, converts it into a digital video signal, and outputs it in units of frames; Regardless of the type, the image common format processing stage generates 30 frames per second and outputs 30 frames per second, and the data and various signals inputted from the image common format processing stage are compressed and compressed. In the compressed image data control device comprising a video compression processing stage to make a stream to the network connection processing stage that is the final output stage in units of frames, wherein the image compression processing stage is input 30 frames per second from the video common format processing stage The frame of data depends on the current quantization coefficient value (Q [0: 4]) and the user. Interface unit which controls the output according to a result of comparison between a predetermined value and quantized coefficients; The data frame D outputs the quantization coefficient value Q [0: 4] for data compression to the interface unit according to the remaining data capacity of the transmission buffer, which depends on the transmission speed of the final output stage. A compression processing unit for compressing [0: 7]); The BCH coder unit checks the error state of the compressed data through the compression processing unit and inserts error correction / detection-capable data to detect the state at the receiver and restore the original image data or to know whether an error is included. Device for controlling the number of compressed image data frames, characterized in that it comprises a. The image processing apparatus of claim 1, wherein the interface unit comprises a first frame discrimination signal FS generated whenever data is output in units of frames from the image A / D conversion processing stage, and the first frame in the image common format processing stage. The fourth frame discrimination signal FSB, which delays the second frame discrimination signal FSI generated by receiving the discrimination signal FS, and the quantization coefficient value Q [0: 4] generated by the compression processor and the compression process A control unit for controlling an output state of a data frame D [0: 7] input from the video common format processing stage by inputting a macroblock discrimination signal MB, which is a basic unit of? While the control signal CTRL is output from the control unit, the data frame D [0: 7] currently input is made into a high impedance state so that the compression processing unit does not perform a compression process on the control signal CTRL. A processing unit for outputting to the compression processing unit as it is and outputting the compression as it is; And a delay unit configured to input a second frame discrimination signal FSI from the processor to delay the third frame discrimination signal FSE generated by the control signal CTRL of the controller and output the delayed third frame discrimination signal FSE to the controller and the compression processor. Device for controlling the number of compressed image data frames, characterized in that. 3. The method of claim 2, wherein the control unit compares the quantization coefficient value preset by the user with the current quantization coefficient value Q [0: 4] generated by the compression processor to determine whether the current quantization coefficient value is greater than or equal to. A quantization coefficient comparator for outputting a skip signal SKIP; An FS converter for outputting one clock of a system clock high every time the first frame discrimination signal FS generated by the video A / D conversion processing stage is input; An AND gate which logically multiplies a skip signal SKIP which is an output signal of the quantization coefficient comparator and an output signal FSS of the FS converter; Enabled by the first high output signal of the AND gate, the next input high output signal counts the number of frames of data and initializes when it matches the number of frames set by the user, and resets the reset signal RST to the quantization coefficient comparator. A frame number counter for outputting a signal so that the skip signal SKIP is turned off; And a control signal generator which is enabled by the first high output signal of the AND gate and outputs a control signal CTRL to the processor until a reset signal RST is generated in the frame number counter. Data frame number variable control device.