KR0174910B1 - Bitstream Data Transmission Device - Google Patents

Abstract

The present invention provides a bitstream data transmission apparatus capable of adaptively adjusting the data rate according to the empty flag level of a transmission buffer for transferring data between a video or audio decoder and a computer device. To this end, the apparatus comprises a source source for supplying bitstream data; A decoder for restoring bitstream data provided from the source source to an original state; A buffer for serially connecting a plurality of first-in, first-out buffers so that the bitstream data output from the source source can be transmitted to the decoder at a constant rate; Detects the empty level of the buffer by the number of first-in first-out buffers that become empty flags among the multi-first-in first-out buffers, and the interrupt request signal having the priority determined according to the detected empty state level and the detected empty state level. It is configured to include an empty level detector that provides a value as a source source. Therefore, it is possible to deal more flexibly with the overflow or underflow of the transmission buffer.

Description

Bitstream data transmission device

1 is a block diagram of a system having a conventional bitstream data transmission apparatus,

2 is a block diagram of a system having a bitstream data transmission apparatus according to the present invention,

FIG. 3 is a detailed circuit diagram of the empty flag level detector shown in FIG.

4 is an encoder for the detected empty level,

5 is a bit allocation example of an input port of the computer device shown in FIG.

6 is an operation flowchart of the computer device shown in FIG. 2 according to detection of a full state level,

7 is an operation flowchart of the computer device shown in FIG. 2 according to the detection of the empty state level.

* Explanation of symbols for main parts of the drawings

10: computer device 20: buffer

30: video decoder 40: empty flag level detector

50: full flag level detector 41: first empty state level detection means

42: second empty state level detecting means 43: third empty state level detecting means

44: interrupt request signal generating means 45: encoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bitstream data transmission device, and more particularly, to a device for transmitting bitstream data while adjusting a transfer rate in data transmission between a video or audio decoder and a computer device.

When trying to supply a decoder for decoding (or decoding) a video or audio bitstream from a computer device that is becoming multimedia, a buffer for transmission is required between the computer device and the decoder. The transmission buffer is usually a first-in-first-out buffer (FIFO). In order to constantly transmit data between the computer device and the decoder using the first-in, first-out buffer, it is necessary to adjust the transmission rate of the first-in, first-out buffer.

1 is a block diagram of a system including a computer device 10, a decoder 30, and a transmission buffer 20 for transmitting bitstream data as described above, illustrating a case where video bitstream data is transmitted. will be. Thus, the decoder 30 used becomes a video becoder.

Looking at the previous process with reference to Figure 1 as follows. First, when predetermined video data is output from the computer device 10 in a bitstream structure, it is output to the video decoder 30 through the buffer 20, where the buffer 20 used is a first-in, first-out buffer as described above. Since it is written first, it is recorded and output. However, since the computer device 10 transmits data at a constant speed without considering the state of the buffer 20, the phenomenon that the data recorded in the buffer 20 is underflowed or overflowed may occur. have.

In order to eliminate the depletion or overflow of the above-mentioned data, a method of using a first-in, first-out buffer having a very large capacity has been proposed, but this method is full state (hereinafter referred to as FF) and half state ( Since half flag (hereinafter referred to as HF) and empty state (empty flag (hereinafter referred to as EF)) are controlled to adjust the transmission rate, it is difficult to precisely control the data transmission rate.

As another method for adjusting the data rate, there is a method of using a plurality of first-in, first-out buffers having a small capacity, but in this case, since HF cannot be detected, this also has a problem that regular adjustment is difficult. Here, FF means full state of the first-in, first-out buffer full, and HF means full state of the first-in, first-out buffer and half of the capacity of the first-in, first-out buffer. EF stands for Empty without any data recorded in the first-in, first-out buffer.

Accordingly, the present invention provides a bitstream data transmission apparatus for adaptively adjusting the data rate according to the empty flag level of a transmission buffer used when transmitting data between a video or audio decoder and a computer apparatus. There is a purpose.

In order to achieve the above object, an apparatus according to the present invention comprises a decoder for restoring the applied bitstream data to its original state; A buffer configured with a series of first-in first-out (FIFO) buffers connected in series to perform buffering on the applied bitstream data so that the applied bitstream data is transmitted to the decoder at a constant rate; When the interrupt request signal has priority by comparing the priority between the predetermined interrupt request signal applied and the currently executing function, the buffer is supplied to the first-in, first-out buffer equal to the empty level level value of the buffer. A source source for controlling a transmission amount of bitstream data; The free state level value of the buffer is detected by the number of first-in first-out buffers that become empty flags among the first-in first-out buffers, and the interrupt request signal having the priority determined according to the detected free state level value and the detected interrupt level signal are detected. And a bin level detector for providing bin levels as a source.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the present invention is directed to an empty state level of a transmission buffer for transmitting data between a computer device which is a source source for providing bitstream data and a decoder for decoding and restoring the bitstream data provided from the computer device to its original state. Accordingly, the data transfer rate from the computer device to the transmission buffer is controlled.

2 is a block diagram of a system having a data transmission apparatus according to the present invention, illustrating a case where the transmitted bitstream data is a video signal.

2 illustrates a computer device 10 which is a source source for supplying bitstream data, a buffer 20 for first-in, first-out of the bitstream data supplied from the computer device 10, and a bitstream output from the buffer 20. A bin for detecting the empty level of the video decoder 30 and the buffer 20 for restoring the data to the original state and outputting the interrupt request signal IRQ and the detected empty level value to the computer device 10. A state level detector 40 and a full state level detector 50 for detecting and outputting the full state level of the buffer 20 to the computer device 10. At this time, the buffer 20 is composed of a plurality of first-in first-out buffers (not shown) in which a plurality of first-in, first-out buffers are connected in series.

FIG. 3 is a detailed circuit diagram of the empty state level detector 40 of FIG. 2, which corresponds to the case where the buffer 20 is composed of three first-in first-out buffers.

In more detail, FIG. 3 shows the EF bit signals representing the empty states of the three first-in first-out buffers (not shown) constituting the buffer 20 as X1, X2, and X3. To the signals output from the 1,2,3 bin level detection means (41,42,43) and the 1,2,3 bin level level detection means (41,42,43) for detecting the level of the empty state. And an interrupt request signal generating means 44 for generating an interrupt request signal to the computer device 10. FIG.

In particular, the first empty state level detecting means 41 is for detecting the case where the buffer 20 is not empty at all, and X1 and X2 representing empty states of the three first-in first-out buffers (not shown). And an NAND gate G1, which is a logic element that is negatively logically multiplied by the X3 signal as an input signal, and outputs the result of the logic operation through the line L1.

The second empty state level detecting means 42 has two first-in first-out buffers (not shown) when at least one first-in first-out buffer (not shown) of the three first-in, first-out buffers (not shown) becomes empty. This is to detect the case where the state becomes empty. In order to detect these two cases, the second empty state level detecting means 42 is a logic for ORing two signals X1, X2, X3 and X1 of the three signals X1, X2 and X3 described above. Signals output from the logic devices AND gate G5 and the logic device G1 to logically multiply the output signals of the elements OR gates G2, G3, and G4, logic elements G2, G3, and G4. An inverter IN1 for inverting the inverter, an inverter IN2 for inverting the signal output from the logic element G5, an inverter IN3 for inverting the output signal of the logic element G7 described later, and And a logic element G6 for ORing the signals output from the inverters IN1 to 3.

Here, a signal in which one first-in first-out buffer (not shown) is detected to be empty is output from the logic element G6 and transmitted to the interrupt request signal generating means 44 through the line L2, and two first-in-first-outs. The signal in which the buffer (not shown) is detected to be empty is output from the logic element G5 and transmitted to the interrupt request signal generating means 44 through the line L3.

The third empty state level detecting means 43 is for detecting the case where all three first-in first-out buffers (not shown) are empty, and the logic element G7 for ORing the X1, X2, and X3 signals described above. The detected signal is output to the interrupt request signal generating means 44 through the line L4.

The interrupt request signal generating means 44 logically multiplies the detection result transmitted through the line L2 and the line L3 to output the interrupt request signal IRQ (Interrupt Request 1) to the computer device 10 ( The output signal of logic element G7 applied through G8) and line L4 is configured to be generated as an interrupt request signal having priority over the interrupt request signal output from logic element G8.

3 configured and operated as described above illustrates a case in which the above-described X1, X2, and X3 become active when they are in a low logic state. Accordingly, depending on which logic of the active state X1, X2, X3 is set, FIG. 3 may be implemented using other logic elements. 3 is an exemplary diagram illustrating a case where three first-in, first-out buffers (not shown) exist in the buffer 20, and may be changed according to the number of first-in, first-out buffers provided in the buffer 20. .

However, a free state level is detected according to the number of free state of the first-in first-out buffer used, and the computer device 10 requests an interrupt having a higher priority as the detected free state level becomes larger, and a first-in-first-out buffer (not shown). The technical idea that the smaller the empty state level is, the lower priority the interrupt is required to the computer device 10, the same applies regardless of the number of first-in, first-out buffers. When the number of first-in, first-out buffers provided in the buffer 20 is large, the number of levels of the interrupt request signal required by the computer device 10 can be subdivided. That is, when the number of first-in, first-out buffers provided in the buffer 20 is n, the interrupt request signals generated from the interrupt request signal generating means 44 may be subdivided into a maximum of n (IRQ1 to IRQn).

4 shows an encoder 44 for encoding the empty state level values detected by the first, second, and third empty state level detecting means 41, 42, and 43 and outputting them to the computer device 10. When the state level value is detected as four values through the lines L1, L2, L3, and L4, it is a 4 * 2 encoder 44 for encoding and outputting data corresponding thereto in the form of 2 bits. The encoder 45 is provided in the empty level detector 40 of FIG. The input terminal to which the (0) data of the encoder 45 is applied is connected to the line L1 to which the output signal of the first bin state level detecting means 41 is output, and (1) the input terminal to which the data is applied is the second bin. (2) The input terminal to which data is applied is connected to the line L2 to which the output signal of the logic element G6 of the state level detecting means 42 is output. The output signal of G5 is connected to the line L3 to be output, and (3) the input terminal to which data is applied is connected to the line L4 to which the output signal of the third empty state level detecting means 43 is output.

5 shows an example of bit allocation of an input port including a flag port attached to a computer device. A bit is allocated to the full state level value transmitted from the full state level detector 50, Two bits are allocated to the empty state level value transmitted from the state level detector 40. Here, two bits are A0 and A1 values output from the encoder 44.

6 is a flowchart illustrating the operation of the computer device 10 according to the full state of the buffer 20, and FIG. 7 is a flowchart illustrating the operation of the computer device 10 according to the empty state of the buffer 20.

Next, an operation of an embodiment of the present invention will be described with reference to FIG. 2.

When the bitstream data is transmitted from the computer device 10, the buffer 20 sequentially writes to the provided first-in first-out buffer (not shown). At this time, the computer device 10 transmits the data to the buffer 20 until all data is filled in a first-in, first-out buffer (not shown) configured in series, which is determined by the detection result of the full level detector 50. Are controlled accordingly.

That is, as shown in FIG. 6, the computer device 10 transmits data to the buffer 20 in a state in which a mode for detecting a flag state is set (step 61). At this time, the computer device 10 checks a flag port among the mounted input ports (not shown), and the full state data which becomes active when all of the first-in, first-out buffers (not shown) in the buffer 20 are filled in is filled. Data continues to be transmitted until authorized (steps 62 and 63).

When the full state data becomes active in step 62, the computer device 10 proceeds to step 64 to stop the data transfer operation once and perform another operation. That is, it is possible to perform a task according to a separate interrupt request.

However, since video decoder 30 continues to take the required amount of data from buffer 20, first-in, first-out buffers (not shown) of buffer 20 become empty at some instant. Detecting this is the empty level detector 40.

The empty level detector 40 detects each of the first-in, first-out buffers (not shown) in the buffer 20 from the case where the data is not empty at all to the empty state. The detected level values are configured to output log2 (n) level values for n inputs.

First, when the data is not empty at all in the first-in, first-out buffer (not shown), since X1, X2, and X3 are all applied in a high logic state, only the first empty state level detecting means 41 outputs low logic and the rest. The second and third empty state level detecting means 42 and 43 output a high logic and thus become inactive. Accordingly, no interrupt request signal is applied to the computer device 10, and the encoder 45 outputs a '00' value through the A0 and A1 output terminals since the '0111' value is applied. Encoder 45 outputs a value of '00' when the input signal is '0111', outputs a value of '01' when '1011', and outputs a value of '10' when '1101', In case of '1110', '11' is output.

Then, when all of the data recorded in the at least one first-in first-out buffer (not shown) is read by the video decoder 30 and the empty state is detected, the first empty state level detecting means 41 reads the line L1. Through the high logic output through the inactive state, the second empty state level detecting means 42 is at least one of the X1, X2, X3 signal is applied to the low logic logic logic (G2, G3, G4) Will output high logic.

Accordingly, logic element G5 outputs high logic, inverter IN1 outputs low logic, inverter IN2 outputs high logic, and inverter IN3 outputs logic logic G7 to high logic. Outputs low logic. Accordingly, the logic device G6 outputs the low logic according to the signal output from the inverter IN1 so that only the signal output through the line L2 becomes active. The encoder 45 outputs '01' as an encoding result because the currently input data is '1011', and the output encoding result '01' is output to the corresponding input port shown in FIG. 5 of the computer device 10. Is sent.

The interrupt request signal generating means 44 outputs the low logic through the logic element G8 because the low logic signal is applied through the line L2. As a result, the interrupt request signal IRQ1 becomes active and requests the computer device 10 to perform a function according to the interrupt.

Accordingly, the computer device 10 determines whether the applied interrupt request signal has priority over the function currently being performed. As a result of the determination, when the interrupt request signal currently applied has priority over the function currently in progress, the computer device 10 stops the function currently being executed and operates as shown in FIG. That is, when it is determined to perform a function according to the interrupt request signal currently applied, the computer device 10 checks the A0 and A1 input ports shown in FIG. 5 in step 71 to set a flag value for the current empty state. Detect. At this time, the detected flag value is '01' since the interrupt request signal currently generated is generated when one first-in first-out buffer (not shown) is detected to be empty. Therefore, the computer device 10 proceeds to step 72 and sequentially transmits bitstream data corresponding to the capacity of one first-in first-out buffer to the buffer 20.

However, if the authorized interrupt request has no priority over the function currently being performed, the computer device 10 ignores the authorized interrupt request and continues to perform the function that was being performed. As a result, when one first-in first-out buffer in the buffer 20 remains empty and the other first-in-first-out buffer becomes empty again, the first-in-first-out buffer becomes traced back to detect the empty state level for the two first-in-first-out buffers.

Then, when two first-in first-out buffers are empty, one of the logic elements G2, G3, and G4 of the second empty state level detecting means 42 is output in a high logic state. Since the logic device G5 is a logical product, when at least one of the outputs of the logic devices G2 and G3G4 is output in low logic, the low logic is output. Accordingly, the low logic signal is transmitted through the line L3, so that the logic element G8 of the interrupt request signal generating means 44 outputs the low logic, so that at least one first-in, first-out buffer has the same level of interrupt request as it is empty. Generate a signal. The encoder 45 outputs '10' as an encoding result because the input signal is '2'. Accordingly, the computer device 10 sequentially transmits bitstream data corresponding to the capacity of two first-in, first-out buffers to the buffer 20 when it is determined to perform processing for the currently requested interrupt.

When all the first-in, first-out buffers of the buffer 20 are empty, the level is detected from the third empty state level detecting means 43. That is, since all of the applied X1, X2, and X3 signals are applied in low logic, the logic device G7 outputs a low logic signal. Accordingly, the interrupt request signal generating means 44 outputs the interrupt request signal IRQ2 having a higher order of priority to the computer device 10 because low logic is applied through the line L4.

When the interrupt request signal IRQ2 is applied, the computer device 10 operates in the same manner as when the interrupt IRQ1 described above is applied.

Meanwhile, the encoder 45 transmits data of '11' to the input port of the computer device 10 by the signal output through the line L4. Accordingly, the computer device 20 sequentially transmits bitstream data corresponding to the capacity of three first-in first-out buffers provided in the buffer 20 when performing the service for the required interrupt signal.

As described above, the present invention adjusts the data rate transmitted from the source source to the buffer in consideration of both the empty and full state of the transmission buffer used when supplying the bitstream data supplied from the source source to the decode board, It is possible to deal more flexibly with the overflow or underflow condition of the transmission buffer, thereby improving the reliability or quality of the decoded result on the decode board.

Claims (2)

A decoder for restoring the applied bitstream data to its original state; A buffer comprising a series of first-in, first-out (FIFO) buffers connected in series and configured to buffer the applied bitstream data so that the applied bitstream data is transmitted to the decoder at a constant rate; The priority between the predetermined interrupt request signal applied and the function currently being performed is compared so that when the interrupt request signal has a priority, the first-in, first-out buffer can be filled in the same number as the free state level value of the buffer. A source source for controlling a transmission amount of the bitstream data supplied to a buffer; An interrupt request signal having a priority level determined according to the detected free state level value by detecting a free state level value of the buffer according to the number of first-in first-out buffers that become empty flags among the first-in first-out buffers of the plurality of stages; And a free state level detector for providing said detected free state level value to said source source. 2. The apparatus of claim 1, wherein the empty level detector detects the empty level value every time a first-in, first-out buffer fills up from when the first-in first-out buffer in the buffer is filled to the first-in first-out buffer is empty. Empty state level detecting means; An encoder for encoding and transmitting the detected level value so that the source source can recognize the empty state level value; And an interrupt request signal generating means configured to divide the detected free state level value into at least two groups and to generate an interrupt request signal having a different priority for each group.