KR0174723B1 - Fusing Circuit - Google Patents

Abstract

The present invention relates to a fusing circuit that can be applied to an unregulated technique that requires no adjustment in a set maker by adjusting the electrical characteristics of the IC.

According to the present invention, a fusing circuit includes a variable link, first comparison voltage output means for outputting a first comparison signal according to a fusing state of the variable link, and a second comparison voltage output for outputting a second comparison signal having a predetermined value. Means, a fusing enable means for fusing the variable link according to the input signal, a first comparison signal applied from the first comparison voltage output means and a second comparison signal output from the second comparison voltage output means, And comparing means for outputting a signal indicating a fusing state of the variable link according to the compared result.

Description

A fusing circuit

1 is a block diagram of a fusing circuit of a conventional semiconductor device.

2 is a detailed circuit diagram of the semiconductor fusing circuit of FIG.

3 is a block diagram of a fusing circuit of a semiconductor device according to an embodiment of the present invention.

4 is a detailed circuit diagram of a fusing circuit of the semiconductor device of FIG.

* Explanation of symbols for main parts of the drawings

210: variable link 220, 250: comparison signal output unit

230: fusing enable unit 240: comparison unit

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fusing circuit of a semiconductor device, and more particularly, to a highly reliable fusing circuit applicable to an unregulated technique for adjusting the electrical characteristics of an IC.

[Prior art and his problems]

In manufacturing a semiconductor IC, even if an IC having the same function is manufactured, the electrical characteristics of the manufactured IC are not the same, but variously obtained. This is complicated and it is difficult to carry out the various steps of the IC manufacturing process always under the same conditions. to be.

Therefore, the final electrical characteristics of the fabricated IC are distributed based on the design target center. However, in the products to be applied IC, the electrical characteristics need to be managed to have a very small characteristic distribution, one of which is the carrier and deviation of the frequency modulation (FM).

Generally, in NTSC video signal processing IC of VHS VCR, when 0.5Vpp video signal is input to FM circuit based on luminance signal, the tip level of synchronization signal of input video signal is 3.4 in FM circuit. MHz ± 0.1 MHz, white peak is 4.4 MHz ± 01. MHz, ie deviation is specified in the VHS specification of the VCR to output frequencies of 1.0 MHz ± 0.1 MHz.

However, even if an accurate IC design target value is set, and therefore the IC is designed and manufactured, the IC target specification may not be met accurately.

In the related art, a variable resistor is installed outside the manufactured IC in a manner to accurately meet the target specifications of the manufactured IC. Using a variable resistor installed outside the manufactured IC, the carrier and the deviation of the FM were adjusted to output the prescribed FM signal.

In the method using the variable resistor, the operator must adjust the deviation from the carrier of FM in the VCR's manufacturing line, which causes a problem such as lengthening of the manufacturing time of the VCR and an increase in manufacturing cost. Competitiveness weakened.

In order to solve the above problems, conventionally, a method of obtaining an FM signal in which the carrier and the deviation are adjusted by cutting the fusible link at both ends of the pad during the semiconductor manufacturing process is used.

Since the above method adjusts the carrier and the deviation of the FM during the manufacturing process of the semiconductor IC, the carrier and the deviation of the FM change again according to the progress of the subsequent fixing after adjusting the carrier and the deviation of the FM. A prescribed FM value could not be obtained.

Therefore, in order to solve such a problem, an unregulated technique using a variable link has appeared.

1 is a block diagram of a fusing circuit using a conventional variable link.

Referring to FIG. 1, a conventional fusing circuit outputs a comparative voltage for outputting a variable link 110 and first and second comparison signals COM1 and COM2 according to a fusing state of the variable link 110. The unit 120, a fusing enable unit 130 for fusing the variable link 110 according to the input signal CADJ, and first and second comparison signals COM1 applied from the comparison voltage output unit 120. And a comparison unit 140 for comparing the COM2) and outputting a signal indicating a fusing state of the variable link 110 according to the comparison result.

According to the conventional fusing circuit, when the variable link 110 is fused by the fusing enable unit 130 to which the input signal CADJ is applied, the first comparison signal COM1 output from the comparison voltage output unit 120 is generated. The comparison unit 140 becomes relatively larger than the second comparison signal COM2, and the comparison unit 140 compares the first comparison signal COM1 and the second comparison signal COM2 applied from the comparison voltage output unit 120 to change the variable link 110. ) Outputs a low-level signal FADJ indicating that it has been fused.

On the contrary, when the variable link 110 is not fused by the fusing enable unit 130, the first comparison signal COM1 applied from the comparison voltage output unit 120 is relatively the second comparison signal COM2. As a result, the comparator 140 outputs a high signal FADJ indicating that the variable link 110 is not fused.

2 shows a detailed view of the conventional fusing circuit of FIG.

Referring to FIG. 2, the comparison voltage output unit 120 includes an npn transistor Q11 in which a predetermined first bias Vbias1 is applied to the base, and a power supply voltage VDD is applied to the collector, and the transistor Q11. One end is connected to the emitter and the variable link 110, the resistor R11 for outputting the first comparison signal COM1 according to the fusing state of the variable link 110, and the other end of the resistor R11 One end is connected and the other end is connected to the ground power source GND, and the resistor R12 is configured to output the second comparison signal COM1 to the comparison unit 140.

The fusing enable unit 130 includes an N-type MOS transistor MN11 driven by an input signal CADJ by applying an input signal CADJ to a gate and applying a power supply voltage VDD to a drain. An npn transistor Q12 and the transistor Q12 that are connected to a source of the MOS transistor MN11 and are supplied with a power supply voltage VDD to a collector and driven according to a driving state of the N-type MOS transistor MN11. The emitter is connected to the base, the collector is connected to the variable link 110, the emitter is grounded, and includes an npn transistor (Q13) driven according to the operating state of the transistor (Q12).

In addition, the fuse enable unit 130 is connected between the source terminal of the N-type MOS transistor NM11 and the base of the transistor Q12, and a resistor R13 for applying a bias voltage to the base of the npn transistor Q12. And, one end is connected to the emitter of the npn transistor Q12 and the other end is grounded, further includes a resistor (R14) for applying a bias voltage to the base of the npn transistor (Q13).

The comparison unit 140 inputs and compares the first and second comparison signals COM1 and COM2 output from the voltage divider 120, and compares the first comparison signal COM1 with a smaller value than the second comparison signal. And outputting the first output signal and outputting a signal FADJ indicating a fusing state of the variable link 110 according to the first and second output signals of the comparison means. It is composed of the output means for.

The comparison means of the comparison unit 140 includes a P-type MOS transistor MP11 in which a predetermined second bias voltage Bbias2 is applied to a gate, and a power supply voltage VDD is applied to a source, and the P-type MOS transistor MP11. A source is connected to the drain of the first voltage, and the first comparison signal COM1 is applied to the gate from the comparison voltage output unit 120 to output a first output signal (P13) and a P-type MOS transistor (P13) A source is connected to the drain of the P-type MOS transistor MP11 in parallel with the MP13, and a second comparison signal COM2 is applied to the gate from the comparison voltage output unit 120 to output the second output signal. P type morph transistors (MP14).

The output means of the comparator 140 includes a P-type MOS transistor MP12 in which a predetermined second bias voltage Vbias2 is applied to a gate and a power supply voltage VDD is applied to a source, and a P-type MOS transistor of the comparison means. The first output signal applied from the MP13 is applied to the base and the collector, and the npn transistor Q14A having the emitter grounded, and the first output signal applied from the P-type MOS transistor MP13 of the comparing means to the base. A second output signal applied from the P-type MOS transistor MP14 of the comparing means is applied to the collector and the npn transistor Q15 with the emitter grounded, and from the P-type MOS transistor MP14 of the comparing means. The second output signal is applied to the base, the collector is connected to the drain of the P-type MOS transistor (MP12) and the emitter is made of an npn transistor (Q16) grounded.

The variable link 110 is a material used in the semiconductor IC manufacturing process, a metal or a polysilicon film is usually used. In addition, a Zener zap diode may be used instead of the variable link 110.

The operation of the fusing circuit of the conventional semiconductor device having the structure as described above is as follows.

The fusing circuit operates in two modes, one of which is a fusing mode that determines whether the variable link 110 is fused, and the other is a normal mode.

First, the operation in the normal mode will be described.

In the normal mode, since the set terminal SET is applied with a low state signal, ie, a ground level, from the outside, the variable link 110 is in a short state when the variable link 110 is not fused. In this case, the resistance value of the variable link 110 in the unfused short state is only a few Ω.

In the comparison voltage output unit 120, the bias Vbias1 is applied to the base of the transistor Q11, so that the level of the node C is higher than the level of the node A by the resistor R11. The first comparison signal COM1 is relatively low compared to the second comparison signal COM2 and is applied to the comparator 140.

In the comparing unit 140, the P-type MOS transistors MP11 and MP12 to which the bias Bbias2 is applied to the gate are turned on, and the P-type MOS transistor MP13 is turned on by the first comparison signal COM1. Accordingly, the npn transistors Q14 and Q15 are turned on, and the transistor Q16 is turned off to output a high level signal indicating that the variable link 110 is not fused to the output terminal FADJ.

Next, the operation of the fusing mode will be described.

In the fusing mode, the fusing state of the variable link 110 is determined according to the level of the signal applied through the input terminal CADJ. When the low level signal is applied to the fusing enable unit 130 through the input terminal CADJ, the N-type MOS transistor MN11 is turned off. Accordingly, the transistors Q12 and Q13 are turned off to change the variable link 110. ) Does not affect at all.

On the contrary, when the variable link 110 is to be fused, a high level signal is applied from the outside through the input terminal CADJ.

The N-type MOS transistor MN11 is turned on by the input signal CADJ in the high state, the npn transistor Q12 is turned on, and the npn transistor Q13 is saturated. Therefore, a large amount of current flows instantaneously through the variable link 110.

The variable link 110 is fused by a large amount of current flowing momentarily, and when the variable link 110 is fused, the variable link 110 is open and has an infinite resistance value (∞).

Therefore, when the variable link 110 is fused, the voltages of the nodes B and C can be expressed as follows.

Therefore, when VBVC is established and the variable link 110 is in an open state, VB_VA is established.

Here, VVbias is the voltage at the Vbias1 terminal, Vbias1 is the voltage between the base and emitter of the npn transistor Q11, and Icq1 represents the collector current of the npn transistor Q11, respectively.

In the state in which the variable link 110 is fused and opened, as shown in Equation (1), the level of the node A is relatively higher than that of the node C, so that the second comparison signal COM2 of the comparator 140 is present. ) Is relatively lower than the first comparison signal COM1.

The comparator 140 outputs a low level signal indicating that the npn MOS transistor Q16 is turned on by the low level second comparison signal COM2 and the variable link 110 is fused through the output terminal FADJ. .

However, since one end of the conventional fusing loop variable link 110 as described above, that is, the node A and the node B are directly connected, the voltage of the node A becomes the ground potential during the normal mode operation. As a result, the potential of the node B also becomes the ground voltage.

Accordingly, the node C becomes the ground voltage, and accordingly, the p-type MOS transistors MP13 and MP14 are turned on at the same time, and thus the normal mode operation as described above cannot be performed.

[Purpose of invention]

An object of the present invention is to configure the comparison voltage output means for generating the first and second comparison voltage, respectively, to accurately detect the fusing state by generating a comparative low pressure according to the fusing state of the variable link in the normal mode operation. It is to provide a fusing circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a fusing circuit capable of accurately adjusting design target values after fabrication of a semiconductor IC.

Another object of the present invention is to provide a fusing circuit applicable to an unregulated technique, which can accurately obtain a design target value of a semiconductor IC.

Still another object of the present invention is to provide a fusing circuit capable of accurately fusing and improving reliability.

It is still another object of the present invention to provide a fusing circuit that can be applied to an unregulated technique that requires no adjustment in a set maker by adjusting the electrical characteristics of the IC.

[Configuration of Invention]

The present invention for achieving the above object is a variable link, a first comparison voltage output means for outputting a first comparison signal according to the fusing state of the variable link, and a second comparison signal having a predetermined value for outputting a second comparison signal; A comparison voltage output means, a fusing enable means for fusing the variable link according to the input signal, a first comparison signal applied from the first comparison voltage output means and a second comparison signal output from the second comparison voltage output means; And compare means for outputting a signal indicating a fusing state of the variable link according to the comparison result.

In addition, the present invention is a set of a plurality of variable links, each of which is connected to the set terminal is selected in accordance with the signal applied to the set terminal, and a variable link, each of the variable link is arranged in response to the selected signal, the selected signal It is characterized by providing a semiconductor device having a plurality of fusing circuits for fusing a variable link, the characteristics of which can be adjusted in response to a signal output according to the fusing state of the variable link.

[Action]

The present invention separately configures a comparison voltage output unit for outputting a comparison signal having a constant value regardless of the fusing state of the variable link, and accurately applies the comparison voltage to accurately detect the fusing state of the variable link.

EXAMPLE

In the novel fusing circuit of the present invention, as shown in FIG. 4, the comparison voltage output unit 250 for outputting the second comparison signal COM2 having a constant value regardless of the fusing state of the variable link 210. In this configuration, the comparison unit 240 accurately applies the comparison voltage COM2 to accurately detect the fusing state of the variable link 210.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 shows a block diagram of a fusing circuit according to an embodiment of the present invention.

The fusing circuit according to the embodiment of the present invention includes a variable link 210, a first comparison voltage output unit 220 for outputting a first comparison signal COM1 according to the fusing state of the variable link 210, and A second comparison voltage output unit 250 for outputting a second comparison signal COM2 having a value, a fusing enable unit 230 for fusing the variable link 210 according to the input signal CADJ, and And compares the first comparison signal COM1 applied from the first comparison voltage output unit 220 with the second comparison voltage COM2 output from the second comparison voltage output unit 250 and varies according to the comparison result. Comparing unit 240 for outputting a signal indicating a fusion state of the link (210).

According to the fusing circuit according to the embodiment of the present invention, when the variable link 210 is fused by the fusing enable unit 230 to which the input signal CADJ is applied, the first output is output from the first comparison voltage output unit 220. The second comparison signal COM1 is relatively larger than the second comparison signal COM2 output from the second comparison voltage output unit 250, and the comparator 240 is applied from the first comparison voltage output unit 220. Since the first comparison signal COM1 is greater than the second comparison signal COM2 by comparing the first comparison signal COM1 and the second comparison signal COM2 output from the second comparison voltage output unit 250, the variable link A low level signal FADJ indicating that 210 is fused is output.

On the contrary, when the variable link 210 is not fused by the fusing enable unit 230, the first comparison signal COM1 applied from the first comparison voltage output unit 220 relatively outputs a second comparison voltage. The comparison unit 240 is smaller than the four comparison signals COM2 output from the unit 250. Accordingly, the comparison unit 240 receives the first comparison signal COM1 and the second comparison voltage applied from the first comparison voltage output unit 220. Since the first comparison signal COM1 is smaller than the second comparison signal COM2 by comparing the second comparison signal COM2 output from the output unit 250, the variable link 210 is not fused. The state signal FADJ is outputted.

FIG. 4 shows a detailed view of the fusing circuit in the embodiment of the invention of FIG.

Referring to FIG. 4, the first comparison voltage output unit 220 includes an npn transistor Q21 in which a predetermined first bias Vbias1 is applied to the base and a power supply voltage VDD is applied to the collector, and the transistor ( It is connected to the emitter of the Q21 and the variable link 210, consisting of a series resistor (R21), (R22) for outputting the first comparison signal (COM1) according to the fusing state of the variable link (210).

The second comparison voltage output unit 250 includes an npn transistor Q27 to which a predetermined first bias Vbias1 is applied to the base and a power supply voltage VDD is applied to the collector, an emitter of the transistor Q27, It is composed of resistors R25 and R26 connected in series between ground power supplies GND and outputting a second comparison signal COM2 having a constant value to the comparator 240 regardless of the fusing state of the variable link 210. lost.

The fusing-in blue 230 has an N-type MOS transistor MN21 driven by an input signal CADJ by applying an input signal CADJ to a gate and a power supply voltage VDD to a drain, and the N-type An npn transistor Q22 and a transistor Q22 that are connected to a source of a source transistor MN21 and a power supply voltage VDD is applied to a collector to be driven according to a driving state of the N-type MOS transistor MN21. The npn transistor is connected to the base, the collector is connected to the variable link 210, the emitter is grounded, npn transistor driven according to the operating state of the npn transistor Q22 is driven in accordance with the operating state of the transistor (Q22) (Q23).

In addition, the fuse enable unit 230 is connected between the drain terminal of the N-type MOS transistor MN21 and the base of the transistor Q22 to apply a bias voltage to the base of the npn transistor Q22. ), And one end is connected to the emitter of the npn transistor Q22 and the other end is grounded, and further includes a resistor R24 for applying a bias voltage to the base of the npn transistor Q23.

The comparison unit 240 inputs and compares the first comparison signal COM1 output from the first comparison voltage output unit 220 and the second comparison signal COM2 output from the second comparison voltage output unit 250. When the first comparison signal COM1 receives the second comparison signal COM2 and compares the result, the comparison result shows that the first comparison signal COM1 is smaller than the second comparison signal COM2. A comparison means for outputting one output signal or a second high fertilizer signal, and a signal FADJ indicating a fusing state of the variable link 210 according to the first and second output signals of the comparison means. It consists of an output means for.

The comparison means of the comparator 240 includes a P-type MOS transistor MP21 in which a predetermined second bias voltage Vbias2 is applied to the gate, and a power supply voltage VDD is applied to the source, and the P-type MOS transistor MP21. A P-type MOS transistor (MP23) for outputting a first output signal, to which a drain source of is connected and a first comparison signal (COM1) is applied to the gate from the first comparison power supply output unit (220), and the P-type MOS A source is connected to the drain of the P-type MOS transistor MP21 in parallel with the transistor MP23 and outputs a second output signal to which the second comparison signal COM2 is applied to the gate from the second comparison voltage output unit 250. It was made of a P-type morph transistor (MP24).

The comparison means of the comparator 240 includes a P-type MOS transistor MP22 to which a predetermined second bias voltage Vbias2 is applied to the gate, and a power supply voltage VDD is applied to the source, and the P-type MOS transistor MP22. And an npn transistor Q24 to which a first output signal applied from the P-type MOS transistor MP23 of the comparing means is applied to the base and the collector, and the emitter is grounded, and a P-type MOS transistor MP23 of the comparing means. Npn transistor Q25 having a first output signal applied from the base and a second output signal applied from the P-type MOS transistor MP24 of the comparison means applied to the collector and the emitter grounded, and the comparison means. A second output signal applied from the P-type MOS transistor MP24 is applied to the base, and the collector is connected to the drain of the P-type MOS transistor MP22, and is composed of an npn transistor Q26 loaded with an emitter.

The operation of the fusing circuit of the semiconductor device of the present invention having the structure as described above is as follows.

First, the operation in the normal mode will be described.

In the normal mode, the set terminal SET has a low level, that is, a ground level signal is applied from the outside, and when the variable link 210 is not fused, the set terminal SET has a low level through the input terminal CADJ to the fusing enable unit 230. Since the signal of is applied, the N-type MOS transistor MN21 is turned off, and thus the transistors Q22 and Q23 are turned off, so that the variable link 210 is not affected at all.

In addition, since the resistance value is only a few Ω in the SHOP state in which the variable link 210 is not fused, the voltage of the node A becomes the ground potential GNP in the first comparative voltage output unit 220. Therefore, the potential of the node B also becomes the ground potential GND.

Therefore, the first comparison signal COM1 having the ground level is output from the first comparison voltage output unit 220 to the comparison unit 240.

On the other hand, in the second comparison voltage output unit 250, the bias Vbias1 is applied to the base of the transistor Q27, so that the level of the node c is variable unlike the first comparison voltage output unit 220. Regardless of the fusing state of the link, the electric potential corresponding to the voltage difference of the resistor R26 is constantly applied.

In this case, the potentials of the node B of the first comparison voltage output unit 220 and the node B 'of the second comparison voltage output unit 250 are the same, and the resistors R21 and R22 have the same value. do.

Therefore, the level of the node C is relatively higher than the level of the node A, and the first comparison signal COM1 output from the first comparison voltage output unit 220 is received from the second comparison voltage output unit 250. The level is relatively lower than the output second comparison signal COM2 and is applied to the comparator 240.

In the comparator 240, the p-type MOS transistors MP21 and MP22 to which the bias Vbias2 is applied to the gate are turned on, and the P-type MOS transistor MP23 is turned on by the first comparison operation COM1. Accordingly, the npn transistors Q24 and Q25 are turned on, and the transistor Q26 is turned off to output a high level signal indicating that the variable link 210 is not fused to the output terminal node FADJ.

Next, the operation of the fusing mode will be described.

On the contrary, in the case of fusing the variable link 210, a high level signal is applied from the outside through the input terminal DADJ and a high state signal is applied through the set terminal SET.

The n-type MOS transistor MN21 is turned on by the high input signal CADJ, the npn transistor Q22 is turned on, and the npn transistor Q23 is saturated. Therefore, a large amount of current flows through the variable link 210.

The variable link 210 is fused by a large amount of current flowing momentarily, and when the variable link 210 is fused, the voltages of the nodes B and C can be expressed as follows.

Since VB = VB 'and R21 = R25, VB = VB'VC is established, and VB' is established when the variable link 210 is open.

Here, VVbis is the voltage at the Vbias1 terminal, Vbeq1 is the voltage between the base and emitter of the npn transistor 21, and Icq1 'represents the collector current of the transistor Q27, respectively.

In the state in which the variable link 210 is fused and opened, as shown in Equation (1), the level of the node A is higher than that of the node C, and thus, the first of the first comparative voltage output unit 220. The comparison signal COM1 becomes relatively higher than the second comparison signal COM2 of the second comparison voltage output unit 250.

Accordingly, in the comparison unit 240, the P-type MOS transistor MP24 is turned on by the second comparison signal COM2, and the second output of the high level is turned on, and the npn morph transistor Q26 is turned on by the second output signal. The low level signal is output when the variable link 110 is fused through the output terminal FADJ.

[effect]

According to the present invention as described above, by fusing the variable link using the fusing circuit after the semiconductor manufacturing process, not only accurate target design can be obtained, but also non-adjustment that requires no adjustment in the set maker by adjusting the IC's electrical characteristics. Applicable to the technology.

Also, by separately configuring a comparison voltage output unit for outputting a comparison signal having a constant value regardless of the fusing state of the variable link, the comparison voltage can be accurately applied to accurately detect the fusing state of the variable link.

Claims (6)

The first link voltage output means 220 for outputting the variable link 210, the first comparison signal COM1 according to the fusing state of the variable link 210, and the second comparison signal COM2 having a predetermined value. A second comparison voltage output means 250 for outputting the first, a fusing enable means 230 for fusing the variable link 210 according to the input signal CADJ, and a first comparison voltage output means 220. Compare the first comparison signal (COM1) applied from the second comparison signal (COM2) output from the second comparison voltage output means 250, and a signal indicating the fusing state of the variable link 210 according to the comparison result A fusing circuit comprising a comparison means for outputting the 240. The method of claim 1, wherein the comparison voltage output means 250 is connected in series between the transistor Q27 and the transistor of the transistor (Q27) and the ground voltage is applied to a predetermined first bias is applied to the base, A fusing circuit comprising a resistor (R25) and a resistor (R26) for outputting a second comparison signal (COM2) of a constant value to the comparison means (240). The first comparison voltage output unit 220 includes an npn transistor Q21 to which a predetermined first bias Vbias1 is applied to a base and a power supply voltage VDD is applied to a collector, and the transistor Q21. One end is connected to the emitter and the variable link 210, consisting of a series resistor (R21), a resistor (R22) for outputting the first comparison signal (COM1) according to the fusing state of the variable link (210) A fusing circuit characterized by the above. The method of claim 1, wherein the comparison means 240 is a first comparison signal (COM1) output from the first comparison voltage output means 220 and the second comparison voltage output from the second comparison voltage output means (250) The signal COM2 is input and the two comparison signals COM1 and COM2 are compared to output the first output signal having a high level when the first comparison signal COM1 is smaller than the second comparison signal COM2, and then compare the first comparison signal COM1 and COM2. A first means for outputting a high level second output signal when the second comparison signal COM2 is larger than the signal COM1 and a fusing state of the variable link according to the first and second output signals of the first means; And a second means for outputting a signal FADJ. The P-type MOS transistor MP21 of claim 4, wherein the first means of the comparison means 140 includes a predetermined second bias voltage Vbias2 applied to a gate and a power supply voltage ADD applied to a source. A source is connected to the drain of the P-type MOS transistor MP21 and a first comparison signal COM1 is applied to the gate from the first comparison voltage output unit 220 to output the first output signal. And a drain connected to the drain of the P-type MOS transistor MP21 in parallel with the P-type MOS transistor MP23, and the second comparison signal COM2 is gated from the second comparison voltage output unit 250. And a P-type MOS transistor (MP24) for applying to and outputting a second output signal. A set terminal is connected to each other, and a plurality of variable links in which a corresponding variable link is selected according to a signal applied to the set terminal is arranged in correspondence with each of the variable links 1: 1, and the selected variable link is fused according to an input signal. And a plurality of fusing circuits, the characteristics of which can be adjusted in response to a signal output according to the fusing state of the variable link.