KR0174609B1 - Power supply control circuit of graphic liquid crystal display - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

A circuit for supplying operating power to a light distribution lamp of a graphic liquid crystal display device.

2. The technical problem to be solved by the invention

Regardless of the actual use of the system, as the light distribution lamp is turned on, it saves power consumption and shortens the life of the light distribution lamp.

3. Summary of Solution to Invention

A power supply control circuit of a graphic liquid crystal display device according to the present invention comprises: a light distribution lamp; DC voltage source; A voltage converter converting the applied DC voltage into an AC voltage required for lighting the light distribution lamp and outputting the converted AC voltage; A switching unit connected between the DC voltage source and the voltage conversion unit and electrically connected to or disconnected under a predetermined control to selectively apply a DC voltage from the DC voltage source to the voltage conversion unit; A timer which counts down a value loaded in synchronization according to an input clock, and generates a timeout signal when the down counting value becomes 0; A first control for inputting at least one system in-use signal indicating that the system is in use, reloading the timer each time the system in-use signal is input, and blocking the switching unit in response to the timeout signal being generated; And a controller for generating a signal and generating a second control signal for conducting the switching unit.

4. Important uses of the invention

Liquid crystal display device of information equipment system.

Description

Power supply control circuit of graphic liquid crystal display

1 is a block diagram of a power supply control circuit of a graphic liquid crystal display device according to the present invention.

2 is a detailed configuration of FIG.

3 is an operation timing diagram of FIG.

* Explanation of symbols for main parts of the drawings

10: switching unit 20: DC (AC) -AC inverter

30: light distribution lamp 40: control unit

50: timer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply control circuit of a liquid crystal display device, and more particularly to a circuit for controlling an operating power supply supplied to a light distribution lamp of a graphic liquid crystal display device.

In general, an information equipment (OA) system such as a facsimile machine or a copier includes a liquid crystal display (hereinafter referred to as LCD). These LCDs are installed outside the system to inform the user of the functions for operation or to display the status of the system. In general, LCD displays system function and status information as text, but LCD which is presently displays not only text but also graphic. The former LCD is called the Character LCD and the latter LCD is called the Graphic LCD.

The graphic LCD is equipped with a fluorescent lamp for backlight (hereinafter, referred to as a light distribution lamp) to allow a user to more accurately check the function and status information of the system. However, if the light distribution lamp is not turned off, the system is turned on at the same time as the system is powered on and then turned on continuously. As such, when the system is turned on, the light distribution lamp is continuously turned on regardless of whether the user is used or not, so there is a problem in that power is unnecessarily consumed and the life of the light distribution lamp is shortened. In addition, the life of the light distribution lamp is shorter than the life of the system, there is a need to replace during use.

Accordingly, an object of the present invention is to provide a circuit for controlling the power supplied to the light distribution lamp of the graphical LCD.

Another object of the present invention is to provide a power supply control circuit for increasing the life of a light distribution lamp of a graphic LCD.

It is another object of the present invention to provide a power supply control circuit which reduces the amount of power consumed in a graphic LCD.

The present invention for achieving the above object is directed to a power control circuit that automatically cuts off the power supplied to the light distribution lamp when the user does not use the system for a predetermined time.

A power supply control circuit for a graphic LCD according to the present invention includes: a light distribution lamp, a DC voltage source; A voltage converter converting the applied DC voltage into an AC voltage required for lighting the light distribution lamp and outputting the converted AC voltage; A switching unit connected between the DC voltage source and the voltage conversion unit and electrically connected to or disconnected under a predetermined control to selectively apply a DC voltage from the DC voltage source to the voltage conversion unit; A timer which counts down a value loaded in synchronization according to an input clock, and generates a timeout signal when the down counting value becomes 0; A first control for inputting at least one system in-use signal indicating that the system is in use, reloading the timer each time the system in-use signal is input, and blocking the switching unit in response to the timeout signal being generated; And a controller for generating a signal and generating a second control signal for conducting the switching unit.

DETAILED DESCRIPTION A detailed description of a preferred embodiment of the present invention will now be described with reference to the accompanying drawings.

First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used as much as possible even if displayed on different drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a diagram schematically showing a configuration of a power supply control circuit of a graphic LCD according to the present invention.

Referring to FIG. 1, the switching unit 10 is switched according to the switching control signal CONT to conduct or cut off the voltage Vcc from the DC voltage source. The DC-AC inverter 20 converts the DC voltage VD output from the switching unit 10 into an AC voltage required for turning on the light distribution lamp 30. Then, the light distribution lamp 30 is turned on or off according to the AC voltage from the DC-AC inverter 20. The switching control signal CONT is a signal generated from the control unit 40 that controls the lighting or turning off operation of the light distribution lamp 30. The signal is a timeout generated from the timer 50 when the preset time is reached. It is generated in response to the signal TO.

In FIG. 1, the signals S1 and S2 are signals indicating that the system is currently in use, and may be various depending on the purpose. In the case of a facsimile machine or a copier, key input or touch panel input is a good example. The signal TO is a timeout signal generated when there is no use of the system for a predetermined time specified by the user, and the control unit 40 generates the switching control signal CONT based on this. The signal S3 is made of a combination of the signal S1 and the signal S2, and its role is to newly load the internal counter of the timer 50 before the timeout signal TO is generated. Because the internal counter of the timer 105 is counted down while decreasing the loaded value by 1 in synchronization with the input clock CLK, when the counting value becomes 0, the timeout signal TO is generated for one clock period. This is because when the signals S1 and S2 occur, an internal counter of the timer 50 must be newly loaded to prevent an unwanted timeout signal TO from being generated.

If the signals S1 and S2 are generated at a time interval shorter than the timeout time of the internal counter of the timer 50, the timeout signal TO is not generated, and thus the controller 40 responds to the switching control signal CONT. Occurs. Then, the switching unit 10 is short-circuited, whereby the light distribution lamp 30 is turned on. On the contrary, when the user does not use the system for a certain period of time, that is, when the signals S1 and S2 do not occur, the signal S3 made by the combination of the signals S1 and S2 does not occur, and accordingly the timer An internal counter of 50 performs down counting in synchronization with the input clock CLK. When the value counted by the internal counter of the timer 50 reaches 0, the timeout signal TO is generated, and in response, the controller 40 does not generate the switching control signal CONT. Then, the switching unit 10 is opened, and thus the light distribution lamp 30 is turned off. When the light distribution lamp 30 is turned off and the user presses a key or a touch panel, the control unit 40 generates a switching control signal CONT to short-circuit the switching unit 10 so that the light distribution lamp 30 is normally turned on. .

2 is a view showing a specific configuration of a power control circuit according to the present invention for performing the above operation.

The switching unit 10 includes a field effect transistor Q2 and a transistor Q1, and turns on / off the Vcc power according to the level of the switching control signal CONT. When the switching control signal CONT is at a high level. The transistor Q1 is turned on (in response to the generation of the second control signal) and the source-drain of the field effect transistor Q2 is applied by the source S and drain D voltages of the field effect transistor Q2 in the forward direction. The channel is turned on and the Vcc voltage from the DC voltage source is supplied to the DC-AC inverter 20. Then, the DC-AC inverter 20 receives a Vcc voltage of DC and converts it into an AC voltage required for lighting the light distribution lamp 30. When the switching control signal CONT is at a low level (in response to the occurrence of the first control signal), the transistor Q1 is shut off and the source-drain voltage of the field effect transistor Q2 is not applied, so the source-drain channel is also turned off. The VGG power from the DC voltage source supplied to the DC-AC inverter 20 is cut off. A resistor R1 and a resistor R2 connected in series are connected between the source S of the field effect transistor Q2 and the collector of the transistor Q1, and the magnitude of the resistor R1 and the resistor R2 is connected. May be selected according to the minimum voltage required for the source-drain channel on of the field effect transistor Q2 and the characteristics of the transistor Q1.

As can be seen from the above description, the switching unit 10 includes a transistor Q1, a field effect transistor Q2, and resistors R1 and R2. Transistor Q1 has an emitter, a collector, and a base terminal. The base is connected to the output terminal Q of the flip-flop 46 of the control unit 40, and the emitter is connected to the ground terminal. The field effect transistor Q2 is connected between the DC voltage source and the DC-AC inverter 20 and has a source (S), a drain (D), and a gate (G) terminal. The source S is connected to a DC voltage source, the drain D is connected to the input terminal of the DC-AC inverter 20, and the gate G is connected to the collector of the transistor Q1. The resistor R1 and the resistor R2 are connected in series between the source S of the field effect transistor Q2 and the collector C of the transistor Q1, wherein the resistor R1 and the resistor R2 are connected in series. ) Is connected to the gate G of the field effect transistor Q2.

The control unit 40 includes a NOR gate 42, an AND gate 44, and a flip-flop 46. The input terminal of the NOR gate 42 is a S3 signal for newly loading the timer 50 after the key input signal S1, which is a system busy signal, and the touch panel input signal S2 are inputted to perform a no-gating operation. Is output. The AND gate 44 performs an AND gating operation on the output of the NOR gate 42 and the reset signal RESET signal, and outputs the result of the calculation to the clear (CLR) terminal of the flip-flop 46 as an S11 signal. The deflip-flop 46 has an input terminal D and an output terminal ( ), A clock stage CLK, a preset stage PRST, and a clear stage CLR. The input terminal D and the preset terminal are connected to receive a Vcc voltage. The clock terminal CLK is connected to the OUT2 terminal of the timer 50 so that the timeout signal TO is applied. The clear terminal CLR is connected to the output terminal of the AND gate 44. Output stage ) Is connected to the base of the transistor Q1 of the switching unit 10.

The reset signal RESET input to the controller 40 is an output of the deflip-flop 46 when the system is powered on. This is to set the initial value of) to high state. The key input signal S1 and the touch panel input signal S2 are signals currently used by the system at intervals shorter than a minimum time to save power consumed by the light distribution lamp 30. The key input signal S1 is a signal generated when the user presses a key on an operating panel equipment to operate the system. The touch panel input signal S2 is attached to the surface of the LCD so that the user This signal is generated when you press the menu on the screen. In facsimile machines and copiers, these two signals are closely related to the light distribution lamp of the LCD. Depending on the intention of the user, the signals S1 and S2 may be two or more different.

The timer 205 represents a programmable interval timer (INTEL 8254) of INTEL, Inc., which is commonly used. There are three counters inside the 8254 timer. According to the present invention, the output OUT0 of the counter 0 is the input clock CLK1 of the counter 1, and the output clock 1 of the counter 1 is the input clock CLK2 of the counter 2. Is being used. Combining these three counters allows for longer time settings. The signal S3 generated by the knocking operation of the signal S1 and the signal S2 operates as the gate signal GATE2 of the counter2, which newly loads the value of the counter2. That is, whenever a key input or a touch panel input occurs, Counter 2 ignores the current counting value and loads a new value and starts counting down again. Then, the signal S1 and the signal S2 clear the deflip-flop 46 of the control unit 104 and the output ( ) To a high level to short-circuit the switching unit 10 to turn on the light distribution lamp (30).

If the system is not in use for a user-specified time, that is, the signal S3 is not generated, the counter 2 continues to count down, counting a value of zero, and counting the timeout signal TO one cycle of the clock CLK2. Occurs during. The timeout signal TO is operated as a clock of the deflip-flop 46 of the controller 40 and its output ( ) To a low level to open the switching unit 10. Then, the light distribution lamp 30 is turned off. After that, when the user presses a key or a touch panel to use the system, the deflip-flop 46 of the controller 40 is cleared again to output the output ( ) Becomes a high level, the switching unit 10 is short-circuited, and the light distribution lamp 30 is turned on again.

The timing according to the above operation is shown in FIG.

The signal S1 of FIG. 3 is a signal generated when a key is pressed, and the signal S2 is a signal generated when the touch panel is pressed. In general, when the system is powered on and stable, the reset signal RESET is at a high level, so that the signal S11 and the signal S3 are the same. The signal S3 is a signal produced by the knocking of the signal S1 and the signal S2. The signal S3 also acts as a load signal (gate signal: GATE2) of the counter 2 of the timer 50. When there is no signal S1 and signal S3 for a predetermined time K, a signal TO generated from the output terminal OUT2 of the counter 2 is generated and a deflip-flop at the rising edge Of 46) That is, since the switching control signal CONT is set at the low level, the switching unit 10 is opened and the output VD of the switching unit 10 is also at the low level, so that the light distribution lamp 30 is turned off. When the key input signal or the touch panel input signal is generated for the first time after the light distribution lamp 30 is turned off, the signal S11 and the signal S3 are generated, and the deflip-flop 46 is cleared and output ( ) Is made high again and the light distribution lamp 30 is turned on.

As described above, when the user does not use the system for a preset time, the power supply to the light distribution lamp is automatically cut off, thereby increasing the lifespan of the light distribution lamp and saving power.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (7)

A power supply control circuit of a graphic liquid crystal display for displaying the function and state of a system, comprising: a light distribution lamp; DC voltage source; A voltage converter converting the applied DC voltage into an AC voltage required for lighting the light distribution lamp and outputting the converted AC voltage; A switching unit connected between the DC voltage source and the voltage conversion unit and electrically connected to or disconnected under a predetermined control to selectively apply a DC voltage from the DC voltage source to the voltage conversion unit; A timer which counts down a value loaded in synchronization according to an input clock, and generates a timeout signal when the down counting value becomes 0; A first control for inputting at least one system in-use signal indicating that the system is in use, reloading the timer each time the system in-use signal is input, and blocking the switching unit in response to the timeout signal being generated; And a control unit for generating a signal and generating a second control signal for conducting the switching unit in other cases. The method of claim 1, wherein the controller is further configured to input a reset signal of the system and generate the first control signal for shutting off the switching unit in response to the reset signal being applied. Power supply control circuit. The power control circuit of claim 1, wherein the system busy signal is a key input signal or a touch panel input signal. The NOR gate of claim 2, wherein the control unit performs a no-gating operation on the system busy signal and outputs a result of the operation as a signal for newly loading the timer, an output of the NOR gate, and the reset signal. And a de-flop that generates the gate gate and the first control signal having a predetermined period in response to the input of the timeout signal, and is cleared according to a signal according to the operation result of the gate gate. Power control circuit. The transistor of claim 1, wherein the switching unit is connected to a transistor that is turned on in response to the first control signal and is cut off in response to the second control signal, and is connected to a difference between the DC voltage source and the voltage converter, wherein the transistor is turned on. In response to the source-drain channel being turned on so that a DC voltage from the DC voltage source is supplied to the voltage converter, and in response to the transistor being blocked, the source-drain channel is not turned on and the DC voltage from the DC voltage source is And a field effect transistor for blocking supply to the voltage converter. The transistor of claim 5, wherein the switching unit includes an emitter, a collector, and a base terminal, wherein the base is connected to an output terminal of the flip-flop, and the emitter is connected to a ground terminal, a source, a drain, And a gate terminal, wherein the source is connected to the DC voltage source, the drain is connected to an input terminal of the voltage converter, and the gate includes at least a field effect transistor connected to the collector of the transistor. Power control circuit. The switching circuit of claim 6, wherein the switching unit further comprises a first resistor and a second resistor connected in series between a source of the field effect transistor and a collector of the transistor, and a connection point thereof is connected to a gate of the field effect transistor. Power control circuit, characterized in that made by.