KR0174550B1 - Shading compensating circuit using cis - Google Patents

Abstract

The present invention is a shedding compensation circuit for compensating for black and white processing of an image in a facsimile system.

Read the white reference plane from the close-up image sensor (CIS) and digitally convert it to store the correction factor value for each pixel in the memory, input the original image signal 10msec after the next line, calculate the correction factor value and output the corrected image data To improve.

Description

Shading Compensation Circuit Using CIS

1 is a circuit diagram according to the present invention.

2 is an output waveform diagram of the ABC circuit 140 of FIG.

3 is an output waveform diagram of the calculation circuit 70 of FIG.

* Explanation of symbols for main parts of the drawings

10: CPU 20: CIS

30: operational amplifier 40: ABC circuit

50: A / D converter 60: ROM

70: operation circuit

The present invention relates to a shading compensation circuit in a facsimile system, and more particularly to a shading compensation circuit for improving image quality by compensating for monochrome processing of an image using a contact image sensor (hereinafter referred to as CIS). It is about.

Conventionally, since shedding compensation is performed by scanning image data using a CCD, there is a problem in that image quality is deteriorated due to an unbalance of fluorescent light quantity. Accordingly, an object of the present invention is to provide a shedding compensation circuit for improving image quality by compensating for black and white processing of an image using a CIS.

Hereinafter, with reference to the accompanying drawings the present invention will be described in detail.

1 is a circuit diagram according to the present invention, which includes a CPU 10 for controlling a system, a CIS 20 for scanning an image signal of an original, and an operational amplifier for amplifying and outputting the image signal scanned by the CIS 20. 30, an ABC (Auto Background Control: ABC) circuit 40 for inputting an image signal amplified by the operational amplifier 30 to obtain a peak value of the image signal and outputting a reference voltage of a predetermined level; An A / D converter 50 for inputting an image signal output from the operational amplifier 30 to convert the digital signal into a digital signal using the reference voltage of the ABC circuit 40, and a ROM 60 for storing correction coefficient data. And an arithmetic circuit 70 that calculates the image signal digitally converted by the A / D converter 50 and the correction coefficient data stored in the ROM 60 to each pixel and outputs the correction data.

FIG. 2 is an output waveform of the ABC circuit 40 of FIG. 1, and FIG. 3 is an output waveform diagram of the calculation circuit 70 of FIG.

One embodiment of the present invention will be described with reference to FIGS.

The white reference plane input from the CIS 20 is read and amplified by the operational amplifier 30. The white reference signal amplified by the operational amplifier 30 is converted into a digital signal by the A / D converter 50. Each correction coefficient of the white reference signal digitally converted by the A / D converter 50 is stored in the ROM 60 by 1728 correction coefficient values for each pixel. At this time, after 10msec of the next line, the image signal output from the CIS 20 is amplified by the operational amplifier 30. The ABC circuit 40 for inputting the image signal amplified by the operational amplifier 30 automatically outputs a constant reference voltage by catching the peak value of the image signal in order to automatically remove the fluctuation of the image signal under the influence of the environment and to produce a constant output. To the reference voltage terminal of the A / D converter 50. That is, the respective inputs of the analog image signals output from the operational amplifier 30 hold the peak voltages VR1, VR0, and VR2 with respect to VPI, VP0, and VP2 of FIG. 2, respectively, and reference voltages of the A / D converter 50, respectively. Used as As a result, the A / D converter 50 converts the analog image signal into a digital image signal and always outputs a constant image signal as shown in FIG. At this time, the calculation circuit 70 calculates the image signal digitally converted by the A / D converter 50 and the correction coefficient stored in the ROM 60 to output the corrected image signal. Here, the calculation formula calculated by the calculation circuit 70 is as follows.

이고, 보정후 출력VGo(n)=K(n)×VG(n)이 된다.Correction factor

After correction, the output VGo (n) = K (n) x VG (n).

Vp: Original image signal voltage

As described above, the optical system using CIS reads the document using the same image sensor and the cell-lens (Sel-fol) as the original, so that the optical path is shortened and the optical system can be easily adjusted to improve shedding compensation. It has the advantages of improved reliability, clearer image quality and easier operational processes.

Claims (1)

In a shedding compensation circuit of a facsimile system, a CPU 10 for controlling a system, a CIS 20 for scanning an image signal of an original, and an image signal of the CIS 20 are input to capture peak values of the image signals. The ABC circuit 40 which outputs a reference voltage of a predetermined level and the CIS 20 read image signal are input and converted into a digital image signal using the reference voltage of a predetermined level output from the ABC circuit 40. A / D converter 50, ROM 60 storing correction coefficient data of each pixel, image signal digitally converted by A / D converter 50, and correction of each pixel stored in ROM 60 A shedding compensation circuit using a CIS, comprising: a calculating circuit 70 for calculating coefficients and outputting corrected image data.