KR0173734B1 - Image vertical size auto control circuit of wide screen display apparatus - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a circuit for adjusting a vertical size of an active image on a screen according to an aspect ratio of an input image signal in a wide screen display device.

2. Technical problem to be solved by the invention

A circuit for automatically determining and adjusting a vertical size of an active image according to an aspect ratio of an input image signal is provided.

3. Summary of Solution to Invention

By determining the presence or absence of an image of the input image signal, an adjusted vertical blanking signal having a blanking section corresponding to a section without an image is generated, and the vertical blanking period is adjusted to correspond to the blanking section of the signal, thereby performing vertical deflection. In addition, it verifies the normality of the image existence section to prevent the error.

4. Important uses of the invention

It is used to adjust the vertical size of the active image according to the aspect ratio of the input image signal so that only the active image is displayed on the entire screen.

Description

Automatic Vertical Scale Circuit of Image in Wide Screen Display

1 is a display state when displaying an image in letterbox format on a screen in 4: 3 aspect ratio.

2 is a display state when displaying an image in letterbox format on a screen of 16: 9 aspect ratio.

3 is a state diagram when the image in letterbox format is stretched vertically and displayed on a 16: 9 aspect ratio screen.

4 is a circuit for automatically adjusting the vertical size of an image according to the present invention.

5 is an operation timing diagram of the image discrimination circuit 10 of FIG.

6 is an operation timing diagram of the shift register 32 in FIG.

7 is an operation timing diagram of the section detection circuit 12 in FIG.

8 is an operation timing diagram of the pulse generation circuit 16 in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wide screen display device, and more particularly to a circuit for adjusting a vertical size of an active image displayed on a screen according to an aspect ratio of an input image signal.

The display formats of most television devices which have been used so far are not only screens for projection television devices, but also 4: 3 aspect ratios in the display means implemented by the image display area of a typical cathode ray tube (cathoderay tube). has an aspect ratio. Similarly, the aspect ratio of most video sources is 4: 3.

However, not all video sources are made in 4: 3 aspect ratio. For example, a movie is converted from a film format to a videotape format for playback or transmission as a television signal. When converting these movie sources to video format, it has customarily changed the aspect ratio to 4: 3, the aspect ratio suitable for most television devices. An example of such a movie source is wide screen sources having a 16: 9 aspect ratio display format. When converting such movie sources into a videotape format, for example, a video signal converted from a 16: 9 aspect ratio movie source to a 4: 3 aspect ratio is lost as much as left and right portions cut out from the film image.

If the wide screen image is reduced in scale until the horizontal width matches the left and right borders of the 4: 3 aspect ratio screen, the vertical size of the image is smaller. As a result of this, the film source image appears completely on the 4: 3 aspect ratio screen, but at this time, the upper and lower portions of the 4: 3 aspect ratio screen are not filled with the image. In order to avoid spurious signals that may occur in areas where no image appears, a dark bar is transmitted to the upper and lower portions of the image converted to the 4: 3 aspect ratio. The particular display format thus processed is commonly referred to as letter box format. Accordingly, a letterbox image may be considered as an image having an active screen portion smaller than that of a normal video signal.

In an image such as the letter box format, the size of the image of the actual active screen portion except for the black band is changed according to the size of the source image. For example, a cinema scope size image is different from the wide screen image. Otherwise it has an aspect ratio of 2.35: 1.

For example, when the display state of the letterbox format image is displayed on a 4: 3 aspect ratio screen, the display state is as shown in FIG. 1, and the upper and lower black bands are shown. If the letterbox format image as described above is displayed as it is on the screen of the wide screen without a separate signal processing, as shown in FIG. 2, a sensation of spreading the active image from side to side occurs. In order to prevent the sensation of feeling described above, by increasing the vertical size of the letterbox format active image, as shown in FIG. 3, the active image does not spread from side to side even on a wide screen screen, and the upper and lower black bands also appear. It should not be.

Accordingly, as described above, the wide screen display apparatus is capable of displaying a full screen of a wide screen using only active images for various image sources having different aspect ratios such as 4: 3, 16: 9, and 2.35: 1. . For this purpose, some aspect ratios that are expected to be input are set in the microcomputer (MICOM) of the wide screen display device, and the user selects them according to the type of the input video signal. When the user selects one of the aspect ratios set as described above, the microcomputer adjusts the vertical size of the active image by enlarging or reducing the vertical blanking section at a ratio according to the selected aspect ratio to provide a screen suitable for the aspect ratio of the input image signal.

Therefore, in the related art, whenever the input video signal is changed to a video signal having a different aspect ratio, the user has to select an aspect ratio every time. In addition, there is a problem that it is impossible to adjust the size of the active image when inputting an image signal having a non-set aspect ratio.

Accordingly, an object of the present invention is to provide a circuit capable of automatically determining and adjusting a vertical size of an active image according to an aspect ratio of an input image signal.

Another object of the present invention is to provide a circuit capable of automatically determining and verifying a vertical size of an active image according to an aspect ratio of an input image signal and adjusting the same without error.

The present invention for achieving the above object is to determine the presence or absence of the image of the input image signal to generate an adjusted vertical blanking signal having a blanking section corresponding to the section without the image, and to correspond to the blanking section of the adjusted vertical blanking signal The vertical retrace period is adjusted so that the vertical deflection is performed. In addition, the error is prevented by verifying the normality of the discrimination of the image existence section.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description and the annexed drawings, numerous specific details are set forth, such as specific circuit configurations, circuit elements, logic states, etc., to provide a more general understanding of the invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

4 is a circuit diagram for automatically adjusting the vertical size of an image according to the present invention, and is applied to a wide screen display apparatus which receives any one of image signals of letterbox format having different aspect ratios as described above. The different aspect ratios are, for example, 4: 3, 16: 9, 2.35: 1, and the like as described above. In FIG. 4, the input video signal Vin becomes one of the video signals of letterbox format having different aspect ratios as described above. The horizontal synchronous signal is separated from the input video signal Vin as in the normal case. The vertical blanking signal V_BL is generated in the vertical deflection circuit 18 according to the vertical synchronization signal separated from the input video signal Vin as in the usual case. During the vertical deflection, vertical blanking is performed during the blanking period of the vertical blanking signal V_BL.

The circuit of FIG. 4 first determines an image presence section of the input image signal Vin. To this end, the image discrimination circuit 10 including the comparator 26, the AND gate 28, and the counter 30 sets the level of the input video signal Vin for each horizontal scan line of the input video signal Vin. The presence or absence of an image is determined by comparing with the threshold level Vth. At this time, the threshold level Vth is set to the pedestal level of the input video signal Vin. The comparator 26 compares the level of the input video signal Vin with the threshold level Vth, and outputs a logic high when the level of the input video signal Vin is less than the threshold level Vth, and outputs a low signal when the level of the input video signal Vin is less than the threshold level Vth. One input terminal of the end gate 28 is connected to the output terminal AB of the comparator 26, and a sampling clock SCLK is applied to the other input terminal of the end gate 28. In this case, the sampling clock SCLK uses a signal obtained by multiplying the horizontal frequency fh of the input video signal Vin by a constant n times as a clock as shown in (B) of FIG. 5 for obtaining a predetermined number of sample values for one horizontal scan line. As a result, the AND gate 28 outputs the result of comparing the level of the input video signal Vin and the threshold level Vth for each sampling section with respect to the horizontal scanning line as shown in FIG. The output of this AND gate 28 is provided to the counter 30 as a clock. The horizontal synchronization signal HS as shown in FIG. 5A is applied to the clear terminal CLR of the counter 30. Accordingly, the counter 30 clears every horizontal scan line by the synchronization section high of the horizontal synchronization signal HS, and then increments the pulse of the high applied from the AND gate 28 as shown in FIG. At this time, the counter 30 generates a high pulse as shown in (E) of FIG. 5 when the count value for one horizontal scan line reaches a preset value n. In other words, the counter 30 counts the number of sampling sections for each horizontal scan line, which are determined by the comparator 26 and the AND gate 28 to determine that the level of the input video signal Vin is smaller than the threshold level Vth, and sets the set value. Only when n becomes a high pulse signal indicating that the horizontal scan line is a horizontal scan line without an image. In FIG. 5, the section T1 represents horizontal scanning periods without an image and the section T2 represents horizontal scanning periods with an image.

Therefore, the image discrimination circuit 10 discriminates whether or not there is an image for each horizontal scan line of the input image signal Vin. That is, in the case of a horizontal scan line without an image, one high pulse signal is output for each horizontal scan line, and in the case of a horizontal scan line with an image, a low output is maintained.

In the above state, the section detection circuit 12 detects from the output of the counter 30 the section in which the image is present, that is, the active image section. At this time, in order to detect the active image section, an image start point and an image end point of each FID must be detected. To this end, the section detection circuit 12 includes a shift register 32, an end gates 34 and 36, counters 38 and 42, latch circuits 40 and 44, and a subtractor 46. From the output of the counter 30 of the discrimination circuit 10, the image start point and the image end point of each feed are detected, and the number of horizontal scan lines from the beginning of each feed to the image start point is output as the image start point value V_ST and the image end point is output. Outputs the number of horizontal scan lines in the image as the end point value V_SP.

At this time, the shift register 32 and the AND gates 34 and 36 are used for accurate timing control. The vertical blanking signal V_BL as shown in FIG. 6A is applied to the serial input terminal S1 of the shift register 32 and A horizontal synchronizing signal HS, such as 6 degrees B, is applied as a shift clock. Then, at the output terminals QA and QB of the shift register 32, the vertical blanking signal V_BL is sequentially shifted by the horizontal synchronizing signal HS to output signals as shown in Figs. The shift register 32 shifts the vertical blanking signal V_BL of FIG. 6A for every falling edge of the horizontal synchronization signal HS of FIG. Likewise, it is output through output terminals QA and QB. The output QA of the shift register 32 is logically multiplied by the vertical blanking signal V-BL by the AND gate 34 to be applied as a clock to the latch circuits 40 and 44 as shown in FIG. The output QB is logically multiplied by the vertical blanking signal V_BL by the AND gate 36 to be applied to the clear terminal CLR of the counters 38 and 42 as shown in FIG.

In this state, the counter 38 and the latch circuit 40 detect the video start point of the input video signal Vin. The vertical clock signal VCLK is applied to the enable terminal EN of the counter 38 that inputs the output of the counter 30 as a clock, and a signal as shown in FIG. 6 is applied to the clear terminal CLR. The vertical clock signal VCLK is a square wave signal having a duty of 50% as shown in FIG. 7C and has a frequency equal to the vertical frequency of the input video signal Vin. Therefore, the counter 38 is cleared during the high period of the signal as shown in FIG. 6F and then enabled during the period when the vertical clock signal VCLK is high, i.e., the first half Fa of every period as in FIG. Accordingly, the counter 38 outputs a signal output from the counter 30 as shown in FIG. 5E at the time t1 of FIG. Count until it appears. At this time, if the active image section is shown in FIG. 7, the section in which the actual count is made in the counter 38 becomes the C_Fa section in FIG. 7. The count value of the counter 38 is applied to the latch circuit 40. The latch circuit 40 sets the count completion value of the counter 38 at the rising edge of the signal as shown in FIG. It latches and outputs the image starting point value V_ST. Therefore, the image start point value V_ST corresponds to the number of horizontal scan lines from the time t1 of FIG. 7 at which every feed starts to the time t2 of FIG. 7 at which the image appears.

The counter 42, the latch circuit 44, and the subtractor 46 also detect the video end point of the input video signal Vin. The vertical clock signal VCLK of FIG. 7C is applied to the enable terminal EN of the counter 42 which inputs the output of the counter 30 as a clock, and a signal such as FIG. 6F is applied to the clear terminal CLR. do. Therefore, the counter 42 is cleared during the high period of the signal as shown in FIG. 6F and then enabled during the period in which the vertical clock signal VCLK is low, i.e., the second half Fb of every period as shown in FIG. Accordingly, the counter 42 calculates the number of continuous horizontal scan lines in which the signal output from the counter 30 as shown in FIG. Count until the image appears. At this time, if the active image section is shown in FIG. The count value of the counter 42 is applied to the latch circuit 44, which latches the count completion value of the counter 42 at the rising edge of the signal as shown in FIG. At this time, the latched value of the latch circuit 44 corresponds to the number of continuous horizontal scan lines determined as no image from t4 in FIG. 7 at the end of the image to t5 in FIG. 7 at the end of each period. Accordingly, the value latched in the latch circuit 44 is applied to the subtractor 46 to subtract from the number of horizontal scan lines VAL of one feed. Then, the value output from the subtractor 46 becomes the image end point value V_SP. That is, the image end point value V_SP corresponds to the number of horizontal scan lines from the time t1 of FIG. 7 at which every day starts to the time t4 of FIG. 7 at which the image ends.

Therefore, the image start point value V_ST and the image end point value V_SP are obtained from the beginning of every period.

The image start point value V_ST and the image end point value V_SP are applied to the input terminals A of the comparators 48 and 50 of the pulse generation circuit 16, respectively. At this time, the output of the counter 14 is applied to the other input terminal 8 of the comparators 48 and 50. The vertical blanking signal V_BL is applied to the clear terminal CLR of the counter 14, and the horizontal synchronization signal HS is applied as a clock. Accordingly, the counter 914 counts the number of horizontal scan lines from the start to the end of every feed after being cleared by the high of the vertical blanking signal V_BL. The counted value is output as a pointer value indicating the progress of horizontal scanning. The comparator 48 then compares the pointer value applied from the counter 14 with the image start point value V_ST applied from the latch circuit 40, i.e., the first active high when the horizontal scan proceeds to the normal start point. Generate a signal. The comparator 50 compares the pointer value applied from the counter 14 with the image end point value V_SP applied from the subtractor 46, i.e., the second active signal high when the horizontal scan proceeds to the image end point. Occurs. The first active signal is applied to the set terminal S of the R-S flip-flop 52, and the second active signal is applied to the reset terminal R of the R-S flip-flop 52. Therefore, the R-S flip-flop 52 is set by the first active signal high and reset by the second active signal high. That is, the output of the RS flip-flop 52 is set and maintained high at the moment when the horizontal scan proceeds to the start point of the image, and reset to low at the moment when the horizontal scan progresses to the end point of the image. Set and reset will be repeated continuously. As a result, a signal is generated from the output terminal Q of the R-S flip-flop 52 to a high point from the end of the image of one feed to the start of the image of the next feed, and to a low portion of the remaining section. At this time, the high section corresponds to the section without an image and the low section corresponds to the active section. The output signal of the R-S flip-flop 52 becomes the vertical blanking signal V_BL adjusted as shown in FIG. Comparing the adjusted vertical blanking signal V_BL with the original normal vertical blanking signal V_BL as shown in FIG. 8A, it can be seen that the blanking section is extended. In this case, the blanking period of the adjusted vertical blanking signal V_BL corresponds to a time point from which the image of one feed is terminated to the time of the start of the next feed image with respect to the input video signal Vin.

If the vertical deflection is caused by the adjusted vertical blanking signal V_BL generated as described above, the vertical size of the active image in the letterbox format as described above is extended so that the active image is displayed on the wide screen as shown in FIG. It will not spread from side to side and at the same time, the black band will not appear.

Therefore, when the aspect ratio of the input video signal is changed, the vertical size of the active video is automatically determined and adjusted so that 4: 3, 16: 9, 2.35 :! For example, various image sources having different aspect ratios can be displayed on the entire screen of a wide screen using only active images.

Accordingly, even if the aspect ratio is not set separately, the vertical size of the active image according to the aspect ratio of the input image signal can be automatically determined and adjusted, and the user does not have to select the aspect ratio.

Meanwhile, the following error may occur in the section detection in the section detection circuit 12 described above. First, there may be a case where a part of a specific shield in the input image signal Vin is a dark signal. In this case, the image discrimination circuit 10 may output high pulses indicating that there is no image with respect to a horizontal scan line of a part of the dark one of the active image section of 1 FD. As a result, an error occurs between the image start point value V_ST and the image end point value V_SP generated in the interval fetch circuit 12, and accordingly, the blanking section of the adjusted vertical blanking signal V_BL 'as shown in FIG. do. In this case, the vertical deflection must be performed using the original vertical blanking signal V_BL. Secondly, there may be a case where the input video signal Vin is a signal in which the entire screen is completely dark. At this time, the image discrimination circuit 10 will output high pulses indicating that there is no image for all horizontal scanning lines of one feed. Then, in the section detection circuit 120, the image start point value V_ST and the image end point value V_SP are not generated, and accordingly, the adjusted vertical blanking signal V_BL 'as shown in FIG. 8C cannot be generated. Therefore, even in this case, the original vertical blanking signal V_BL cannot be generated. Therefore, even in this case, the vertical deflection must be performed using the original vertical blanking signal V_BL.

Section composed of comparators 56, 62, counters 54, 58, 64, RS flip-flops 60, 66, and OR gate 68 to prevent the error in the first case The verification circuit 20 compares the image start point value V_ST and the image end point value V_SP detected by the section detection circuit 12 with each other, and verifies that the section detection is normal when it is continuously maintained for a predetermined number or more. .

In more detail, one input terminal A of the comparator 56 is connected to the output terminal of the latch circuit 40 and the other input terminal B is connected to the output terminal of the counter 38, and the vertical blanking as shown in FIG. The signal V_BL is input to the enable terminal EN. Therefore, the comparator 56 is enabled by the high of the vertical blanking signal V_BL at every feed to compare the output of the counter 38 with the output of the latch circuit 40. At this time, the output of the counter 38 becomes the image start point value V_ST one feed after the output of the latch circuit 40. Therefore, the comparator 56 compares the image starting point value V_ST with the value detected at the previous feed and outputs a high pulse signal to the counter 58 through the output terminal A = B for each feed. . In addition, one input terminal A of the comparator 62 is connected to the output terminal of the latch circuit 44, the other input terminal B is connected to the output terminal of the counter 42, and enables the vertical blanking signal V_BL as shown in FIG. Input to terminal EN. Therefore, the comparator 62 is enabled by the high of the vertical blanking signal V_BL at every feed to compare the output of the counter 42 with the output of the latch circuit 44. At this time, the output of the counter 42 becomes a value one feed after the output of the latch circuit 44. Therefore, the comparator 62 compares the output value of the counter 42, which is the basis of the image end point value V_SP, every time with the value detected in the previous one, and counts a high pulse signal through the output terminal A = B in the same case. Output to clock 64.

The clear terminal CLR of the counters 58 and 64 is connected to the output terminal of the counter 54. The counter 54 counts a pulse of the vertical blanking signal V_BL and generates a high signal when it is counted to a set value, that is, a set number of feeds, and applies the signal to the clear terminal CLR of the counters 58 and 64. At this time, the clear terminal CLR of the counter 54 is connected to the output terminal of the oragate 68, and the two input terminals of the oragate 58 are connected to the output terminals of the counters 58 and 64, respectively. Accordingly, the counter * 54 is cleared when a high signal is applied from the oragate 68 before counting up to the set value, thereby maintaining the output in the low state.

The set terminal S of the R-S flip-flop 60 is connected to the output terminal of the counter 58, and the reset terminal R of the R-S flip-flop 60 is connected to the output terminal of the counter 54. Therefore, the RS flip-flop 60 is set and outputs a high signal when the counter 58 completes counting up to a set value before the counter 58 is cleared by the output of the center 54, and the counter 54 outputs a high signal. When the count is completed up to the set value before it is cleared by the output, the signal is reset and the low signal is output. Similarly, the set terminal S of the R-S flip-flop 66 is connected to the output terminal of the counter 64, and the reset terminal R of the R-S flip-flop 66 is connected to the output terminal of the counter 54. Therefore, the RS flip-flop 66 is set and outputs a high signal when the counter 64 completes counting up to a set value before being cleared by the output of the counter 54, and the counter 54 is set to the counter 64. If the count is completed up to the set value before it is cleared by the output, it is reset and outputs a low signal. At this time, the count setting value at which the counter 54 generates a high signal is set to a value larger than 1 by the count setting values of the counters 58 and 64.

As a result, when the image starting point value V_ST is compared between the respective feeds by the comparator 56 and continuously maintained for a predetermined number or more of the feeds, which is the count value of the counter 54, the RS flip-flop 60 detects the interval. A high signal indicating that this is normal is output. In addition, when the output values of the counter 42, which is the basis of the image end point value V_SP, are compared between the respective feeds by the comparator 62, and are continuously maintained for a predetermined number or more of the set values counted by the counter 54, The RS flip-flop 66 outputs a high signal indicating that the section detection is normal. On the other hand, if a part of a specific portion of the input video signal Vin is a dark signal, the R-S flip-flops 60 and 66 output a low signal indicating that the section detection is abnormal. The outputs of the R-S flip-flops 60 and 66 are input to the AND gate 76 of the selection circuit 24.

In addition, in order to prevent the error in the second case described above, the image verification circuit 22 composed of the counter 70, the latch circuit 72, and the comparator 74 is used to determine that there is an image by the image discrimination circuit 10. The number of horizontal scan lines is counted for each period, and the count completion value is compared with a predetermined reference value Vref to verify that the image is valid when the reference value Vref is higher.

In more detail, the counter 7 inputs the horizontal synchronization signal HS as a clock and enables the terminal. The output of the counter 30 is applied to the signal, and a signal as shown in FIG. 6 is applied to the clear terminal CLR. Therefore, after the counter 70 is cleared during the high period of the signal as shown in FIG. 6 (F), the counter 70 is turned on during the period in which the output of the counter 30 is low, i.e., during every active image section as shown in FIG. Is enabled. Accordingly, the counter 70 outputs a low-output section from the counter 30 as shown in FIG. 5E at the time t2 of FIG. 7, which is the starting point of the image, that is, the number of continuous horizontal scan lines that are determined to be the image. Counts. The count value of the counter 70 is applied to the latch circuit 72. The latch circuit 72 latches the count completion value of the counter 70 at the rising edge of the signal as shown in FIG. Therefore, the value latched in the latch circuit 72 corresponds to the number of horizontal scan lines in which an image is present, and is applied to one input terminal A of the comparator 74. A constant reference value Vref is applied to the other input terminal B of the comparator 74, and the vertical blanking signal V_BL as shown in FIG. 6A is input to the enable terminal EN. Therefore, the comparator 56 is enabled by the high of the vertical blanking signal V_BL at every feed, and compares the output of the latch circuit 72 with the reference value Vref and outputs a high pulse signal through the output terminal AB when the reference value Vref is greater than or equal to the reference value Vref. .

As a result, when the number of horizontal scan lines with an image in one pile is greater than or equal to the reference value Vref, a high signal indicating that the image is a valid image is output from the comparator 74. On the other hand, when the input image signal Vin is a signal in which the entire screen is completely dark, the number of horizontal scan lines in which one image is contained is less than the reference value Vref, so that a low signal indicating that the input image signal Vin is not a valid image is output from the comparator 74. Will be. The output of the comparator 74 is input to the AND gate 76 of the selection circuit 24.

Accordingly, the AND gate 76 outputs high when the outputs of the RS flip-flops 60 and 66 and the comparator 74 are high, but outputs the RS flip-flops 60 and 66 and the comparator 74. If any one of them is low, it outputs low. The output of the AND gate 76 is applied to the select terminal SEL of the selector 78. A vertical blanking signal V_BL as shown in FIG. 8A is applied to one input terminal 10 of the selector 78 and the other input terminal I1. The adjusted vertical blanking signal V_BL 'as shown in FIG. 8 (C) is applied. Therefore, the selector 78 detects when the output of the AND gate 76 is high, that is, when both the section detection and the image detection are normal in the section verifying circuit 20 and the image verifying circuit 22, FIG. The vertical blanking signal V_BL 'adjusted as follows is selected and output to the vertical deflection circuit 18. On the other hand, when the output of the AND gate 76 is low, that is, when at least one of the section detection and the image detection is verified to be abnormal in the section verification circuit 20 and the image verification circuit 22, the vertical synchronization of the input video signal Vin is vertical. The vertical blanking signal V_BL shown in FIG. 8A according to the signal is selected and output.

Thereafter, the vertical deflection circuit 18 adjusts the vertical blanking period so as to correspond to the blanking period of the vertical blanking signal V_BL or the adjusted vertical blanking signal V_BL 'outputted from the selection circuit 24 for vertical deflection. As a result, the vertical size of the active image in the letterbox format as described above is extended, so that the active image does not spread from side to side on the screen of the wide screen, and the upper and lower black bands do not appear. In addition, it is possible to prevent an error that may occur by verifying whether the image is present or not.

As described above, the present invention can automatically determine and adjust the vertical size of the active image according to the aspect ratio of the input image signal without separately setting the aspect ratio, and the user does not have to select the aspect ratio. At this time, the error can be prevented by verifying the determination of the presence or absence of the image.

Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications can be made without departing from the scope of the present invention. In particular, in the embodiment of the present invention, the image section detection and the verification of the image detection have been exemplified, but this is for improving the reliability in operation, and may optionally employ only one or omit all of them. Also, in the exemplary embodiment of the present invention, the screen corresponding to the aspect ratio is displayed by changing the vertical blanking period of the vertical deflection circuit by detecting the start point and the end point of the image, but the number of horizontal scan lines carrying the image signal and the starting point and Since the end point is known, the vertical interpolation by the digital signal processing does not have to vary the vertical retrace period of the vertical deflection circuit. Therefore, the scope of the invention should not be defined by the described embodiments, but should be defined by the equivalents of the claims and the claims.

Claims (15)

A vertical size automatic adjustment circuit of an image in a wide screen display apparatus which receives any one of image signals having different aspect ratios, wherein the level of the image signal is set for each horizontal scan line of the input image signal. Image discrimination means for discriminating the presence or absence of an image, and detecting the image start point and the image end point of every feed from the output of the image discrimination means, and determining the number of horizontal scan lines from the beginning of each feed to the image start point. Section detection means for outputting the number of horizontal scan lines to the end point of the image and outputting the number of horizontal scan lines to the end point of the image; A counter means for outputting the data; A pulse generating means for generating an adjusted vertical blanking signal for sequentially comparing the phase end value to the time point at which the image of one feed ends and the time point at which the next feed image starts; And a vertical deflection means for adjusting the vertical blanking period so as to correspond to the blanking section of the blanking signal to perform vertical deflection. The vertical scale automatic adjustment circuit according to claim 1, wherein the threshold level is set to a pedestal level of the input video signal. 3. The apparatus according to claim 1 or 2, wherein the image discriminating means comprises: comparing means for comparing the level of the video signal with the threshold level for every horizontal sampling line with respect to the horizontal scanning line of the input video signal; And a counter for generating a signal indicating that the image is a horizontal scan line only when the number of sampling sections determined that the level of the image signal is greater than the threshold level is counted for each horizontal scan line and the set value is reached. Vertical size automatic adjustment circuit. 4. The method of claim 3, wherein the section detecting means counts the number from the start of every feed until the image appears, if the continuous horizontal scan is judged that there is no image, and outputs a count complete value as the image starting point value. A start point detecting means and the number of continuous horizontal scan lines determined to be absent from the image are counted from the beginning of the second half to the end of the medium, and the count completion value is subtracted from the number of horizontal scan lines of one feed to the image end point value. And an end point detecting means for outputting. 5. A comparator according to claim 4, wherein said pulse generating means generates a first active signal when said pointer value becomes equal by comparing with said image starting point value, and when said pointer value becomes equal by comparing with said image end point value. And a comparator for generating a second active signal, and an RS flip-flop for generating the adjusted vertical blanking signal set by the first active signal and reset by the second active signal. Automatic adjustment circuit. A vertical size automatic adjustment circuit of an image in a wide screen display apparatus which receives any one of image signals having different aspect ratios, wherein the level of the image signal is set for each horizontal scan line of the input image signal. Image discrimination means for discriminating the presence or absence of an image, and detecting an image start point and an image end point of every feed from the output of the image discriminating means, and determine the number of horizontal scan lines from the beginning of each feed to the image start point. Section detection means for outputting the number of horizontal scan lines to the end point of the image and outputting the number of horizontal scan lines to the end point of the image; A counter means for outputting the data; Pulse generating means for generating an adjusted vertical blanking signal which is compared with the image end point value sequentially from the time point at which the image of one feed ends to the time point at which the image of the next feed starts, and the detected image; A section verifying means for verifying that the section detection is normal when the start point value and the image end point value are compared between the respective feeds and continuously maintained for a predetermined number or more of the feeds; and when the section detection means is verified that the section detection is normal. Selecting means for selecting and outputting the adjusted vertical blanking signal, and if it is verified to be abnormal, selecting means for selecting and outputting a vertical blanking signal according to a vertical synchronization signal of the input video signal, and blanking the signal output from the selecting means. Vertical deflection by adjusting the vertical retrace period to correspond to the interval Vertical size automatic adjustment circuit comprising a direct deflection means. 7. The vertical size automatic adjustment circuit according to claim 6, wherein the threshold level is set to a pedestal level of the input video signal. 8. The apparatus according to claim 6 or 7, wherein the video discrimination means is a constant sampling interval for each horizontal scan line of the input video signal. The comparison means for comparing the level of the video signal with the threshold level, A counter for generating a signal indicating that the image is a horizontal scanning line only when the number of sampling sections determined that the level of the video signal is greater than the threshold level is counted for each horizontal scanning line and becomes a set value. Vertical size automatic adjustment circuit, characterized in that. The method of claim 8, wherein the section detecting means counts the number of consecutive horizontal scan lines determined to be the absence of the image from the start of every feed until the image appears, and outputs a count completion value as the image starting point value. A start point detecting means and the number of continuous horizontal scan lines determined to be absent from the image are counted from the beginning to the end of the second field and the count completion value is subtracted from the number of horizontal scan lines of one feed to the image end point value. And an end point detecting means for outputting. 10. A comparator according to claim 9, wherein said pulse generating means generates a first active signal when said pointer value becomes equal by comparing with said image starting point value, and when said pointer value becomes equal by comparing with said image end point value. And a comparator for generating a second active signal, and an RS flip-flop for generating the adjusted vertical blanking signal set by the first active signal and reset by the second active signal. Automatic adjustment circuit. A vertical size automatic adjustment circuit of an image in a wide screen display apparatus which receives any one of image signals having different aspect ratios, wherein the level of the image signal is set for each horizontal scan line of the input image signal. Image discrimination means for discriminating the presence or absence of an image, and detecting an image start point and an image end point of every feed from the output of the image discriminating means, and determine the number of horizontal scan lines from the beginning of each feed to the image start point. Section detection means for outputting the number of horizontal scan lines to the end point of the image as an image end point value, and a value counted by counting the number of horizontal scan lines from the start to the end of the macro shield as a pointer value indicating the progress of horizontal scanning. A counter means for outputting the pointer value and the pointer value; A pulse generating means for generating an adjusted vertical blanking signal having a blanking period from when the image of one feed ends to the time when the image of the next feed starts, in comparison with the phase end value, and the detected image; A section verifying means for verifying that the section detection is normal when the start point value and the end point value of the image are compared between the respective feeds and continuously maintained for a predetermined number or more of the feeds, and the continuous discriminated image is determined by the image discriminating means. Image verification means for counting the number of horizontal scan lines for each of the fields and comparing the count completion value with a predetermined reference value to verify that the image is a valid image; and the section verification means and the image verification unit in the section verification means and image verification unit. If all of the detections are verified to be normal, the adjusted vertical blanking signal If it is selected and outputted and verified to be abnormal, the selection means for selecting and outputting a vertical blanking signal according to the vertical synchronization signal of the input video signal, and the vertical retrace period corresponding to the blanking period of the signal output from the selection means. Vertical size automatic adjustment circuit comprising a vertical deflection means for adjusting the vertical deflection. 12. The vertical scale automatic adjustment circuit of claim 11, wherein the threshold level is set to a pedestal level of the input video signal. 13. The apparatus according to claim 11 or 12, wherein the video discriminating means comprises: comparing means for comparing the level of the video signal with the threshold level for every horizontal sampling line for each horizontal scanning line of the input video signal, and in the comparing means. And a counter for generating a signal indicating that the image is a horizontal scanning line only when the number of sampling sections for which the level of the image signal is determined to be greater than the threshold level is counted for each horizontal scanning line and becomes a set value. Vertical size automatic adjustment circuit. The method according to claim 13, wherein the section detecting means counts the number of continuous horizontal scan lines that are determined to be absent from the image until the image is displayed from the beginning of every feed, and outputs a count completion value as the image starting point value. A start point detecting means and the number of continuous horizontal scan lines determined to be absent from the image are counted from the beginning to the end of the second field and the count completion value is subtracted from the number of horizontal scan lines of one feed to the image end point value. And an end point detecting means for outputting. 15. The apparatus according to claim 14, wherein the pulse generating means generates a first active signal when the pointer value is equal to the image starting point value, and generates the first active signal when comparing the pointer value with the image ending point value. A comparator for generating a second active signal, and an RS flip-flop for generating the vertical blanking signal to be adjusted by being reset by the first active signal and reset by the second active signal. Adjustment circuit.