KR0172412B1 - Method for testing semiconductor memory device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

A test technique for semiconductor memory devices.

2. The technical problem to be solved by the invention

By failing early screens for defective wafers at the wafer level, semiconductor devices and test circuits can be used to increase yields and reduce test and assembly costs.

3. Summary of Solution to Invention

A semiconductor memory device having a memory cell array having a plurality of memory cells capable of writing and reading data, bit lines connected to the memory cells, and precharge transistors connected to the bit lines. A write operation when testing memory cells performs a write operation after turning off the precharge transistors, and a write operation in a package step turns on the precharge transistors to precharge the bit lines and then write them. And control means for generating a precharge control signal for performing the operation.

4. Important uses of the invention

It is suitably used for semiconductor memory devices.

Description

Test Method of Semiconductor Memory Device

1 is a schematic circuit diagram of a static ram constructed in accordance with the prior art.

2 is a timing diagram showing the timing relationship of various control signals used in FIG.

3 is a diagram showing a memory array of a general static RAM.

4 is a schematic circuit diagram of a static ram constructed in accordance with the present invention.

5 is a timing diagram showing a timing relationship of various control signals used in FIG.

TECHNICAL FIELD The present invention relates to semiconductor memory devices, and more particularly, to a test technique for testing memory chips of a semiconductor memory device.

In the semiconductor memory device, the post-inspection process from the wafer level to the package generally proceeds from replacing the failed pins with spares as a result of the pre-laser, which is a wafer level test. After assembling the package, check the operation with pre-burn first, and then stress test the chip to check the operation again after the burn-in test process to process defective short fail. Proceed. In the above-mentioned post inspection process, repair and repair of the chips that are failed during the assembly process or the burn-in process by pre-laser can be used to improve the yield. Unnecessary test and cooking costs can be reduced.

The semiconductor memory device may be classified into a write operation for inputting data from an external signal and a read operation mode for outputting the data of the pin to an external device. Also, static RAM (SRAM), which is generally a random access memory (RAM), includes a flip-flop structure of two cross-connected inverters. This structure of the static ram was filed in US Pat. A SCHMITT TRIGGER SENSE AMPLIFIER

FIG. 1 is a view schematically showing a structure of a static RAM according to the related art, and FIG. 2 is a timing diagram showing a writing operation of the static RAM shown in FIG.

Referring to FIG. 1, the memory 쎌 MC1-1 includes a high resistance load element R1, R2, an en-channel driving MOS transistor Q3, Q4, and an en-channel pass MOS transistor Q1, Q2. do.

One end of the high resistance load elements R1 and R2 is supplied with a power supply voltage and the other end thereof is connected to the drain terminals of the transistors Q3 and Q4. The transistor Q3 and Q4 source terminals are connected to a ground voltage. The gate terminal of the transistor Q3 is commonly connected to the node N2 which is the junction of the high resistive element R2 and the transistor Q4. The gate terminal of the transistor Q4 is commonly connected to the node N1 which is the junction of the high resistive element R1 and the transistor Q3. The current path of MOS transistor Q1 is connected between bit line B / L0 and the node N1, and the gate is connected to word line WL1. The current path of the transistor Q2 is a bit line Is connected between the node and the node N2, and a gate is connected to the word line W / L1. The nodes N1 and N2 have complementary data, and when the transistors Q1 and Q2 are turned on, the complementary data is the bit line B / L0, and Is delivered to. Such a memory shock is called a 4-transistor static memory shock. Each of the bit line pairs B / L1 includes a string consisting of the memory cells MC1-1 to MC1-j. , ..., B / L1, An array of memory chips connected between them is shown. The memory chips may be comprised of 8 to 32 and more memory chips.

The precharge transistors P1 and P2 of the precharge transistors P1 and P2 connected to the bit line B / L of the selected one of the memory cells are turned off during the write operation, but the other precharge transistor P1 is always on. . This helps to speed up the operation speed in the read operation after the write operation. However, such a structure has no problem in general reading and writing, but there is a problem in applying a test pattern for an initial defective screen.

The test pattern used to screen the defects of the pass transistors Q1 and Q2 is generally called a disturb pattern. However, a conventional structure does not provide effective disturb.

This disturb can be performed by writing the logical data 1 or 0 in a row stripe as shown in the memory array of FIG. 3, and then selecting only the even word lines W / L to correspond to the odd word lines W / L. A node (i.e., a "node node CN") to which the drain node of the pass transistors Q1 and Q2 which are written is connected to the word line WL (hereinafter referred to as the "node node CN"), and the bit lines B / L; By inverting the phases between them, the effect of stressing the fax transistors Q1 and Q2 is obtained, and a fault with the defective pass transistors Q1 and Q2 is failed. The most effective method of the disturb pattern is a method of testing with the maximum possible phase difference between the n-node CN and the bit line B / L.

However, as shown in FIG. 2, the selected bit line B / L0, Even when the phase of is written to the external data, the precharge transistor P1, which is always on, does not become a complete ground level phase, and the rest of B / Li, In addition to the external input, the phase of the bit line pairs B / L, Precharged to the power supply voltage, the pass transistors Q1 and Q2 due to the above-mentioned disturbance pattern have almost no stress effect and thus fail to be an effective fail screen. Therefore, if a failure occurs during the post inspection process, yield decreases and unnecessary test cost increases. Can be induced directly.

Accordingly, an object of the present invention is to provide a semiconductor memory device and a test method capable of increasing the efficiency of wafer-level testing.

Another object of the present invention is to provide a semiconductor memory device and a test method which can increase the yield.

It is still another object of the present invention to provide a semiconductor memory device and a test method which can reduce costs by early detection of a failing memory chip.

According to the technical idea of the present invention for achieving the above object, a memory array having a plurality of memory pins capable of writing and reading data, a bit line connected to the memory pins, A semiconductor memory device having connected precharge transistors, the write operation when testing the memory cells performs a write operation after turning off the precharge transistors, and a write operation in a package step includes the precharge. And control means for generating a precharge control signal for performing a write operation after precharging the bit lines by turning on azi transistors.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the drawings represent like reference numerals wherever possible.

4 is a schematic circuit diagram for explaining a state mode of a static RAM constructed in accordance with the present invention.

The memory chip array shown in FIG. 4 is the same as the circuit shown in FIG. The control circuit configured to control the was changed. The modified control circuit controls the NAND gate G3 receiving the write enable signal WE and the word line control signal PWL, the NAND gate G4 receiving the output signal of the NAND gate G3, and the precharge control signals φ PRE and φ PRES. The external precharge control signal XPC (hereinafter referred to as a control signal) generated for this purpose is composed of circuits which delay a predetermined time through the inverters G5 to G8. The precharge control signal? PRE output through the NAND gate G4 is a signal for controlling the gates of the precharge transistors P2 and is turned on or off by the signals WE, PWL, and XPC, and is output from the inverter G8. The precharge control signal? PRES, which is a signal, is always on during normal read and write operations. In the state mode, that is, the precharge control signals? PRE and? PRES are in the high level regardless of the external signal according to the signal XPC at the high level, and thus the operation in the desired mode has no effect on the address decoder, the clock signal, or the like. Can be done.

5 is a timing diagram illustrating a timing relationship of various signals used in FIG. 4.

4 and 5, when the signal XPC becomes high level, the precharge control signals φPRE and φPRES become high level so that the entire precharge transistor P1, P2 is turned off, and the bit line B / L, The level of is determined. For example, when repeating the operation of writing 0,1 data in the word line W / L direction and then writing a corresponding number of even word line W / L during the disassembly test as shown in FIG. The voltage phase of the unused bit line B / L is not taken to the full ground level by the precharge circuit, reducing the possibility that one data of 연결된 connected to an unselected odd number of odd lines is lost by a bad pass transistor. That is, it does not become an initial bad screen.

In FIG. 4 of the present invention, a high-level signal is applied to the XPC pad during the disturb test so that φ PRE is disconnected. Therefore, 1 data of the pin connected to the unselected odd word line W / L may cause the pass transistor of the corresponding pin to be bad. This is a good condition where leakage occurs (the bit line is at ground level), which facilitates an initial bad screen.

Although the present invention has been limited to static RAM, they may also be implemented on DRAM (DRAM) within the scope of obtaining the same effect.

The function of determining whether the fail may cause leakage of the pass transistor in a long cycle time rather than a short cycle time is more effective.

As described above, the present invention has the effect of not only increasing the yield but also reducing the test and assembly costs by causing the initial screen to fail on the defective wafer at the wafer level.

Although the present invention described above is limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the present invention.

Claims (3)

A semiconductor memory device having a memory cell array having a plurality of memory cells capable of writing and reading data, bit lines connected to the memory cells, and precharge transistors connected to the betaine. A write operation when testing memory cells performs a write operation after turning off the precharge transistors, and a write operation in a package step turns on the precharge transistors to precharge the bit lines and then write them. And control means for generating a precharge control signal for performing an operation. The method of claim 1, wherein the control unit delays a predetermined time delay between the first NAND gate receiving the write enable signal and the word line control signal, and the external precharge control signal generated to control the precharge control signal. And a second NAND gate receiving the inverted control signal inverted later, an output signal of the first NAND gate, and an inverter inverting the inverted control signal. A wafer level test of a semiconductor memory device having a memory array having a plurality of memory chips capable of writing and reading data, bit lines connected to the memory chips, and precharge transistors connected to the bit lines. A method: A write operation when testing the memory chips performs a write operation after turning off the precharge transistors, and a write operation in a package step turns on the precharge transistors to free the bit lines. A wafer level test method that performs a write operation after charging.