KR0172363B1 - Semiconductor memory device having multi-bank structure - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor memory device.

2. Technical problem to be solved by the invention

The present invention provides a low decoder for efficient time delay and fast operation of word lines and precharge in a multi-bank memory device.

3. Summary of Solution to Invention

The present invention provides a semiconductor memory device, comprising: a first device connected to an external system for selecting respective banks and controlling generation of a low address sampling control signal in response to the system clock, a low address strobe signal, and a bank select address signal; A low strobe buffer for outputting a control signal and a row generating the low address sampling control signal after a predetermined time to control activation and precharge of a word line in response to the first control signal from the low strobe buffer An address sampling control signal generation circuit and a low decoder for latching an output signal of which the low address is predecoded as an output signal of the low address sampling control circuit are provided.

4. Important uses of the invention

The present invention is suitably used for a semiconductor memory device.

Description

Semiconductor Memory Device with Multi-Bank Structure

Figure 1 is a block diagram showing a multi-bank configuration according to the prior art.

2 is a control path diagram showing a path of multi-bank control of a multi-bank structure according to the present invention.

3 is a block diagram of bank control signal generation circuits of a multi-bank structure according to the present invention.

4 is a detailed circuit diagram of the low address buffer of FIG.

5 is a detailed circuit diagram of the low straw buffer of FIG.

6 is a specific circuit diagram of the low address sampling control signal generation circuit of FIG.

7 is a specific circuit diagram of the pulse generation circuit of FIG.

8 is a detailed circuit diagram of the low decoder of FIG.

9 is a specific circuit diagram of the delay circuit of FIG.

10 is a detailed circuit diagram of the block selection logic circuit of FIG.

11 is a detailed circuit diagram of the PXI generation circuit of FIG.

12 is an operation timing diagram according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to word line activation and bit line precharge of a memory device having a multi-bank structure using a low address sampling method.

Recently, Dynamic RAM (Dynamic Random Access Memory) has been changed from asynchronous to synchronous with the System Clock, and the number of internal banks has also increased to two banks (16Mega). banks), the number of banks is increasing to four banks in the case of 64-mega dynamic RAM and eight banks in the case of 256-mega synchronous dynamic RAM. As the number of banks of the dynamic RAM increases in the relationship between the central processing unit (CPU) and memory, the number of word lines that can be maintained in an active state increases, resulting in a cache miss. In the case of a miss, the page cache memory hit ratio of the dynamic RAM can be increased, so that data can be accessed quickly. However, in the conventional configuration as shown in FIG. 1, the output lines of the low address buffer must be increased in order to increase the number of banks because each bank must have the output lines of the low address buffer, the low predecoder, and the low predecoder output lines separately. The low predecoder and low predecoder output lines also need to increase with the number of banks. In addition, the conventional configuration has a configuration in which the banks are arranged sideways when the number of banks is increased, so that the increase in the chip size becomes very large, making it difficult to increase the number of banks.

1 is a block diagram showing a multi-bank configuration according to the prior art.

Referring to FIG. 1, the configuration includes four banks 0, 1, 2, and 3, each of which is composed of a memory cell array and a bit line sense amplifier, spread out side by side, Predecoders 3, 5, 7, and 9 exist in their respective banks 0, 1, 2, and 3, and there are separate outputs 11, 13, 15, and 17 of the low predecoder. Column decoders 50, 60, 70, and 80 also exist for each bank. Therefore, when the number of banks is increased, the problem of increasing the chip size is very large, and it is difficult to increase the number of banks. In addition, although not shown in the configuration of a stacked multi-bank in which the low-free decoder and the low-free decoder output lines are used in common, the low-address buffer, the low-free decoder, and the low-free decoder output lines are respectively shown in the bank group. Since they are shared, the previous clock of the external system in the sensing operation of the enable and disable of the word line of each bank and the sense amplifier of the bit line is performed. The activation operation by the Active command of the clock is disabled by the Precharge command of another bank given at the next clock. Accordingly, a problem arises in that a precharge operation is started before the word line is disabled or the bit line sense amplifier starts sensing before the word line is enabled.

Accordingly, an object of the present invention is to provide a low strobe buffer and a low address sampling circuit for controlling the effective time delay and operating time of word line activation and sensing of precharge and bit line sense amplifiers in a memory device having a multi-bank structure; To provide a low decoder.

It is another object of the present invention to control the effective time delay and the operation time of word line activation and precharge operation in a multi-bank structure memory device which shares a low predecoder and a low predecoder output line. A low address sampling control signal generation circuit is provided.

According to the technical idea of the present invention for achieving the above objects, the memory pre-array and the low predecoder and the low predecoder to decode a portion of the low address by the system clock and a memory array and memory A semiconductor memory device including a plurality of banks sharing an output line, the semiconductor memory device being connected to an external system to select respective banks in response to the system clock, a low address strobe signal and a bank select address signal, and a low address sampling control signal. A low strobe buffer for outputting a first control signal for controlling the generation of a signal; and the row after a predetermined time for controlling activation and precharge of a word line in response to the first control signal from the low strobe buffer. Generate the address sampling control signal. By sampling the output signal of the row address control signal generating circuit, and the row address sampling control circuit is characterized by having the row decoder to the row address latch signal for pre-decoding output.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the drawings represent like reference numerals wherever possible.

2 is a control path diagram showing a path of multi-bank control of a multi-structure of a stacked multi-bank structure according to the present invention. Referring to FIG. 2, n banks a1-an in the vertical direction share the low predecoder 30 and the low predecoder output line 5. Delay circuit 21-2n, which receives the block selection circuit 41-n1 under the control of the low address sampling control signals RADSABa1-RADSABan and the output signal BLSia1-BLSian of the block selection circuit, and outputs the signal RSPDa1-RSPDan by delaying the predetermined time. And a PXI driver that receives the output signals of the low predecoder, the low address sampling control signal, and the output signal of the delay circuit, and outputs a control signal PXIa1-PXIan to the word line driver 11-1n, and the low address sampling control signal. Low decoders 1-n receiving RADSBa1-RADSABan, the output signals of the signal RSPDa1-SRPDan, and the low predecoder 30 and outputting a word line enable driving signal WLEia1-WELian to the wordline driver 11-1n, and the low The word line input drive signal WLEia1-WLEian, which is an output signal of the address sampling circuit and the low decoder, is input to each word. It consists of a word line driver 11-1 n which generates the line drive signals WLi1-WLin. Therefore, whenever a row enable command is given for each bank, the low address sampling pulse RSPai (i) is generated by the low address sampling control signal RADSABai (i = 1-n) generated when the bank row is activated to activate the word line of the corresponding bank. = 1-n) occurs to latch the block selection address for block selection. In addition, the signal RSPai is delayed to generate the delay signal RSPDi so that a low address is latched to the PXI driver and the low decoder so that the signals PXIai and WLEai are logic high and the word line of the corresponding address is activated to logic high. In the present invention, unlike the conventional configuration in which the output lines of the low address buffer existed separately by the number of each bank, all banks share and use the same low address buffer output line. The low address buffer latches the row address by PRAR, a pulse generated by the low row buffer at every low activation.

3 is a configuration diagram of bank control signal generation circuits of a multi-bank structure according to the present invention. Referring to FIG. 3, a low address sampling control signal generation circuit 10-1 to 10-n for generating a low address sampling control signal RADSABa1-RADSABan by inputting the first control signal PRa1 and the low address sampling control signal RADSABa1. Pulse generator circuits 50-1 to 50-n, which generate pulses RSPa1-RSPan with a predetermined delay time as input to RADSA-Ban, and complementary low address strobe signal RAS and clock buffer from outside The low strobe buffer 100 generates the first control signal PRa1-PRan in response to the clock PCLK and the bank selection address signal BAi (i = 0-n) outputted through the control signal. The low address buffer 10, the block selection circuit 41-n1, the delay circuit 21-2n in FIG. 2 and the low strobe buffer 100 and the low address sampling control signal generating circuit 10-1 in FIG. -n, the pulse generating circuits 50-1 to 50-n show specific circuits in FIGS. 4 to 11 to be described later.

4 is a detailed circuit diagram of the low address buffer of FIG. Referring to FIG. 4, inverter 5 is composed of an inverter chain 3 consisting of two inverters receiving an address Ai from the system as an input signal and outputting a predetermined signal, and a clock PLCK buffered clock input from the system. A latch circuit comprising transmission gates 10 and 40 for switching and switching controlled by a clock PCLK and inverters 7 and 9 for outputting an output signal from the inverter chain 3 through the transmission gate 10 to latch the output signal; And a latch circuit comprising inverters 11 and 13 for latching a signal output through the transmission gate 40 and an external input signal, for example, PRAR, to control the signal as an inverted signal and a non-inverted signal through the inverter 17. The switching gates 20 and 30 for switching and the latching signals output through the transmission gates 20 are latched by the inverters 11 and 13. And a latch circuit composed of inverters 19 and 21, and inverters 25 and 27 for inverting the signals latched by the inverters 11 and 13 through the inverter 15 and outputting them through the transfer gate 30 to latch the output signals. And an inverter 23 for inverting the output signal from the latch circuit of the inverters 19 and 21 to output the low address RAi, and an inverting the output signal from the latch circuit of the inverters 25 and 27 to output the complementary low address RAiB. It consists of inverter 29. Since the logical operation can be easily understood by the above configuration, a description thereof will be omitted.

5 is a detailed circuit diagram of the low strobe buffer of FIG. Referring to FIG. 5, inverter 5 which inverts the external control signal PCLK outputted from the clock buffer as an input in response to the system clock CLK from the outside, and inverter chain 3 as the input of the complementary low address strobe signal RAS are input. NAND gates 10 and 20 inverted and logically multiplied with a predetermined delayed inverted signal through one input, an inverter 1 connected to an output terminal of the NAND gate 20 to invert an output signal, and an external power supply voltage Vcc terminal and ground An activation switch 80 connected to a voltage Vss terminal and an output terminal connected to the input terminal of the NAND gate 10 as one input, connected to an external power supply voltage Vcc terminal when the word line is activated, and connected to a ground voltage Vss terminal at the time of precharging and switching. Is connected to the external power supply voltage Vcc terminal and the ground voltage Vss terminal, and the output terminal is one input to the input terminal of the NAND gate 20. The precharge switch 90 and the bank selection address signal BAi (i = 0-n) connected to the external power supply voltage Vcc terminal of the word line and connected to the ground voltage Vss terminal of the precharge are connected as inputs. The NAND gate 30 which sends an output signal to the NAND gate 10 and the NAND gate 20 through the inverter chain 11 and is connected to an external power supply voltage Vcc terminal and a ground voltage Vss terminal, thereby outputting the output signal of the NAND gate 10; PMOS transistors 40, 50, and NMOS transistors 60, 70 each having an output signal of the inverter 5, an output signal of the NAND gate 20, and a clock PCLK as gate inputs, a drain of the PMOS transistor 50, and the NMOS Inverter chain 7 which latches the signal output to connection node n1 between the drain of transistor 60 and the output of inverter chain 7 are inverted NAND gate 100 having three inputs including an inverter 9 for outputting the first control signal PRai, an output signal through the inverter chain 3 and an external power voltage VCC through the activation switch 80 when activated, and the clock PCLK. The inverter PR 21 outputs a signal delayed and inverted in response to the output signal from the NAND gate 100, and the output signal of the NAND gate 100 and the output signal of the inverter chain 21 are inverted and logic-integrated using two inputs to generate the signal PRAR. It consists of a Noah Gate 200 that outputs. The PRAR is a pulse generated by automatic pulse logic every time a bank row is activated, and is different from the conventional logic high state. While the pulse PRAR is logic high, the low address outputs RAi, RAiB are set and latched while being logic low.

In this case, the first control signal PRai becomes a logic high state when the word line is activated, and becomes a logic low when precharged.

FIG. 6 is a specific circuit diagram of the low address sampling control signal generation circuit of FIG. Referring to FIG. 6, each bank to be activated is determined to generate the first control signal PRai, which passes through the inverters 3 and 5, and is a predetermined delay time to become the input of the NOA gate 50. In addition, the output signal passing through the inverters 3 and 5 passes through the inverter chain 7 composed of an even number of inverters and is inputted to the other input terminal of the NOA gate 50 after a predetermined time delay. The output signal of the NOA gate 50 inverted and logic is delayed for a predetermined time through the inverter chain 13 to output the low address sampling control signal RADSABai.

In operation, when the word line is activated, the first control signal PRai becomes a logic high state, and in response to the signal, the first control signal PRai passes through inverters 3 and 5 and outputs an output signal of the same logic state after a predetermined time. Therefore, the output signal of the logic high is the one input of the NOR gate 50, the output signal of the logic high is the one input of the NOA gate 50, and the output signal of the logic high is delayed by the inverter chain 7 for a predetermined time. In other words, the logic high signal is outputted to the other input of the NOR gate 50 to invert and logically generate a logic low pulse. The logic low state signal is delayed for a predetermined time to generate the low address sampling control signal RADSABai in the logic low state. On the other hand, when precharging a word line, the first control signal is input to a logic low. Therefore, through the above-described process, the low address sampling control signal RADASBai is output in a logic high state.

7 is a specific circuit diagram of the pulse generation arc of FIG. Referring to FIG. 7, the low address sampling control signal RADSABai generated in the low address sampling control signal generation circuit in FIG. 6 is one input, and the signal is delayed and inverted through the inverter chain 3 to another input. The pulse generation circuit is configured with an inverter chain 5 which delays a predetermined time in response to the NOA gate 100 and the output signal of the NOA gate 100. In operation, when the low address sampling control signal RADSABai activates a word line, a logic low is input, and a signal of a logic high state, which is a short pulse after a predetermined time delay, is output through the pulse generating circuit. In addition, latching the block selection address and latching the corresponding low address in the low decoder and the PXI driver to generate RSPDai, a delayed pulse of FIG. 8 to be described later to activate the signal PXIai and the word line enable signal WLEiai to logic high. It is a pulse generator circuit.

8 is a detailed circuit diagram of the low decoder of FIG. An inverter 7 for inverting the low address sampling control signal RADSABai as an input; a PMOS transistor driven with an output signal of the inverter 7 as a gate input, a source connected to an external power supply voltage Vcc terminal, and a drain connected to a connection node n2; 10 and both sides are connected to the connection node n2 and the ground voltage Vss terminal, and the drain and the source are connected to each other in series, and the output signals of the inverter chain 5 between the low addresses DRAij, DRAk1, DRAmn and outputted by the low predecoder It consists of a low decoder composed of NMOS transistors 20, 30, 40 and 50 serving as the gate input. In operation, when the low addresses DRAij, DRAk1, and DRAmn, which are outputs of the low predecoder, are in a logic high state, the EnMOS transistors 20, 30, 40, and 50 are turned on, and a signal of a logic high state is generated by the inverter 7. The input node n2 is turned off by being input to the gate of the PMOS transistor 10 and the connection node n2 is in a logic low state. Accordingly, the logic low state signal of the connection node n2 is latched by the inverter chain 9 to output the word line enable control signal WLEiai as a signal inverted with a predetermined time delay through the inverter chain 11. On the other hand, when the word line is precharged, the low address sampling control signal RADSABai is output in a logic high state, and the above-described pulse generation circuit is operated by the signal to input a logic low state signal to the gate of the NMOS transistor 50. The NMOS transistor 5 is turned off, while the logic low state signal inverted by the inverter 7 is input to the gate of the PMOS transistor 10 to turn on the PMOS transistor 10, so that the connection node n2 is an external power source. The voltage Vcc becomes a logic high state which is a voltage obtained by subtracting the threshold voltage of the PMOS transistor 10. Subsequently, the logic high state signal is latched through the inverter chain 9 and the latched signal is input to output the word line enable control signal WLEiai of the logic low state which is delayed for a predetermined time and inverted through the inverter chain 11. .

9 is a specific circuit diagram of the delay circuit of FIG. Referring to FIG. 9, the inverter chain 10 which outputs the output signal RSPai of the pulse generation circuit of FIG. 7 with a predetermined time delay and the block selection signal BLSi and the delayed signal in the inverter chain 10 are inverted as two inputs. The NAND gate 20 is multiplied by an AND, and the inverter 3 is connected to an output terminal of the NAND gate and outputs an inverted signal, that is, RSPDai. In operation, the output signal RSPai of the pulse generating circuit is input to the NAND gate 20 after a predetermined time while the block selection signal BLSi is input to generate the RSPAai having a predetermined short pulse type.

FIG. 10 is a detailed circuit diagram of the block selection logic circuit of FIG. Referring to FIG. 10, an inverter 3 which outputs an inverted signal in response to a low address sampling control signal RADSABai, an output terminal of the inverter 3 and one input terminal are connected, and an output signal of the inverter 3 and an output of the low predecoder. A NAND gate 10 inverted and logically multiplied with a low address DRAij, an output terminal and an input terminal of the NAND gate 10 are connected, and are controlled by the signal RSPai to serve as a switch, and an output terminal of the transmission gate 20 A latch circuit 30 consisting of two inverters connected to an input terminal to latch the output signal of the NAND gate 10, and an inverter outputting the block selection signal BLSi after the output terminal and the input terminal of the latch circuit 30 have a predetermined delay time. It consists of chain 7. I'll skip this because it's easy to see.

FIG. 11 is a detailed circuit diagram of the PXI generation circuit of FIG. Referring to FIG. 11, the inverter 7 which inverts the low address sampling control signal RADSABai as an input, the output signal of the inverter 7 as a gate input, the source is connected to the external power supply voltage Vcc terminal, and the drain is connected to the connection node n2. The low-address DRA01 outputted by the low predecoder and the delay shown in FIG. 9 are connected to the driven PMOS transistor 10 and both sides thereof are connected to the connection node n2 and the ground voltage Vss terminal, and the drain and the source are connected to each other in series. It consists of a low decoder composed of NMOS transistors 20 and 30 whose gate input is RSPDai, which is an output signal of the circuit. In operation, when the low address DRA01, which is the output of the low predecoder, is in a logic high state, the NMOS transistors 20 and 30 are turned on, while a signal in a logic high state is input to the gate of the PMOS transistor 10 by the inverter 7. Turn off to connect node n2 to a logic low state. Accordingly, the logic low signal of the connection node n2 is latched by the inverter chain 9 to output the signal PXIai as a signal inverted by a predetermined time delay through the inverter chain 11.

FIG. 12 is a timing diagram of the row activation and precharge of the banks of FIG. 3 according to the present invention. Referring to FIG. 12, the clock PCLK is an internal clock which is an output of the clock buffer. When the low activation command of the bank a1 is given to the clock indicated by the reference numeral 1, the first control signal PRa1 and the signal PRAR are generated by the clock PCLK in the low strobe buffer, and the signal PRAR latches the corresponding low address. When the signal PRa1 makes the low address sampling signal RSPa1 become a logic low, the low address sampling signal RSPa1 is generated by falling to the logic low of the low address sampling control signal RADSABa1, and the word line enable is performed by the delayed signal RSPDa1. The signal WLEia1 and the signal PXIa1 are activated at a logic high so that the word line of the corresponding row is activated at a logic high. In addition, when the bank a1 indicated by reference numeral 2 becomes precharged, the low address sampling control signal RADSABa1 becomes logic high, and the low decoder and the inside of the PXI driver are precharged to logic high, so that the word line enable signal WLEia1 and the signal are performed. PXIa1 is disabled to logic low.

As described above, according to the present invention, in a multi-bank structure memory device sharing a low predecoder and a low predecoder output line, the effective time delay and the operation time of the activation of the word line and the precharge operation are controlled, and the speed is increased. It can be effective.

Although the present invention described above is limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (5)

In a semiconductor memory device comprising a memory cell array consisting of a memory cell and a matrix of the memory cells, a low predecoder for decoding a part of a low address by a system clock, and a plurality of banks sharing an output line of the low predecoder. A low strobe connected to an external system to select respective banks in response to the system clock, the low address strobe signal, and the bank select address signal and to output a first control signal for controlling generation of a low address sampling control signal; A low address sampling control signal generation circuit for generating the low address sampling control signal after a predetermined time to control activation and precharge of a word line in response to a bu buffer and a first control signal from the low strobe buffer; , The lower address The semiconductor memory device of the predecoded row address information to the output signal of the sampling control circuit characterized in that it includes a row decoder for latching. The semiconductor memory device according to claim 1, wherein the low address sampling control signal generation circuit is independently provided for each of the plurality of banks. 2. The logic circuit of claim 1, wherein the low strobe buffer is configured to output the first control signal to logic high when the word line is activated, and the first control signal to logic low when precharging the word line. And a precharge switch configured to adjust the output of the semiconductor memory device. The semiconductor device of claim 1, wherein the low decoder is operated when the corresponding bank is activated to maintain the low address information and the word line in an enabled state, and to disable the word line when precharging the corresponding bank. Memory device. The semiconductor memory device of claim 1, wherein the low decoder generates a pulse having a predetermined size when the bank is activated to input a low address of the bank during an enable state of the pulse.