KR0172303B1 - Command language sorter - Google Patents

Abstract

The present invention provides an instruction aligner for correctly providing an instruction stored in an external prefetch queue to a decoding unit according to a plurality of control signals generated in an external prefetch unit, wherein the plurality of first control signals from the prefetch unit selection means (21 to 25) for selecting and outputting instructions stored in the prefetch queue according to (sel1, sel2, sel0); And rotating means 26 for rotating the instructions selected by the selection means in accordance with the second control signal Bsht_amt [4: 0] from the prefetch unit and providing them to the decoding unit. The instruction aligner does not require any interface between the prefetch queue and the cache block, and puts all instruction alignment functions between the prefetch queue and the decoder to facilitate design improvements.

Description

Instruction sorter

1 is a block diagram showing peripheral function blocks associated with an aligner according to the present invention.

2 is a structural diagram of an instruction aligner according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

21 to 25 multiplexer 26 byte rotator

TECHNICAL FIELD The present invention relates to an instruction aligner, and more particularly, to an instruction aligner installed between a cache unit and a decoding unit in the design of a microprocessor such that the correct instruction is input to the decoding unit in time.

In general, in the case of CICS (Complex Instruction Set Computer), the length of the instruction is not constant. In the microprocessor used for this CISC, the instruction may range from 1 byte in length to 15 bytes in length.

When reading instructions from the code cache into the prefetch unit, they are usually read in line size. However, if an instruction spans two consecutive lines, the prefetch unit must access the code cache twice to read two consecutive lines.

To eliminate this hassle, conventionally, a split line access is performed which simultaneously brings the upper half line of one line and the lower half line of the next line in one cycle.

However, using this method to read an instruction from the code cache will cause the instruction to be written to the prefetch queue without being aligned correctly. Therefore, the correct instruction can be sent to the decoding unit, which requires an aligner to correctly align the instruction.

SUMMARY OF THE INVENTION The present invention has been made in view of solving the above problems and in response to a need, and an object of the present invention is to provide an instruction aligner that allows a correct instruction to be provided to a decoding unit in time.

In order to achieve the above object, the present invention provides an instruction aligner for correctly providing an instruction stored in an external prefetch queue to a decoding unit according to a plurality of control signals generated in an external prefetch unit. Selecting means for selecting and outputting a command stored in the prefetch queue according to a plurality of first control signals of a plurality of first control signals; And rotating means for rotating the instructions selected by the selection means in accordance with the second control signal from the prefetch unit and providing them to the decoding unit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

For simplicity, we assume a line size of 32 bytes, the number of cache entries is 128, and the physical cache. It is assumed that the prefetch address is 32 bits and the lower 12 bits access the cache without address translation. The prefetch address can then be divided as follows.

Instructions read from the code cache into the prefetch unit are always loaded into the prefetch queue at the line size according to the prefetch address generated by the prefetch unit. At this time, in the split line access, the access is performed only when both the current line and the next line hit, and the miss processing routine is performed when one line is missed.

1 is a block diagram showing peripheral functional blocks associated with an aligner according to the present invention, in which 1 is a page unit, 2 is a bus unit, 3 is a code transmission lookaside buffer (TLB), 4 is a code cache, and 5 is x. A pairing check unit, 6 a y pairing check unit, 7 a prefetch unit, 8 a decoding unit, 9 a sorter, and 10 a prefetch queue.

The page unit 1 performs control on address translation, and when a TLB miss occurs, a request is made to the bus unit 2 for memory access to obtain information necessary for address translation from the main memory.

The code TLB 3 contains information necessary for address translation, and sends a physical address to the code cache 4 when the TLB hits.

The code cache 4 contains instructions sent to the prefetch queue, and then loads a line (32 byte) instruction into the prefetch queue when a cache access request comes from the prefetch unit.

There is also a pass (64 bits) that can be loaded directly into the prefetch queue from the bus unit 2 to reduce any interruption of instruction flow into the decoding unit upon cache miss.

The decoding unit 8 reads the instruction from the prefetch queue if necessary via the code cache sorter and decodes the instruction.

There are both passes from prefetch queue pair 0 (pair 0) and pair 1 to x pairing check unit 5 and y pairing check unit 6 to support dual pipelines. .

The pairing check units 5 and 6 determine whether or not pairing is possible and inform the prefetch unit 7.

The prefetch unit 7 fills the prefetch queue by generating a prefetch address so that the prefetch queue always has valid instructions, and controls the prefetch queue and sorter 9 so that the correct instructions go to the decoding unit 8. do.

In the prefetch queue, two 32-byte lines form a queue pair. Whenever a branch is expected by a jump instruction or the like, the queue pair is changed and loaded.

Therefore, when the decoding unit 8 reads an instruction, the instruction is accessed by accessing only a pair of queues until a branch is expected, and when the branch is expected, the instruction is accessed by accessing another pair of queues. Therefore, the path from both pairs of queues to the x pairing check unit 5 and the y pairing check unit 6 must be in the sorter.

2 is a structural diagram of an instruction aligner according to an embodiment of the present invention for supporting both split line access and non-splitting, in which sel0, sel1, sel2, and Bsht_amt [4: 0] are external (prefetch units). This is a control signal created in, which performs control to read the correct command from the decoder.

In the present embodiment, as shown in the drawing, a plurality of multiplexers 21 to 25 for selecting and outputting a command stored in a prefetch queue according to control signals sel0, sel1, and sel2 from a prefetch unit, and a prefetch unit And a byte rotator 26 for rotating the instructions selected by the multiplexers 21 to 25 and providing them to the decoding unit in accordance with the control signal Bsht_amt [4: 0].

The prefetch queues PFQ_00, PFQ_01, PFQ_10, and PFQ_11 are register type storage locations that receive 32-byte instructions from the code cache and store them until they are read into the decoding unit. In order to be able to load instructions from a foreign bus at the time of a cache miss, it must be possible to load an external bus size (or 64-bit load if the external bus size is 64 bits).

The valid bit indicates that the existence of a bit is valid every 8 bytes and is used to check whether a valid instruction exists in the queue when reading the instruction into the decoding unit.

The multiplexer 16_2x1 is a multiplexer which selects and outputs one 16 byte from two 16-byte inputs by the selection signals sel0 and sel1. The multiplexer 32_2 x 1 is a multiplexer which selects one of 32 bytes of two 32-byte inputs and outputs it to an output by the selection signal sel2. If the selection signal is 0, an input corresponding to 0 of the multiplexer is selected, and if 1, an input corresponding to 1 is selected.

The byte rotator rotates the 32-byte input by the control signal Bsht_amt [4: 0] and sends it to the output. The size of the byte_rotator output is determined according to the length of the instruction that can be decoded in the decoder unit at one time.

For example, if the following 32-byte input is represented in hexadecimal and the value of the control signal (Bsht_amt [4: 0]) is 4, the lowest 4 bytes of the input are truncated and 12 bytes are output from there. do.

32 byte input:

00ffeeddccbbaa998877665544332211112233445566778899aabbccddeeff00

12 bytes output: 112233445566778899aabbcc

The selection signals sel0, sel1, sel2 and the control signals Bsht_amt [4: 0] are the size of the instruction received from the decoding unit in the prefetch unit, the valid bits of the prefetch queue (16) to read the appropriate instruction into the decoding unit. Bit), whether to make a branch prediction hit, or the like. In the case of not supporting the split line access, it is not necessary to multiplex by 16 bytes by the selection signals sel0 and sel1, and it is sufficient to multiplex 32 bytes by one control signal. The selection logic is configured with four 16-byte multiplexers to support split line access.

Assuming that instructions are supplied continuously from the code cache to the prefetch queue, the operation of the sorter having the above configuration is as follows.

Prefetch addresses are generated by the prefetch unit to read instructions from the code cache into the prefetch queue, usually when the address is incremented continuously and branch recovery is needed, for example when branch recovery is needed. Access the code cache with the new address. When loading into the prefetch queue, four cases can occur due to bits 4 and 5 of the prefetch address. Bit 4 indicates whether split line access or not, and bit 5 determines whether to load to the upper prefetch queue PFQ_00 or PFQ_10 or to the lower prefetch queue PFQ_01 or PFQ_11 in the figure.

According to bit 4, the following two cases will be described. If a branch is expected, nothing is wrong except that only the cue pair is changed, so only the cue pair 0 (PFQ_00, PFQ_01) is used.

First, the case of nonsplit line access (prefetch address [5: 4] = 00 or 10) will be described.

In this case, if prefetch_address [4] = 0, only one line is accessed without access to two lines. If it is 0 according to prefetch_address [5], it is loaded into PFQ_00 and prefetch_address [5] is 1 If so, it is loaded into PFQ_01.

If the first prefetch address [5] is 0, when accessing the next consecutive line, the prefetch address [5] is increased by one to 1, so that PFQ_00 and PFQ_01 are loaded alternately. When the prefetch unit loads the prefetch queue, it puts a valid bit in the prefetch queue so that it can detect that the prefetch queue is empty.

There are 4 bits in PFQ_00 and 4 bits in PFQ_01 because valid bits must be placed every 8 bytes to support 64-bit loads from the bus unit.

The control signal sel0 is a selection signal of the multiplexer MUX that selects one of the upper 16 bits 31-16 of PFQ_00 or the upper 16 bits of PFQ_01, and the control signal sel1 is the lower 16 bytes (15- 15) of PFQ_00. 0) or PFQ_01 The lower 16 bytes select signal of the multiplexer (MUX).

The control signal sel2 is generated when the cue pair is changed by branch prediction or branch recovery.

The control signal Bsft_amt [4: 0] is a control signal for rotating an input of 32 bytes from a minimum of 1 byte to a maximum of 31 bytes. This signal is needed to support splitline access and variable length instruction prefetch.

In this way, the code cache aligner and the control signals sel0, sel1, sel2, and Bsfr_amt [4: 0] can be used to send a variable-length instruction that spans two lines to the decoding unit at once.

If the first prefetch address bit 5 is zero, the instruction is loaded for the first time in PFQ_00, and the fetch starts from PFQ_00. At this time, for the prefetch address [4: 0], the position of the byte to be received at the beginning of PFQ_00 is determined. At this time, the values of the control signals sel0, sel1, and sel2 are all zero.

Since prefetch address [4] is 0, fetching starts from one byte of the lower 16 bytes of PFQ_00, and then moves from the lower half line (lower 16 bytes) to the upper half line. Change sel1) to 1 to select the lower half line of PFQ_01. Then, when the upper half line of PFQ_00 is read again and the lower half line of PFQ_01 is passed, the control signal sel0 is changed to 1 to select the upper half line of PFQ_01.

In this way, the instruction continues to read until the branch pair is changed.

On the other hand, the case of the split line access (prefetch_address [5: 0] = 01 or 11) is as follows.

In this case, prefetch_address [4] = 1. One line and the next line are accessed over two lines, and if it is 0 according to prefetch_address [5], it is loaded into PFQ_00 and prefetch_address [5]. If it is 1, it is loaded in PFQ_01.

At this time, when the prefetch address [5] is 0, the upper half line of the current address is loaded in the upper half line (31-16 bytes) of PFQ_00, and the lower half line of the next line is loaded in the lower half line of PFQ_00. Also, if the first prefetch address [5] is 0, when the next successive line is accessed, the prefetch address [5] is increased by one to 1, so that PFQ_00 and PFQ_01 are alternately loaded.

If the first prefetch address bit 5 is zero, the instruction is loaded for the first time in PFQ_00. At this time, the position of the byte to be fetched at the beginning of PFQ_00 is determined by the prefetch address [4: 0]. At this time, the values of the control signals sel0, sel1, and sel2 are all zero. Since prefetch address [4] is 1, the first instruction to fetch is located on the upper half line of PFQ_00.

When the fetch starts from one byte of the 16 bytes of PFQ_00, and then goes from the upper half line (16 bytes of 31-16) of PFQ_00 to the lower half line of PFQ_00, the selection signal sel0 selects the upper half line of PFQ_01. Then, after reading the lower half line of PFQ_00 again and changing to the upper half line of PFQ_01, the control signal sel1 is changed to 1 to select the lower half line of PFQ_01. In this way, the instruction continues to read until the branch pair is changed.

For reference, the aligner may be used in any computing system that executes instructions such as a microprocessor as well as a microprocessor.

The present invention as described above does not require any interface between the prefetch queue and the cache block, and all instruction alignment functions are placed between the prefetch queue and the decoder, so that the design improvement is easy.

Claims (4)

An instruction aligner for correctly providing an instruction stored in an external prefetch queue to a decoding unit according to a plurality of control signals generated in an external prefetch unit, wherein the instruction aligner is configured according to the plurality of first control signals from the prefetch unit. Selecting means for selecting and outputting a command stored in the prefetch queue; And rotating means for rotating the instruction selected by the selection means according to the second control signal from the prefetch unit and providing the instruction to the decoding unit. 2. The apparatus of claim 1, wherein the selecting means comprises: a plurality of first multiplexers for selecting and outputting a command stored in each of the prefetch queues using any one of the plurality of first control signals as a selection signal; And a second multiplexer which selects a predetermined output among the outputs of the first multiplexer and selects one of the plurality of first control signals as a selection signal and supplies the selected output to the input of the rotating means. group. 3. The instruction aligner of claim 1 or 2, wherein the rotating means determines the size of its output in accordance with the length of the instruction that can be decoded at one time in the decoding unit. The instruction aligner of claim 3, wherein the plurality of first and second control signals are generated according to a size of an instruction from the decoding unit, a valid bit of the prefetch queue, and a branch predicate hit. .