KR0171774B1 - System bus analysis apparatus of computer system - Google Patents

Abstract

The present invention relates to a system bus analyzer of a computer system, comprising: a search memory (27) for storing a signal of a system bus according to predetermined search position information and size information; A processor 21 for outputting a signal for a trigger condition, reading and processing data of a search memory and providing the signal to a user; A mask register 22 for storing the money care trigger condition input from the processor; A data register 23 for storing a care trigger condition input from the processor; A command register 24 for storing the search position information and the storage size information input from the processor; A comparator 25 for comparing the trigger condition stored in the mask register and the data register with signal information of a system bus for each bus clock, and counting the storage size information if the condition is matched; And generating a search memory storage control signal for outputting an address and a write signal of the search memory to store a signal state of a system bus in the search memory as much as the storage size value when predetermined trigger information is matched according to the output of the comparator. The unit 27 is configured to retrieve the state of the system bus by receiving the trigger condition in the system bus clock unit, thereby efficiently testing the system state of the high-speed medium-sized computer or analyzing the performance of the computer.

Description

System bus analyzer of computer system

1 is a block diagram illustrating an example of a general multiprocessor system.

2 is a block diagram showing a system bus analyzer according to the present invention.

3 is a block diagram showing a bus information analyzer to which the present invention is applied.

4 is a state transition diagram of the bus information analyzer shown in FIG.

FIG. 5 is a diagram showing signal lines of the function control module shown in FIG.

6 is a state transition diagram of the function control module shown in FIG.

7 is a signal line of the processor module shown in FIG.

8 is a state transition diagram of the processor module shown in FIG.

9 is a signal line of the search memory module shown in FIG.

FIG. 10 shows the flow of data through the bus interface module shown in FIG.

* Explanation of symbols for main parts of the drawings

1: system bus 2: processor board

3: memory board 4: input / output control board

5: System control board 6,20: System Bus Analyzer

21 processor 22 mask register

23: data register 24: comparator

25: search memory storage control signal generator

26: search memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system bus analyzer for analyzing the state of a system bus in a computer system. In particular, the present invention relates to a system bus analyzer of a symmetric multiprocessor system to search for a signal satisfying a trigger condition (i.e., a transaction trigger condition). An apparatus for controlling to store at a predetermined size in a predetermined position.

In general, in a multi-processing system based on a bus structure and shared memory, each processor board shares a bus and a memory, and all data transfer is performed through the bus. Therefore, by searching the data transmitted through the system bus, it is possible to grasp the operating status of the system to find out the operational error and to infer the actual system performance.

That is, as shown in FIG. 1, a multiprocessor computer system includes a plurality of processor boards 2, a memory board 3, an input / output control board 4, and a system control board on one system bus 1; 5) is connected to exchange data via the system bus (1). In such a multiprocessor system, the system bus 1 is an important factor in determining the performance of a computer. Thus, the performance of the system bus can be measured by the system bus analyzer 6.

The system bus analyzer 6 provides a function of searching, storing, and processing data on the bus with various trigger environments, and analyzing the performance of the system bus, such as measuring the utilization of the system bus, and functions as a responder (ResPonder). Such a system bus analyzer 6 is not included in the basic configuration of a high-speed medium-size computer, but it is mounted on the system bus backplane and the data driven on the system bus as needed, such as when performing a system integration test or analyzing the performance of the system bus. Search, store and process to analyze the state of the system bus in a specific situation or to measure the performance and provide it to the user.

However, since the conventional system bus analyzer is asynchronous bus occupied type, it is difficult to apply to a high speed medium computer using the synchronous bus using the PANED protocol. It cannot be used directly on high speed medium computers using HiPi ⁺ bus, and its function also has a simple problem.

Accordingly, the present invention is applied to a system bus analyzer in a symmetric structured multiprocessor system using a HiPi ⁺ bus, a system bus that controls to search for a signal that satisfies a predetermined trigger condition and store the predetermined size according to a predetermined position signal. The purpose is to provide an analysis device.

In order to achieve the above object, the apparatus of the present invention is a system bus analyzer configured to search for and monitor signals on a system bus of a multiprocessor system in a predetermined unit, wherein the system bus according to predetermined search position information and size information. A retrieval memory for storing a signal of; A processor configured to output a signal for a trigger condition, read and process data in a search memory, and provide the same to a user; A mask register for storing a money care trigger condition input from the processor; A data register for storing a care trigger condition input from the processor; A command register for storing search position information and storage size information input from the processor; A comparator for comparing the trigger condition stored in the mask register and the data register with signal information of a system bus for each bus clock, and counting the storage size information if the condition is matched; And generating a search memory storage control signal for outputting an address and a write signal of the search memory to store the signal state of the system bus in the search memory as much as the storage size value from the predetermined position information when the trigger condition is matched according to the output of the comparator. It is characterized by consisting of wealth.

That is, the present invention compares the signals of the latched system bus with a predetermined trigger condition every bus clock, and matches all of them in a predetermined unit. The system bus information is stored in the search memory. In this case, according to the present invention, the trigger condition may be based on a basic cycle unit (for example, an address basic cycle, a single transmission data basic cycle, a single transmission address data basic cycle, a block transmission data basic cycle, and a block transmission address data basic cycle) or a bus clock unit. Can be set.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

The HiPi ⁺ bus to which the present invention is applied is a synchronous control method, and uses the PANDED protocol. The PENDED PROTOCOL strictly divides the transmission into an information request step and an information response step. This is how you do not affect. The strict classification here means that the bus used for information request and the bus used for information response can be separated, and each bus can be used by performing an arbitration process through a separate arbitrator. By applying this method, the data transfer bus is used only for the actual data transfer, and unlike other standard buses where other processors have not used the system bus due to the continuous bus seizure during memory access time, By using the bus only for transmission, there is an improvement in transmission performance.

Synchronous control is a protocol that prevents collision of information driven on the system bus, and uses the bus by setting a basic cycle according to the type of transmission cycle. The PANDED protocol is similar to the pipeline of data transfer divided into request and response phases, so synchronous control is advantageous over asynchronous.

A system bus analyzer is needed to detect and eliminate an error on a bus in such a system bus. The system bus analyzer stores a signal of a system bus according to a control signal, as shown in FIG. Search memory 27 for; A processor 21 for outputting a signal for a trigger condition, reading and processing data of the search memory and providing the signal to a user; A mask register 22 for storing a don 'care trigger condition input from the processor; A data register (23) for storing a care trigger condition input from the processor; A command register 24 for storing the search position information and the storage size information input from the processor; A comparator 25 for comparing a transaction trigger condition stored in the mask register and the data register with a signal unit of a system bus in a predetermined unit for each bus clock, and counting by a predetermined size information if they match; And a search memory storage control signal generator 26 for outputting a search memory address and a write signal to store a signal state of a system bus in a search memory according to predetermined position information and size information when a trigger condition is matched according to the output of the comparator. It is configured to include).

In FIG. 2, the processor unit 21 transmits the signal information that the user wants to search to the mask register unit 22 and the data register unit 23, and the mask register unit 22 and the data register unit 23. As shown in FIG. In each of the money care information and the information of the signal to be stored is stored. In addition, the processor unit 21 stores the search position information and the storage size information in the command register, and the comparator 25 compares the trigger condition set in the registers with the signal information of the system bus in a predetermined unit to obtain desired information on the bus. When the signal is driven, a signal indicating the signal is output to the search memory storage control signal generator 25 and counted by predetermined size information. When the signal is driven, the search memory storage control signal generator 25 outputs a search memory address according to the predetermined position information, and stores the information of the corresponding system bus corresponding to the predetermined size information in the search memory 27, and the processor unit ( 21). In this case, the retrieval memory storage control signal generation unit 25 stores latched system bus information that satisfies the trigger condition. From this data, the retrieval memory storage control signal generation unit 25 may store data as much as predetermined size information in the predetermined position information.

As such, the bus information analyzer of the high-speed medium-size computer to which the present invention is applied is a tool for supporting the construction of an integrated system. By monitoring, storing, retrieving, and analyzing all signals driven on the system bus, the system error or abnormal operation status is informed to the tester. Allow appropriate action to be taken.

Next, as shown in FIG. 3, the system bus analyzer to which the present invention is applied latches system bus information every clock to provide the function control module 34 (FCM) and the search memory module 33 (TM). Bus interface module (31: BIM), Clock generation module (32: TPC) which receives various system clocks and provides various clocks used in bus analyzer, Search memory module (33: TM) which stores trace information about system bus And a function control module 34 (FCM) and a processor module 35 (CPU) for controlling the search by comparing the trigger condition and system information.

First, the system bus analyzer to which the present invention is applied monitors, stores, retrieves, and processes all signals driven on the HiPi ⁺ bus, which is a system bus of a high-speed medium-sized computer, and provides various types of information according to a user's request. In the system bus analyzer, the system bus search function monitors all signals driven on the system bus, stores signals satisfying the trigger condition in the search memory 33, and groups them into groups of individual bus signal lines. To provide. Here, the trigger condition may be classified according to the trigger condition type, trigger logic, and storage method as shown in Table 1 below. In the embodiment of the present invention, the trigger condition is limited according to the bus clock.

Referring to Table 1 above, in the embodiment of the present invention 'Bus operation basic cycle single storage' function is HiPi It is a function that retrieves a series of transitions from request to response of data by using the basic cycle of the bus, the address basic cycle, the data basic cycle, and the address / data basic cycle as trigger conditions. These features provide the trigger logic for AND or ANDO within each basic period or transaction. Continuous 128K bus clock data can be stored based on the data satisfying the set trigger condition, and the area of the data to be saved is the 8K bus clock at the front and the 120K bus clock at the center. 16 types of trigger positions can be specified, such as setting or setting the previous 128K bus clock.

And 'Bus operation basic cycle multi-block storage' function is HiPi The basic cycle of the bus, the address basic cycle, the data basic cycle, and the address / data basic cycle are used as trigger conditions, and a function of storing a plurality of data blocks that satisfy the same trigger condition can store up to 1024 blocks. Each block can contain 128 bus cycles of data, including data that satisfies the trigger. However, in case of read transaction, up to 512 blocks can be stored and 256 bus clock data including data satisfying trigger condition can be stored for each block. In addition, four types of trigger positions are provided, such as storing the data of the previous 32 bus clocks, the data of the 96 bus clocks later, or the data of the previous 128 bus clocks.

'Bus clock cycle single block storage' function satisfies the trigger logic of the combination of AND, AND and OR for the set trigger condition among the signals driven in each bus clock, and the bus interface part 3 of the bus information analyzer Data to be latched. At this time, up to 128K clock data can be stored based on this data.The data of the front 8K bus clock and the back 120K bus clock are stored or only the data of the previous 128K bus clock is stored. 16 kinds of trigger positions can be set.

The bus clock cycle multi-block storage function stores a plurality of bus data blocks that satisfy a set trigger condition among the signals driven in each bus clock. Up to 1024 blocks can be stored, and data of 128 bus clocks including data that satisfy the trigger condition can be stored for each block. Based on the data satisfying the trigger condition, four types of trigger positions can be set: the data of the previous 32 bus clocks, the data of the 96 bus clocks behind, or the front 128K only. As mentioned above, specific numerical values are referred to for easy understanding of the present invention, and may be changed to arbitrary values according to designers when they are actually applied, and thus should not be limited to numerical values in interpreting the technical idea of the present invention. will be.

On the other hand, in a high speed medium-size computer, the system bus is basically a path of data movement, and this data movement is performed between beams mounted on the bus, and the board participating in the data transmission is required depending on what is done at a specific time. It is divided into Requester and ResPonder. A requestor is a board that actively participates in data movement and starts data transmission, and a responder is a board that passively participates in data transmission and responds to data transmission of the requestor.

As described above, data transmission between the requester and the response period is performed in a bus operation, and the bus operation is composed of a basic cycle. The basic cycle consists of phases that go in a certain sequence that cannot be separated, and each phase takes one bus clock cycle. Here, the basic cycle includes an address basic cycle, a single transmission data basic cycle, a single transmission address data basic cycle, a block transmission data basic cycle, and a block transmission address data basic cycle. And HiPi The bus clock on the bus is, for example, 16.5 MHz, and the bus clock period is 60.6 nsec, and is composed of 293 signal lines. Can be grouped together.

On the other hand, the operating state of the system bus analyzer is an idle state, as shown in FIG. There is a function control module status in which the function control module searches for data on the system bus in accordance with the search start command of the module. At this time, if the trace-request signal is driven in the idle state, it is processed to the processor module state, and in the processor module state, Start When the signal is driven, it transitions to the function control module state, and Done or Stop in the function control module state. After the signal is driven, it becomes the processor module state and stops at the processor module state. When the signal is driven, it is idle.

Next, the operation of the embodiment of the present invention will be described in detail by dividing each module.

1. Function control module

The function control module 34 (FCM Module) includes a mask register 22, a data register 23, a comparator 25, and a search memory storage control signal generator 25 for setting a trigger condition. In step 27), information on the system bus is written. Therefore, when the system bus data is to be stored in the retrieval memory 27, it is possible only through the function control module 34. The function control module 34 determines whether to store the data on the system bus latched by the bus interface module 31 in the search memory 33 by comparing with the set trigger condition, and manages the overall state of the bus information analyzer, Initializes the search memory 33, generates a control signal, and generates an address during a search memory write operation. In addition, a search condition set in each register is compared with information on an actual bus, and when a condition is satisfied, a signal for notifying the driver is driven, and a time sequence signal is generated and stored in a specific bank of the search memory 33. Functions performed by the function control module 34 include a trigger condition comparison search function, an address control, and a search memory write function.

Here, the trigger condition comparison search function compares the data transmitted from the bus interface module 31 with the trigger condition, and determines whether to store the data in the search memory 33 according to whether or not it is satisfied. This is performed every cycle of the system bus. Because we need to search for the signals that are driven, we perform all the operations in one cycle. The address control and search memory write function drives a control signal necessary for storing data satisfying the trigger condition in the search memory 33 to perform a write operation. The function control module 34 notifies the processor module 35 that the operation has ended when all of the above operations are completed, and waits in a ready state.

The function control module 35 has signal lines as shown in FIG. 5, and the major signals among these signal lines are defined as follows. 'SCLK' is a system clock of 16.5MHz provided by the clock generator 32: TPG, 'CPU_request_' is an input signal driven by the processor module 35 to obtain control, and 'Start_' is a processor module 35 In FIG. 3, an input signal for driving the control right to the function control module 34 informs the execution of the search of the function control module. 'Stop_' is an input signal that informs the function control module 34 of the processor module 35 that all the use of resources has been completed. If the signal is driven while the function control module is performing a search, the interrupt signal informs the termination. Used as a signal.

The 'DoneACK' signal is an input signal received as a response signal to the Done, and the 'P_inBUS <31: 0>' signal is a 32-bit dedicated bus transmitted from the processor module. 'REGsel (17: 0>' signal is an 18-bit register select input signal transmitted from the processor module 35. Registers 0, 15, 16, and 17 are read only, and resistors 1 through 14 Write only (write only) The CPU drives the low active level trigger signal during the read operation and the low active edge trigger signal during the write operation.

'Busin_Data' is a data signal line for system bus information transmitted from a bus interface (BIF) module, and receives data driven on these signal lines every cycle as inputs, compares with a trigger condition, and performs address control. 'Busin_Data 〈282〉' is HiPi Trigger signal provided externally by signal line not defined on bus.

'Ctl_sta &lt; 1: 0 &gt;' is a control state signal line for synchronization between modules, and only the function control module 34 can control the state. According to the status of the control bit, each module outputs the current state as shown in the following table.

'F-Addr &lt; 16: 0 &gt; &quot; is an address signal line transmitted to the search memory module 33. The F-Addr &lt; 16: 0 &gt; 'F_outDATA' is a signal line that transfers the contents of the status register or counter register to the processor module 35. 'Time_seq' is timer data transmitted to the search memory module 33. After initialization, timer starts and resets after searching ends. 'Init_TM' is an output signal informing the initialization operation status of the function control module 34. 'SAT' is an externally provided trigger condition satisfaction signal, which is driven only when the trigger condition is satisfied and is driven for one cycle. 'Done' is a signal indicating that all the search storage functions are completed, and used as an interrupt signal to the processor module 35.

As shown in FIG. 6, the function control module has FIDLE, INIT, Single_S, Transac_S, S_Level, Single_M, Transac_M, and M_Level, respectively.

In FIG. 6, 'FIDLE' indicates that the function control module is in an idle state, 'INIT' indicates a state of initializing the contents of the search memory before searching, and 'Single_S' indicates the trigger condition of the bus clock cycle single block storage function. It repeats until it is satisfied.

'Trans_S' repeats the basic operation of the bus operation cycle single block until it satisfies the trigger condition, 'Single_M' is the state of the bus clock cycle multiblock storage, and 'Trans_M' is the operation of the bus cycle basic cycle multiblock storage. When the trigger of the specified number of blocks set in the trigger condition occurs, the search ends.

'S_level' is to save as many cycles as specified based on the point that satisfies the trigger condition. The search is terminated after the completion of storage. 'M_level' is to save as many blocks as specified based on the point where the trigger condition is satisfied. Continue to save and finish the search after saving.

2. Processor Module

The processor module 35 provides an interface with the user and provides a trigger condition to the function control module 34 when receiving the user's search and store instruction to instruct the function control module to perform a substantial search and storage function. When the search storage function is terminated by the function control module 33, a search memory read operation is performed to obtain a stored search result, and after processing the read data, the system bus information is displayed to the user. In addition, while the search storage function is being performed by the function control module 34, the processor module 35 periodically retrieves the counter register value and displays information on the bus utilization rate to the user.

This processor module has a signal line as shown in FIG. 7, and the meanings of the signal lines are as follows.

'inBUS <31: 0>' is a 32-bit data input bus used when reading status registers or counter registers from the function control module 34 or data stored in the search memory 33, and 'ctlacq <1' : 0> 'is the control status input signal for synchronization between modules. The processor module 35 sees this signal driven from the function control module 34 to request control right or to grasp the current operation progress. 'Done' is an interrupt input signal driven from the function control module 34 and the processor module returns control right by this signal. 'Reset_' is an output signal for resetting each module, and is driven when a pushbutton reset or a power-on reset is operated. 'CPU_request' is an output signal that requests the function control module 34 to obtain control. 'Start' is a signal indicating the start time so that after the trigger condition is applied to the function control module 34, the function control module can retrieve data on the system bus and store data in the search memory 33. This signal must be driven after acquiring control. 'Stop' is a signal indicating that the use of the processor module 35 is all finished, and the control right is transferred to the function control module. 'DoneACK' is a response signal for the Done signal driven from the function control module 34, 'outBUS <17: 0>' is a path for transmitting data necessary to perform a register write operation, and 'S_REG' is a register. As a signal line for selecting a target register to perform a read or register write operation, it is required to maintain a low active state for a read operation and to transition from low to high for a write operation.

'P_Addr <19: 3>' is an address signal line used to read data stored in the search memory 33. The 'P_Addr <19: 3>' drives the 'S_TM <9: 0>' signal together to obtain 32 bits of data. 9: 0> 'is a signal line that selects one of ten banks in the search memory module to read data stored in the search memory.

As shown in FIG. 8, the processor module changes its operation state, where 'A' is a search-related operation state, and 'B' is a display-related operation state for informing a user of a search result.

The processor module 35 is in an idle state, drives the CPU_request signal by the 'Request' signal, acquires a control right, and then records the trigger condition in the mask register and the data register to set the search condition. After driving the signal, it waits in the idle state, wakes up by the 'Done' signal, reads the search memory data, processes it, displays it, and determines whether to continue searching. If not, stop After driving the signal, it transitions to the idle state.

3. Search memory module

The search memory module 33 receives data from the bus interface module 31 and stores the data in the search memory or transmits the stored data to the processor module through the local bus.

Signal lines of such a search memory module are shown in FIG. 9, which will be described below.

'F_Addr <16: 0>' is an address signal line controlled by the function control module 34 and is an input signal for writing bus information from the system bus into the search memory, and 'P_Addr <18: 2>' is a processor module 35. Is an address signal line to be controlled during the search memory read operation.

'TM <9: 0>' is a search memory bank address signal line controlled by the processor module 35, and is used during read operation in the processor module 35, and 'InTraceDATA <319: 288>' is provided by the function control module. Information about time is transmitted, and 'inTraceDATA &lt; 288: 0 &gt; is a signal line which latches and provides data driven on the system bus in the bus interface module 31.

'owner <1: 0>' indicates a module that has control over the current search memory, and the memory control unit restricts the right to write and read operations according to the module having control. Rights to writes are only in the function control module, and processor modules only have rights to reads.

'clkE' and 'clkS' are clock signal lines for writing the search memory, and 'outBUS <17: 0>' is a path for transmitting data according to a data read request of the processor module.

4. Bus Interface Module

The bus interface module 31 latches all data driven on the system bus and transmits the data to the search memory module 33 and the function control module 34. That is, the bus interface module 31 is a system bus (HiPi in the embodiment of the present invention), as shown in FIG. Bus lines are input through the BTL buffer and latched to the D flip-flop to transfer the system bus information to the function control module and the search memory. At this time, the data bus arbitration bus through the DBARB buffer 41, the data bus through the Data BUS buffer 42, the status bus through the Status Bus buffer 43, and the address bus arbitration bus through the AARB buffer 44. , Address bus is Addr. Via the bus buffer 45, the interrupt bus is latched through the Int. Bus buffer 46, and the utility bus is latched through the Utility Bus buffer 47.

As described above, the bus information analyzer to which the present invention is applied is HiPi. A total of 283 signals can be searched from the total of 293 signal lines appearing on the bus, including 282 signals and one external trigger element signal.

5. Clock Generation Module

The clock generation module 32 receives the system bus clock driven on the system bus and provides an internal clock to each module in the bus information analyzer.

As described above, the system bus analyzer according to the present invention can efficiently test the system state of a high-speed medium-size computer or analyze the performance of the computer by searching for the state of the system bus by receiving transaction trigger conditions in basic cycle units of the system bus. It can work.

Claims (1)

A system bus analyzer configured to search and monitor signals on a system bus of a multiprocessor system in a predetermined unit, the system bus analyzer comprising: a search memory 27 for storing signals of a system bus according to predetermined search position information and size information; A processor 21 for outputting a signal for a trigger condition, reading and processing data of a search memory and providing the signal to a user; A mask register 22 for storing the money care trigger condition input from the processor; A data register 23 for storing a care trigger condition input from the processor; A command register 24 for storing the search position information and the storage size information input from the processor; A comparator 25 for comparing the trigger condition stored in the mask register and the data register with signal information of a system bus for each bus clock, and counting the storage size information if the condition is matched; And generating a search memory storage control signal for outputting an address and a write signal of the search memory to store a signal state of a system bus in the search memory as much as the storage size value when predetermined trigger information is matched according to the output of the comparator. A system bus analysis device for a computer system composed of a section 27.