KR0170893B1 - Strobe signal buffer circuit - Google Patents

Abstract

The strobe signal buffer circuit of the present invention is used in a memory device to prevent a latch-up phenomenon that may occur when an initial power supply voltage is applied from the outside. To this end, the strobe signal buffer circuit includes first buffer means for buffering a column address strobe signal from a first input terminal and supplying a buffered column address strobe signal to an output terminal, and a row address strobe from a second input terminal. A second buffer means for buffering a signal to supply a buffered row address strobe signal to an output terminal, and a first control for detecting whether a substrate voltage is at a first voltage level and controlling the operation of the first buffer means according to the result. Means and second control means for detecting whether the substrate voltage is at a second voltage level and controlling the operation of the second buffer means according to the result.

Description

Strobe signal buffer circuit

1 is a timing diagram of a conventional initial power supply voltage and strobe signal.

2 is a block diagram of a strobe signal buffer circuit according to an embodiment of the present invention.

3 is an input and output waveform diagram of the circuit shown in FIG.

4 is a circuit diagram showing an example of the first control unit shown in FIG.

5 is a circuit diagram illustrating an example of the second control unit illustrated in FIG. 2.

* Explanation of symbols for main parts of the drawings

10: first control unit 20: cas buffer unit

30: second control unit 40: Lars buffer unit

The present invention relates to a strobe signal buffer circuit of a semiconductor device, and more particularly, to a strobe signal buffer circuit for preventing a latch-up phenomenon that may occur when an initial power supply voltage is applied from the outside.

The substrate voltage Vbb of a semiconductor device, such as a conventional DRAM, a PSRAM, a cache RAM, or the like, requires a certain time to reach a stable state by receiving an initial power supply voltage from an external source. However, if a trigger signal (TRRIGGER SIGNAL) such as an address strobe signal (ADDRESS STROBE SIGNAL) occurs inside and outside the memory device before the memory device reaches the stable state, the memory device loses its own property or is destroyed. There is a problem that can be.

In order to eliminate the above problems, a conventional memory device generates a power stabilization signal that transitions from a high level to a low level when a substrate voltage reaches a stable voltage level, and among the address strobe signals, a low address strobe signal is stabilized. Under control of the signal.

However, when the initial power supply is applied, the low and column address strobe signals (hereinafter, the las and cas signal) and the write signal from the outside are input as shown in FIG. 1B without following the variation of the power voltage Vcc as shown in FIG. If so, a certain time is required from the moment the power supply voltage is applied until the high level state, which is the DISABLE state, is input. In the meantime, a low level signal equal to the ENABLE state is applied, and the memory device recognizes the read scroll error incorrectly, thereby driving a pull-up NMOS TRANSISTER of a data output buffer to drive the memory. The problem is that the device loses or breaks its inherent properties.

Accordingly, an object of the present invention is to ensure the stability and reliability of the memory device even if the cas and ras signals and the write signal from the outside are input at the same low level as the ENABLE state for a period of time at the moment when the power is applied. The present invention provides a strobe signal buffer circuit.

In order to achieve the above object, the strobe signal buffer circuit of the present invention includes a first buffer means for buffering the column address strobe signal from the first input terminal to supply the buffered column address strobe signal to the output terminal, and the second input Second buffer means for buffering the row address strobe signal from the terminal and supplying the buffered row address strobe signal to the output terminal, and detecting whether or not the substrate voltage is at the first voltage level. First control means for controlling the operation, and second control means for detecting whether the substrate voltage is at the second voltage level and controlling the operation of the second buffer means according to the result.

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

FIG. 2 is a block diagram of a strobe signal buffer circuit according to an embodiment of the present invention, and the transfer time until the substrate voltage as shown in FIG. 3a reaches a stable voltage level Vbb at the moment power is applied from the outside. The first control unit 10 for recognizing the specific voltage V1 at the stable voltage as the substrate voltage and outputting the same signal as the signal of FIG. 3a, and the substrate voltage of the memory device is Vbb at the specific voltage V1. The second control unit 30 and the signal from the first control unit 10 that recognizes the specific voltage (V2) in the time domain until reaching to a stable state and outputs a signal as shown in FIG. In response to the cas signal (/ CAS) from the outside to receive the buffer buffer 20 and the second from the second control unit 30 according to the signal from the external input ras signal (/ RAS) A lath buffer part 40 which receives and buffers is provided.

As illustrated in FIG. 4, the first controller 10 includes a PMOS transistor Q1 (PMOS TR) installed between a power supply voltage Vcc and a node N1 and whose gate is connected to a ground voltage Vss. NMOS transistor Q2 (NMOS TR), which is installed between ground voltage Vss and node N1 and whose gate is connected to substrate voltage Vbb, and PMOS transistor Q1 and NMOS transistor Q2. A plurality of inverters 12 and 13 are provided between the node N1 and the output stage 14 therebetween.

In the PMOS transistor Q1, the gate is grounded to the ground voltage Vss so that the PMOS transistor Q1 is always kept in an ON state.

Accordingly, when the substrate voltage Vbb as shown in FIG. 3c on the input line 11 reaches V1 after a predetermined time T1 has passed, this V1 is lower than the threshold voltage of the NMOS transistor Q2. The NMOS transistor Q2 is turned off and the node N1 has a level transition from low to high level, and the signal on the output line 14 also transitions from low to high level. The operation 20 is performed by the external CAS signal / CAS.

As shown in FIG. 5, the second control unit 30 includes a PMOS transistor Q3 (PMOS TR) installed between the power supply voltage Vcc and the node N2 and whose gate is connected to the ground voltage Vss. , An NMOS TR (Q4) connected between the ground voltage (Vss) and the node (N2) and a gate connected to the substrate voltage (Vbb), the PMOS transistor (Q3), and the MOS transistor (Q4). And a plurality of inverters 32 and 33 installed between the node N2 and the output terminal 34 between the terminals.

In the PMOS transistor Q3, the gate is grounded to the ground voltage Vss so that the PMOS transistor Q3 is always kept ON.

Accordingly, the substrate voltage Vbb as shown in FIG. 3C on the input line 31 has a level lower than the threshold voltage of the NMOS transistor Q4 after V2 has a predetermined time T2. Since the transistor Q4 is turned off and the potential of the node N2 transitions from low to high level, and the signal on the output line 34 also transitions from low to high level, the las buffer 40 has an external lath signal. The operation is performed by (/ RAS).

Here, in the embodiment of the present invention, the NMOS transistor Q4 is driven at a relatively low level because the ratio of the channel length to the channel width is greater than that of the NMOS transistor Q2.

The cas buffer unit 20 receives a low level cas signal (/ CAS) from the outside and buffers the external power stabilization signal as shown in FIG. 3a to the low level from the first control unit 10. The las buffer unit 40 receives a low level lath signal (/ RAS) from the outside at the moment when the power stabilization signal, such as 3b, transitions to the low level from the second control unit 30. Output to the outside.

The time difference between the cas buffer unit 20 and the las buffer unit 40 is operated after the casing buffer unit 20 is operated after the power-on T1, the las buffer unit 40 is operated after the T2. As a result, the operation of the cas buffer unit 20 is faster than the operation of the Lars buffer unit 40 to enter the CAS-BEFORE-RAS mode.

As described above, the strobe signal buffer circuit of the present invention arbitrarily specifies two power supply voltage stabilization levels at a transition time before the power supply voltage is externally applied and reaches a stable level. By affecting the cas buffer to enter the refresh mode, the latch-up phenomenon is prevented.

Claims (4)

First buffer means for buffering the column address strobe signal from the first input terminal and supplying the buffered column address strobe signal to the output terminal, and a row address buffered by buffering the row address strobe signal from the second input terminal. Second buffer means for supplying the strobe signal to the output terminal, first control means for detecting whether the substrate voltage is at the first voltage level and controlling the operation of the first buffer means according to the result, and the substrate voltage being the second voltage. And a second control means for detecting the application of the voltage level and controlling the operation of the second buffer means according to the result. 2. A fixed resistor according to claim 1, wherein said first control means is provided between a power supply voltage (Vcc) and a node (N1), and a fixed resistor having a gate connected to a ground voltage (Vss), and a ground voltage (Vss) and a node (N1). And a plurality of inverters 12 and 13 disposed between the node N1 and the output terminal 14 between the fixed resistor and the active resistor, the active resistor having a gate connected to the substrate voltage Vbb. The second control means is installed between the power supply voltage Vcc and the node N2 and is provided between the fixed resistor with the gate connected to the ground voltage Vss and the ground voltage Vss and the node N2, and the gate Strobe signal buffer, characterized in that it comprises an active resistor connected to the substrate voltage (Vbb), and a plurality of inverters (32, 33) provided between the node (N2) and the output terminal 34 between the fixed resistor and the active resistor. Circuit. 3. The strobe signal buffer circuit according to claim 2, wherein the channel width of the active resistance of the first control means is smaller than the channel width of the active resistance of the second control means. The strobe signal buffer circuit according to claim 2, wherein the fixed resistor is a PMOS transistor and the active resistor is an NMOS transistor.