KR0168800B1 - Apparatus and method for frequency hopping - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method and apparatus for generating a hopping frequency in a frequency hopping / code division multiple access system.

2. The technical problem to be solved by the invention

It provides a hopping frequency generator that provides a hopping pattern for multiple channels and enables a frequency hopping change without interrupting system operation.

3. Summary of Solution to Invention

The present invention discloses a hopping frequency generator comprising at least a memory consisting of two blocks for storing hopping patterns for each of all channels to be used in the system. In one block of the memory, a jump pattern to be used is stored. The hopping pattern of any one of the hopping patterns for the multiple channels thus stored is selected at the time of frequency hopping and synthesized with the corresponding frequency to generate the hopping frequency. As such, since the hopping pattern for a plurality of channels is stored in advance in the memory, only the hopping pattern of the corresponding channel is selected during the operation of the actual system. Therefore, the present invention can efficiently generate the hopping frequency regardless of the increase or decrease of the number of channels. In addition, it is possible to implement a system having the same configuration regardless of the number of channels. On the other hand, another jump pattern for changing the hop frequency is stored in another block of the memory. At this time, the storage operation of the jump pattern is performed between the previously stored jump pattern is output. That is, an operation of outputting a previously stored hopping pattern is performed at each time of frequency hopping, and an operation of storing another hopping pattern for changing the hopping frequency in another block of the memory is performed between frequency hopping time points. . As described above, the present invention may be caused by changing the hopping frequency without interrupting the operation of the system because the timing of the operation of outputting the hopping pattern is different from the operation of storing the harmful hopping pattern.

4. Important uses of the invention

Transmitter of Frequency Hopping / Code Multiplexing Multiple Access System

Description

Hopping frequency generation method and device

1 is a diagram showing the configuration of a transmitter of a frequency hopping / code multiplexing multiple access system according to the prior art.

2 is a diagram illustrating a network configuration of a frequency hopping / code multiplexing multiple access system under a multiple access situation.

3 is a view showing the configuration of the hopping frequency generator according to the present invention.

FIG. 4 is a diagram showing the channel structure of the memory shown in FIG.

5 is a diagram illustrating an example of a fourth channel hopping pattern stored in a ping block of a memory structured as shown in FIG.

6 is a view showing the timing of the hopping pattern output operation and the CPU access operation of the hopping frequency generator according to the present invention.

FIG. 7 is a diagram showing the configuration of the address generator shown in FIG.

FIG. 8 is a diagram showing the configuration of the frequency mapper shown in FIG.

* Explanation of symbols for main parts of the drawings

300: address generator 320: central processing unit (CPU) access unit

340: Multiplexer (MUX) 360: Memory

380: frequency mapper

The present invention relates to a method and apparatus for generating a hopping frequency in a frequency hopping / code division multiple access system. In particular, the present invention relates to a method for generating a hopping frequency and provides a hopping pattern for a plurality of channels and enables the hopping frequency to be changed without interrupting system operation. And to an apparatus.

Spread Spectrum Communication refers to a method of communicating with a transmission bandwidth wider than that of a message signal to be transmitted. According to spread spectrum communication, the energy of a transmitted signal generally occupies a wider bandwidth than the bandwidth occupied by a binary coded digital signal consisting of 0s and 1s, and demodulation takes the received signal with the same spread signal as the signal spread. By despreading. In a conventional communication system, when multiple users use the same transmission frequency band, interference occurs and communication cannot be performed. However, in spread spectrum communication, the same transmission frequency band can be coded and used by multiple users.

A spread spectrum communication system (hereinafter referred to as a CDMA system) that enables code division multiple access (FDMA) uses a frequency hopping method and a direct sequence depending on how the transmission / reception data is processed. ), Time hopping, etc. The transmitting section of a CDMA system (hereinafter referred to as an FH / CDMA system) using the frequency hopping scheme is generally configured as shown in FIG.

Referring to FIG. 1, the frequency at the transmitter of an FH / CDMA system is generated by a frequency synthesizer 104, and the frequency and the data source 106 modulated by the baseband modulator 106. ) Is mixed by the mixer 110 and then transmitted. The frequency hopping is performed by mapping the PN code as a hop pattern generated in the PN (Pseudo Noise) code generator 102 to the frequency in the frequency synthesizer 104.

As shown in FIG. 1, the frequency hopping in the transmitter of the conventional FH / CDMA system is performed as the hopping pattern generated by the PN code generator 102 is input to the frequency synthesizer 104. FIG. This configuration can be easily used when using a fixed jump pattern or when the number of channels is small.

Meanwhile, the FH / CDMA system is preferably used under a multiple access situation as shown in FIG. However, as the number of channels increases under the multiple access situation, the mobile stations MS1, MS2, MS3, ... MSn-1, MSn, 202 to 210 should be able to provide a hop pattern for all channels. Because the mobile station is assigned a channel from the base station 200 when the mobile station requests a call to the base station 200, the mobile station should be able to generate a leap pattern for all channels. As described above, in order to generate the hopping pattern for all channels, the PN code generator has to be provided as many as the number of channels.

On the other hand, in FH / CDMA systems, it is often necessary to change the jump pattern to ensure incompatibility. However, since the hopping pattern is generated by the PN code generator in the transmitter of the conventional FH / CDMA system, the hopping pattern has to be changed after blocking the call operation of the system.

Accordingly, an object of the present invention is to provide a method and apparatus for efficiently generating a hopping frequency even when an FH / CDMA system is used under a multiple access situation.

Another object of the present invention is to provide a hopping frequency generator having the same hardware configuration regardless of the number of channels in an FH / CDMA system.

It is still another object of the present invention to provide a method and apparatus for changing a hopping frequency without interrupting a call operation in an FH / CDMA system.

Still another object of the present invention is to provide a method for generating a hopping frequency for a corresponding channel using a hopping frequency generator having a simple structure, regardless of which channel is allocated in an FH / CDMA system.

The present invention for achieving the above objects discloses a hopping frequency generating device including at least a memory structured in two blocks for storing hopping patterns for each of all channels to be used in the system.

In one block of the memory, a jump pattern to be used is stored. The hopping pattern of any one of the hopping patterns for the multiple channels thus stored is selected at the time of frequency hopping and synthesized with the corresponding frequency to generate the hopping frequency. As such, since the hopping pattern for a plurality of channels is stored in advance in the memory, only the hopping pattern of the corresponding channel is selected during the operation of the actual system. In addition, it is possible to implement a system having the same configuration regardless of the number of channels.

On the other hand, another jump pattern for changing the hop frequency is stored in another block of the memory. At this time, the storage operation of the jump pattern is performed between the previously stored jump pattern is output. That is, an operation of outputting a previously stored hopping pattern is performed at each time of frequency hopping, and an operation of storing another hopping pattern for changing the hopping frequency in another block of the memory is performed between frequency hopping time points. . As described above, the present invention can be generated by changing the hopping frequency without interrupting the operation of the system because the timing of outputting the hopping pattern and the operation of storing the new hopping pattern are different.

Each block of the memory stores a series of hopping patterns for each of a plurality of channels, and each hopping pattern is composed of a hopping sequence.

The operation of selecting and outputting a hopping pattern of any one channel among a plurality of hopping patterns stored in one block of the memory is performed by an address generator, and the address generator provides various information-blocks provided from the central processing unit. Select one block of memory according to the designation information, channel designation information, and jump sequence designation information, select a leap pattern of one channel among the blocks, and select a leap sequence within a predetermined range among the leap patterns of the channel. .

The operation of storing the new jump pattern in another block of the memory is performed by the CPU access unit. The CPU access unit receives a hop pattern for each of the plurality of channels from the CPU, and provides the hop pattern to the memory through the memory data bus to be stored. At this time, the area of the memory in which the hopping pattern is to be stored is designated by generating an address for accessing the area of the memory while the CPU accessing unit outputs the hopping pattern.

The jump pattern is provided to the memory through a memory data bus, but the address generated by the CPU access unit and the address generated by the address generator are provided to the memory through different paths. At this time, addresses from the central processing unit and the address generator that access the area of the memory are selectively selected by the multiplexer and provided to the memory. The selection operation of the multiplexer also depends on the selection signal provided from the central processing unit. When the select signal has any level, the selector selects an address from the address generator and provides it to the memory, so that the hop pattern of the corresponding channel is output. The hop pattern thus output is synthesized at a corresponding frequency and generated as a hop frequency. When the select signal has another level, the selector selects an address from the CPU access unit and provides the address to the memory, thereby storing the hopping pattern through the memory data bus in the corresponding memory area.

Since the two operations occur with a time difference from each other, it is possible to change the hopping frequency without interrupting the operation of the system. In addition, even when generating the hopping frequency, the hopping pattern of any one channel among the hopping patterns of the plurality of channels stored in the memory can be selected and output, thereby simplifying the configuration of the hopping frequency generator.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used as much as possible even if displayed on different drawings. In addition, in the following description, many specific details such as components of specific circuits are shown, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. It will be obvious to those of ordinary skill in the field. In addition, the terms to be described below are terms defined in consideration of functions in the present invention, and may vary according to the intention or custom of the user or chip designer, and the definitions should be made based on the contents throughout the present specification.

3 is a view showing the configuration of the hopping frequency generator according to the present invention, and performs the function of the PN code generator shown in FIG. In other words, the output of the PN code generator in FIG. 1 corresponds to the output of the memory 360.

In FIG. 3, the memory 360 is a place where a hop pattern is stored and is configured as a RAM. The hop pattern is generated by the hop pattern generation algorithm and then written to the memory 360 in order. As shown in FIG. 4, the memory 360 includes two blocks, a ping and a pong, and in each block, the hopping pattern of each channel is sequentially stored from channel ø to channel M. FIG. The address generator 300 is a part that generates an address of the memory 360, and selects one block of a ping block and a pong block under control of a central processing unit (not shown). Select any channel in the selected block. The addressing of the hopping pattern in the channel is performed by a counter. The CPU access unit 320 analyzes a signal from the CPU to address the memory 360 so that the CPU can read / write the contents of the memory 360. Since the multiplexer (MUX) 340 accesses the memory 360 in two places, the address generator 300 and the CPU access unit 320, the multiplexer (MUX) 340 selects one of them. The frequency mapper 380 converts data of the hopping pattern output from the memory 360 into frequency synthesizer (FS) data. The frequency mapper 380 is an element that is configured inside the frequency synthesizer 104 in FIG. 1, but is shown for convenience of description of the present invention.

Referring to the operation of the hopping frequency generator according to the present invention configured as shown in FIG. 3 in more detail as follows.

First, the memory 360, which is the core configuration of the present invention, is structured as shown in FIG. The memory 360 is a RAM where the jump pattern is stored. The reason for the configuration of the RAM is to make it easy to store the jump pattern generated by the jump pattern generation algorithm when the system is initialized, and to easily change the jump pattern at any time during the operation of the system. As shown in FIG. 2, the memory 360 is largely divided into a ping block and a pong block, and the ping block and the pong block have the same structure and have channel blocks. Each channel block contains information about the frequency at which it actually hops. That is, for example, if the hopping pattern for channel 4 is in the order f1, f100, f35, f9, ..., f82, f2, f99, the channel 4 block of the memory 360 is binary in these frequencies. The values are stored as shown in FIG. However, these frequencies are generated by addressing the memory 360 because the memory 360 is a RAM. The address structure of the memory 360 may vary depending on the number of channels and the hop period used in each channel, but the basic structure is shown in the following table.

Referring to the above table, the memory 360 is addressed with an address of a total of n bits, where A? ~ Am is a lower address that allows access to the hopping pattern in each channel, and the value of m varies depending on the hopping period. Am + 1 ~ An-2 is an address that specifies a channel, and the address bits vary depending on the number of channels. An-1 is an address that designates a ping block / pong block. The following describes the ping block / pong block.

When the system operates, it operates using the leap pattern of either block of ping block or pong block. Assuming that it operates as a ping block at initialization, the contents of the pong block are independent of operation. However, when it is necessary to change the hop pattern of an arbitrary channel during operation, the new hop pattern to be changed cannot be updated to the ping block. Because you are currently communicating on the ping block, if the jump pattern is changed during communication, you cannot continue talking with the other party. Therefore, the leap pattern to be changed should be written to the pong block. When the memory 360 is switched to the pong block at the time of synchronization of the frequency hopping, the hopping pattern can be changed without disconnection of the communication. Here, the synchronization of the frequency hopping is a synchronization signal necessary to match the same hopping pattern with the same period between communication systems.

As described above, the memory 360 is addressed with n bits A0 to An-1 to generate a jump pattern.

However, the CPU must access the jump pattern, such as modifying the jump pattern of the memory 360, but cannot access the CPU data bus. This is because memory access and CPU access are asynchronous during the operation of the system, which can result in a collision with the memory access. These problems include a method of configuring the memory 360 as a dual port ram and a method of separating the CPU bus and the RAM bus. However, the method of configuring the memory 360 with the dual port RAM has a problem with the size of the RAM, so in the present invention, the CPU bus and the RAM bus are separated to prevent a collision between the CPU access and the memory access. The key to this is that the CPU must be able to access the jump pattern regardless of normal communication, i.e. regardless of the action that generates the jump pattern. This is possible by using the selection signal SEL for controlling the MUX 340 as a regular signal. In other words, the CPU is to use the time between the jump pattern is generated by the hop clock HCLK. A timing diagram according to this operation is shown in FIG. Referring to FIG. 6, as the hopping pattern is generated at the rising edge of the high level of the hop clock HCLK, FS data is generated, and the CPU access operation is performed at the time between the generation of the FS data.

Another important part of the invention is the address generator 300, with the counter 308 as its main component, as shown in FIG.

Referring to FIG. 7, the output of the counter 308 is the addresses A? -Am of the memory 360. The counter 308 is counted by the hop clock HCLK output whenever the hopping frequency changes. The counter 308 is set to count the area of the memory 360 in which the hopping pattern of one channel is stored. That is, the counter 308 counts the area of the memory 360 in which one of the jump patterns of the plurality of channels stored in the memory 360 is stored according to the hop clock HCLK. However, at this time, not all hop sequences of the hopping pattern are selected to be selected, but only hopping sequences within a predetermined range are counted to be selected. This operation is based on the values stored in the Lower Value register 302 and the Upper Value register 304 by CPU access. In other words, the counter 308 counts the value stored in the lower value register 302 as a starting value, and counts until the value to be counted is equal to the value stored in the upper value register 304 by the comparator 310. do. The comparator 310 outputs a signal to the AND gate 306 to reload the counter 308 when the same value as the value stored in the upper value register 304 is counted by the counter 308. The counter 308 is operated so that the operation of the frequency hopping can be performed more flexibly.

In FIG. 7, CMO through CMn-m-2 of the channel mode register 312 store channel designation information provided from the CPU, and block designation information provided from the CPU is stored in the PPF of the channel mode register 312. The value stored in the channel mode register 312 is provided to the memory 360 as an address along with the value counted in the counter 308. The block of the memory 360 is designated by the value An-1 output from the PPF of the channel mode register 312, and the channel is the value Am + 1 output from CMO ~ CMn-m-2 of the channel mode register 312. It is specified by ~ An-2. The range of the hopping sequence among the hopping patterns of the channel is designated by the values A0 to Am which are counted and output by the counter 308. The hopping sequence stored in the designated area is input to the latch 382 of the frequency mapper 380 configured as shown in FIG.

8 is a diagram showing the configuration of the frequency mapper 380 according to the present invention, which converts the data to FS data, which is a data format for making a frequency in an actual synthesizer. In this case, since the output of the memory 360 input to the latch 382, that is, the data of the hopping pattern is an offset between the hopping frequencies, the adder 386 outputs the output of the latch 382 and the reference frequency generator 384. The reference frequency data generated at is added to output. Since the added and output data are parallel data and output as serial data using a parallel / serial converter 388, a frequency synthesizer synthesizes a corresponding frequency and generates a hopping frequency.

As described above, the present invention provides a hopping frequency generator for storing a hopping pattern and changing the hopping pattern by using a memory having a double structure. Accordingly, even if the number of channels in the FH / CDMA system is increased, there is no need to increase the hardware, thereby simplifying the system configuration. In addition, there is an advantage that the jump pattern can be easily changed without interrupting the operation of the system.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (16)

A hopping frequency generating device of a frequency hopping / code division multiple access system, comprising: a memory storing a hopping pattern for each of a plurality of channels to be used in the system, and a hopping pattern stored in the memory every time the frequency hopping of the system occurs An address generator for generating an address for outputting a hopping pattern of a predetermined channel, and a frequency synthesizer for synthesizing a frequency corresponding to the hopping pattern output from the memory in response to the address generated by the address generator and outputting the hopping frequency Hop frequency generator, characterized in that consisting of. 2. The hopping frequency generator of claim 1, wherein the memory comprises a RAM. The apparatus of claim 1, further comprising a central processing unit providing information designating a predetermined channel to be used in the system, wherein the address generator outputs a jump pattern corresponding to the channel designation information provided from the central processing unit. A hopping frequency generator, characterized in that for generating an address. The hopping pattern of each channel stored in the memory comprises a hopping sequence, wherein the CPU not only provides channel designation information but also designates a range of the hopping sequence of the designated channel. The hopping frequency generator, characterized in that provided to the address generator. The counter according to claim 4, wherein the address generator compares a counter, the jump sequence designation information provided from the central processing unit, and the value counted by the counter, and a value in the range indicated by the jump sequence designation information is assigned to the counter. A comparator for outputting a signal for loading the counter when counted by a channel, and a channel mode register for temporarily designating channel designation information provided from the central processing unit and outputting the channel designation information to the memory together with the value counted at the counter. And the channel counting information temporarily stored in the channel mode register and the value counted in the counter to the memory so that the hopping pattern of the corresponding channel is output to the frequency synthesizer. The hopping frequency generator of claim 5, wherein the counter counts a size value of an area in which a hopping pattern of each channel is stored in the area of the memory. A hopping frequency generator of a frequency hopping / code division multiple access system, comprising: a memory structured by a first block and a second block, and a series of first hopping patterns allocated to each of a plurality of channels to be used in the system; Providing a jump pattern and providing a second jump pattern according to the hop frequency change request; a memory data bus; and the first jump pattern or the second jump pattern provided from the central processing device. Outputting to the memory via a memory data bus, generating an address for accessing the first block of the memory when outputting the first jump pattern, and outputting the second jump pattern when outputting the second jump pattern. An address for accessing a block is also generated, so that the first hop pattern and the second hop pattern respectively correspond to the first block and the second block of the memory. An address generator for generating an access for outputting a hopping pattern of a predetermined channel among an access unit configured to make a write and a hopping pattern already written in the first block or the second block of the memory when the frequency hopping of the system occurs; A selector for selectively selecting an address generated by a generator and an address generated by the access unit and outputting the generated address to the memory; and a jump pattern that is output from the memory in response to an address generated by the address from the selector being output. A hopping frequency generator, characterized by comprising a frequency synthesizer for synthesizing a frequency corresponding to the output frequency as a hopping frequency. The hopping frequency generator of claim 7, wherein each block of the memory stores a hopping pattern for each of a plurality of channels to be used in the system, and each hopping pattern comprises a series of hopping sequences. 9. The apparatus of claim 8, wherein the central processing unit comprises: a selection signal for controlling the operation of the selector, a hop clock indicating a frequency hopping time of the system, block designation information designating a block of the memory, Further comprising channel designation information for designating a hop pattern of any one of the jump patterns written in each block, and jump sequence designation information for designating a jump sequence within a predetermined range of the jump patterns of each channel. Hopping frequency generator. 10. The apparatus of claim 9, wherein the selector selects an address generated by the address generator when the frequency hopping the system in response to the selection signal and the hopping clock, and selects an address generated by the access unit for other times. A hopping frequency generator, characterized in that the selection. 10. The apparatus according to claim 9, wherein the address generator compares a counter, the jump sequence designation information provided from the central processing unit, and the value counted by the counter, and a value in the range indicated by the jump sequence designation information is assigned to the counter. A comparator for outputting a signal for loading the counter when counted by a channel, and a channel mode register for temporarily storing block designation information and channel designation information provided from the CPU, and a value counted by the counter. The hopping frequency generator, characterized in that the block designation information and the channel designation information temporarily stored in the channel mode register to output to the memory so that the value of the jump sequence of the jump pattern of the corresponding channel is output to the frequency synthesizer. . 12. The hopping frequency generator of claim 11, wherein the counter counts a magnitude value of an area in which a hopping pattern of each channel is stored among the areas of the memory. The frequency synthesizer of claim 12, wherein the frequency synthesizer comprises an adder for adding a jump pattern output from the memory and predetermined reference frequency data, and a bottle / serial converter for converting the output of the adder into serial data. The hopping frequency generator, characterized in that for synthesizing a frequency corresponding to the output of the serial converter and output as a hopping frequency. 14. The hopping frequency generator as claimed in any one of claims 7 to 13, wherein the memory comprises a RAM. A method of generating a hopping frequency in a frequency hopping / code division multiple access system comprising at least a memory, the method comprising: storing a series of hopping patterns consisting of hopping patterns assigned to each of a plurality of channels to be used in the system; A jump pattern storing step, a hop pattern output step of outputting a hopping pattern of a predetermined channel among the hopping patterns stored in the memory when the frequency hopping of the system, and a frequency corresponding to the output hopping pattern are synthesized to generate a hopping frequency A method characterized by consisting of the hopping frequency generation process. A method for generating a hopping frequency in a frequency hopping / code division multiple access system comprising at least a memory structured by a first block and a second block, the method comprising: hopping patterns assigned to each of a plurality of channels to be used in the system A first jump pattern storing process of storing a series of first jump patterns in a first block of the memory, and outputting a jump pattern of a predetermined channel among the jump patterns stored in the first block when the frequency hopping of the system occurs A process of generating a first hop frequency generated by synthesizing a frequency corresponding to a jump pattern generated as a second hop frequency, and a jump stored in the first block at the time of frequency hopping of the system when a change of the hop frequency is required in the system; Outputs the hopping pattern of a predetermined channel among the patterns, and changes the hopping frequency at the time between the frequency hopping points of the system. A second jump pattern storing process of storing a second jump pattern in a second block of the memory; and a jump pattern stored in the second block during a frequency hopping after the second jump pattern is stored in a second block of the memory. And a second hopping frequency generating process of generating a second hopping frequency by synthesizing a frequency corresponding to the output hopping pattern after outputting a hopping pattern of a predetermined channel.