KR0165429B1 - Apparatus for recording a digital signal - Google Patents

Abstract

The present invention provides an apparatus for converting an n-bit information word into an n + 1 bit channel word so as to have information corresponding to a tracking pilot tone, and selecting a channel word having a small error DSV and recording the same on a magnetic recording medium. By resetting the integrator in the precoder and the control signal generator every 1 bit information word or 2 (n + 1) bit information words, the timing problem can be solved and the operation speed can be improved.

Description

Digital signal recorder

FIG. 1A is a block diagram according to an embodiment of a conventional digital signal recording apparatus, FIG. 1B is a detailed block diagram of the precoder shown in FIG. 1, and FIG. 1C is a detail of the control signal generator shown in FIG. It is a block diagram.

2A to 2D are operation waveform diagrams of the respective parts in FIGS. 1A to 1C.

3 is a block diagram according to an embodiment of the digital signal recording apparatus according to the present invention.

4 is a detailed block diagram of the first and second aT precoder shown in FIG.

FIG. 5 is a detailed block diagram of the control signal generator shown in FIG.

FIG. 6 is a detailed block diagram of the integrator shown in FIG.

7A to 7G are operation timing diagrams of the parts shown in FIGS. 3 to 6.

* Explanation of symbols for main parts of the drawings

31: Bit addition part 32, 33: Precoder

34,35: delay 36: control signal generator

37: changeover switch 51,53: error DSV calculator

55: comparator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for converting an n + 1 bit channel word into an n + 1 bit channel word so as to have information corresponding to a tracking pilot tone capable of controlling a track, and recording the same on a magnetic recording medium. The present invention relates to a digital signal recording apparatus for resolving a timing problem by improving the precoder every n + 1 bit information word and improving the operation speed.

FIG. 1A is a block diagram according to an embodiment of a conventional digital signal recording apparatus, and includes a bit adder 11, first and second aT precoders 12 and 13, and first and second delayers 14; 15), the switching switch 16 and the control signal generator 17.

Referring to the operation according to the configuration of FIG. 1A, the bit appender 11 separately adds bits corresponding to 0 value and 1 value to the n-bit information word input, respectively, and the first and second aT precoder 12, In 13), the 0-part information word and the 1-part information word are converted into channel words, and then supplied to the input terminals of the switching switch 16 through the first and second delay units 14 and 15.

The control signal generator 17 is for generating a control signal Cs for generating a peak and a notch at a frequency component for which the 0 additional channel word and the 1 additional channel word are desired. The control signal generator 17 will be described in more detail with reference to FIG. 1C.

In FIG. 1C, zero additional channel words output from the first and third aT precoders (12 and 13 of FIG. 1) are output from the first and second error DSV calculators 21 and 23, respectively. The error DSV of DSV and DSV of one additional channel word and DSV of a signal having a desired frequency component are obtained, respectively. In other words, for each case of the 0 additional channel word and the 1 'additional channel word, the difference DSV of the peak frequency component f ₁ and the peak frequency component f ₁ is calculated by squared to obtain the error DSV from the peak frequency f ₁ . The error DSV with the notch frequency f ₂ is obtained by integrating the multiplied value of the channel word and the nod frequency component f ₂ by an integrator composed of an adder and a memory. The error DSV of the zero additional channel word, the DSV of one additional channel word, and the DSV of the signal having a desired frequency component are obtained by adding the error DSV of the peak frequency f ₁ and the error DSV of the notch frequency f ₂ . . The comparator 25 compares the error DSV of the 0 part channel word with the error DSV of the 1 part channel word to generate a selection control signal Cs for selecting a channel word having a small error DSV, thereby switching the switch (16 in FIG. 1). Supply with the selection signal of. Meanwhile, the update control signal Cu updates the integrators of the first and second error DSV calculators 21 and 23 and the first and second aT precoders (12 and 13 in FIG. 1). Here, the integrator consists of an adder and a memory.

Returning to FIG. 1A again, the selector switch 16 has 0 additional channel words and 1 additional outputs output from the first and second delayers 14 and 15 according to the control signal Cs supplied from the control signal generator 17. A channel word having a small error DSV is selected among the channel words, and the selected channel word is recorded on the magnetic recording medium through the channel.

Summarizing the operation of the conventional digital signal recording apparatus described above, the control signal generator calculates an error DSV of 0 additional channel words and an error DSV of 1 additional channel word every n + 1 bits, and compares the results. Generate a selection control signal and an updater control signal according to the method. The select control signal selects a channel word having a small error DSV among 0 additional channel words and 1 additional channel word, while the update control signal is fed back to update the integrator inside the precoder and the control signal generator. However, in this case, the control signal is delayed for a considerable time by the time required to calculate the error DSV for the last n + 1 bits from the first bit of the n + 1 bit channel word input to the control signal generator in the hardware implementation. . Therefore, the precoder must be updated before the first bit of the next n + 1 bit channel word is input to the precoder. The delayed output control signal inputs the first bit of the next n + 1 bit channel word to the precoder. There is a problem that the precoder cannot be updated until

Referring to the waveform diagram of FIG. 2, first, arbitrary input data are shown in FIG. 2a when n = 10 in FIG. The input data of FIG. 2A is added with 0's and 1's in the bit adding section 11. The output signal of the bit adding portion 11 is shown in FIG. 2B. The signal of FIG. 2b is input to the first and second precoders 12 and 13, and is precoded and output. Detailed block diagrams of the first and second precoders 12, 13 are shown in FIG. The output signals of the first and second precoders 12, 13 are shown in Figure 2c. The output signals of the first and second precoders 12 and 13 output a selection signal for selecting a more suitable signal among two channel words through the control signal generator 17.

The 0 additional channel word and the 1 additional channel word, which are output signals of the first and second precoders 12 and 13, are input to the control signal generator 17 of FIG. 1c and integrated in each integrator for n + 1 = 11 bits. The integrated value is squared in each square, and added to each of the adders for 0 additional channelwords and 1 additional channelword and input to the comparator 25.

The comparator 25 compares the two inputs and outputs the selection signals Cs and Cu to select the smaller one. Here, the selection signal is output with a considerable delay by the time calculated by the integrator, the squarer, the adder, and the comparator in the control signal generator 17. The selection signals Cs and Cu are shown in FIG. 2d. The selection signal is used to update the integrator in the control signal generator 17 of FIG. 1C and also to update the internal memory of the precoder 12, 13 of FIG. That is, the integrator and precoder of the control signal generator must be updated before the first bit of the next n + 1 bits is input.

However, when the first bit of the second n + 1 bit is input to the precoder, the 10th and 11th bits of the first n + 1 bit of FIG. 2c are stored in the memory of the precoder. The memory needs to be updated by the selection signal Cu, but the selection signal is delayed and output, and thus incorrect precoding is performed.

Accordingly, the present invention has been made to solve the above-mentioned problem, and converts the n-bit information word into an n + 1 bit channel word so as to have information corresponding to the tracking pilot tone, and selects a channel word having a small error DSV and selects a channel word. An apparatus for recording on a recording medium, which aims to provide a digital signal recording apparatus for resolving timing problems by improving the precoder every n + 1 bit information words and for improving the operation speed.

In order to achieve the above object, a digital signal recording apparatus according to the present invention comprises: a bit addition unit for adding 0 and 1 to an n-bit information word input; A precoder for resetting every n + 1 bits and for converting an n + 1 bit information word and an n'1 bit information word output from the bit adding part into a channel word, respectively; It is reset every n + 1 bit and error DSV for DSV of 0 additional n + 1 bit channel word output from the precoder and DSV of signal having a desired frequency component, and DSV of 1 + n bit channel word A control signal generator for generating a selection control signal for selecting a channel word having a small error DSV by comparing an error DSV with respect to a DSV of a signal having a desired frequency component; And a switch for selecting and outputting a channel word having a small error DSV among 0 additional n + 1 bit channel words and 1 additional n + 1 bit channel word output from the precoder according to a selection control signal output from the control signal generator. It comprises a means.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram according to an embodiment of a digital signal recording apparatus according to the present invention, and includes a bit adding unit 31 for adding a bit having 0 and 1 corresponding to a tracking pilot tone to an input n-bit information word. ) Is reset every n + 1 bit or every 2 (n + 1) bits, and the 0 word n + 1 bit information word and the 1 word n + 1 bit information word outputted from the bit part 31 are respectively channelwords. First and second aT precoders 32 and 33, and a zero-added n + 1 bit channel word and one-plus n + 1 bit channel output from the first and second aT precoder 34 and 35 First and second delayers 34 and 35 for delaying the word for a predetermined time period and reset every n + 1 or 2 (n + 1) bits, and the first and second aT precoders 32 and 33 Control signal generator 36 for generating a selection control signal Cs from the 0 additional n + 1 bit channel word and the 1 additional n + 1 bit channel word output from A channel word having a small error DSV is selected among the 0 additional n + 1 bit channel words and the 1 additional n + 1 bit channel word output from the first and second delay units 34 and 35, respectively, according to the tag control signal Cs. And a switching switch 37 for outputting.

FIG. 4 is a detailed block diagram of the first and second aT precoders 32 and 33 shown in FIG. 3, and when a is 2, one beta logic gate and two delay elements, that is, T flip-flops are shown. do.

FIG. 5 is a detailed block diagram of the control signal generator 36 shown in FIG. 3, wherein the first and second error DSVs each include one subtractor, two multipliers, three integrators, three absolute value calculators, and an adder. Comprising a calculator (51, 53) and a comparator (55).

FIG. 6 is a detailed block diagram of the integrator shown in FIG. 5, which consists of two adders, two D flip-flops, and one multiplexer.

7A to 7G are operation timing diagrams of the respective parts shown in FIGS. 3 to 6 when n is 10. FIG. 7A is an example of a signal input to the bit adder 31, and FIG. 7B is a first drawing. This is an example in which the first reset signal (Fig. 7d) is used as the output signal of the aT precoder 32 (where a = 2). FIG. 7C shows an example of using a first reset signal (FIG. 7d) as an output signal of the second aT precoder 33 (where a = 2), and FIG. 7D shows the first reset signal. Here, when FIG. 7B and FIG. 7C are compared, only odd bits are reversed with respect to 2 bits. FIG. 7E is an example in which a second reset signal (FIG. 7g) is used as an output signal of the first aT precoder 32 (where a = 2), and FIG. 7F is a second aT precoder 33 where a An example of using a second reset signal (Fig. 7g) as an output signal of = 2), and Fig. 7g shows a second reset signal. Here, comparing FIG. 7E and FIG. 7F, only odd bits are opposite to each other in the first n + 1 bit, and opposite to each other in the next n + 1 bit.

When the integrators in the first and second aT precoders 32 and 33 and the control signal generator 36 are reset using the first reset signal (Fig. 7d), the selection control signal Cs is every n + 1 bits. Selects a channel word every time and resets the integrators in the first and second aT precoders 32 and 33 and the control signal generator 36 using the second reset signal (Fig. 7g). Selects a channelword every 2 (n + 1) bits. Therefore, in the case of using the second reset signal (Fig. 7g) than in the case of using the first reset signal (Fig. 7d), the number of bits inverted among two channel words is n + 1/2 bits, This makes it possible to obtain spectra with better characteristic peaks and notches by enlarging the difference in error DSV.

The operation of one embodiment of the digital signal recording apparatus according to the present invention shown in FIGS. 3 to 7 will now be described.

In FIG. 3, the bit appender 31 adds 0 and 1 to the n-bit information word inputted and outputs the first and second aT precoders 32 and 33, respectively.

In the first and second aT precoders 32 and 33, the zero-added n + 1 bit information word and the one-added n + 1 bit information word output from the bit adder 31 are converted into channel words, and thus the first and second aT precoders 32 and 33 are converted into channel words. Outputs to the two delay units 34 and 35 and the control signal generator 36. As shown in FIG. 4, the first and second aT precoders 32 and 33 are the first and second aT precoders 32 that are delayed by 2T with an n + 1 bit information word input when a is 2. Exclusive logic sum is performed on the output signal of " Then, every n + 1 bits, the delay element, for example, the T flip-flop, is reset.

In the first and second delay units 34 and 35, a control signal generator generates 0 additional n + 1 bit channel words and 1 additional n + 1 bit channel word output from the first and second aT precoders 32 and 33. In (36), it delays by the time required to generate the selection control signal Cs and outputs it to the switching switch 37.

In the control signal generator 36, the error DSV and the one-added n for the DSV of the zero-added n + 1 bit channel word output from the first and second aT precoders 32 and 33 and the DSV of the signal having the desired frequency spectrum. A selection control signal for selecting a channel word having a small error DSV is generated by comparing the DSV of the +1 bit channel word with the error DSV of the signal having the desired frequency spectrum. The control signal generator 36 will be described in more detail with reference to FIGS. 5 and 6 as follows.

In FIG. 5, in the first and second error DSV calculators 51 and 53, the 0 part n + 1 bit channel word and the 1 part n + 1 bit channel word, which are input signals of the control signal generator 36, are respectively used. For the peak frequency error DSV from the difference between the zero part n + 1 bit channel word or the one part n + 1 bit channel word and the square wave of the specified frequency (here peak frequency f ₁ ) After integrating to find the absolute value of the integrated error DSV. On the other hand, for each case of the 0 additional n + 1 bit channel word and the 1 additional n + 1 bit channel word, which are the input signals of the control signal generator 36, the 0 additional n + 1 bit channel to make a notch on a specific frequency spectrum. The word or one part is integrated to find the notch frequency error DSV from the product of the sine and cosine of the n + 1 bit channel word and the specific frequency (here, peak frequency f ₂ ), and then the absolute value of the integrated error DSV is obtained. The comparator 55 adds the obtained peak frequency error DSV and the notch frequency error DSV for each of the 0 plus n + 1 bit channel words and the 1 plus n + 1 bit channel word, and then adds 0 plus n + 1 bit channel words. And Part 1 compare each error DSV of the n + 1 bit channel word. According to the comparison result, a selection control signal Cs for finally selecting a channel word having a small error DSV is supplied to the switching switch 37. At this time, the selection control signal Cs is output every n + 1 bits to select one of 0 additional n + 1 bit channel word and 1 additional n + 1 bit channel word, and to the integrator in the control signal generator 36. Feedback to update the integrator. For example, when the 0 + n bit channel word is selected by the selection control signal Cs, the value of the integrator in the second error DSV calculator 53 is the value of the integrator in the first error DSV calculator 51. Updated with a value. The integrators in the first and second error DSV calculators 51 and 53 will be described in more detail with reference to FIG.

In Fig. 6, the signal input to the integrator is integrated every n + 1 bits and reset by the reset signal. The value integrated for n + 1 bits is added to the previous integrated value and output. In the multiplexer (MUX), one of the output integral value and the output integral value of the relative path is selected by the selection control signal Cs and stored in a buffer, for example, a D flip-flop, and an integral value for the next n + 1 bits and a further value. Is printed out. At this time, the integrator shown in FIG. 6 can simplify the integrator hardware by performing integration only for n + 1 bits, and can speed up the computation. In addition, by separating the integral value for the current n + 1 bit and the previous integral value, it is possible to solve the timing problem due to the delayed feedback of the selection control signal (Cs). On the other hand, the signal input to the integrator is integrated every 2 (n + 1) bits, and by resetting by the reset signal, a spectrum having more characteristic peaks and notches can be obtained.

In the selector switch 37, 0 additional n + 1 bit channel words and 1 additional n output from the first and second delayers 34 and 35 according to the selection control signal Cs output from the control signal generator 36. A channel word having a small error DSV among +1 bit channel words is selected, and the selected channel word is recorded on the recording medium through the channel.

In another embodiment, the square wave of the peak frequency is subtracted from the channel word to make a dip around the peak, multiplied by the sine and cosine of the peak frequency, and then integrated. After adding the deep error DSV, the peak error DSV and the notch error DSV, the error DSVs of 0 part n + 1 bit channel words and 1 part n + 1 bit channel words are compared. According to the comparison result, a selection control signal Cs for finally selecting a channel word having a small error DSV is supplied to the switching switch 37.

As described above, the present invention provides an apparatus for converting an n-bit information word into an n + 1 bit channel word so as to have information corresponding to a tracking pilot tone, and selecting and recording a channel word having a small error DSV on a magnetic recording medium. In addition, by resetting the integrator in the precoder and the control signal generator every n + 1 bit information word or every 2 (n + 1) bit information words, the timing problem can be solved and the operation speed can be improved.

Claims (6)

A bit appender for adding 0 and 1 to the n-bit information word input; A precoder for resetting every n + 1 bits and for converting a 0-bit 2-bit information word and a 1-bit n + 1 bit information word outputted from the bit section respectively into channel words; It is reset every n + 1 bit and error DSV of DSV of 0 additional n + 1 bit channel word and DSV of signal having desired frequency component outputted from the precoder and DSV of 1 additional n + 1 bit channel word A control signal generator for generating a selection control signal for selecting a channel word having a small error DSV by comparing an error DSV with respect to a DSV of a signal having a desired frequency component; And a switch for selecting and outputting a channel word having a small error DSV among 0 additional n + 1 bit channel words and 1 additional n + 1 bit channel word output from the precoder according to a selection control signal output from the control signal generator. Digital signal recording apparatus comprising a means. 2. The control signal generator of claim 1, wherein the control signal generator integrates to obtain a peak frequency error DSV from a difference between a zero addition n + 1 bit channel word and a square wave of peak frequency to make peaks and notches on a particular frequency spectrum. The absolute value of the integrated error DSV is obtained, the zero-integration is integrated to find the notch frequency error DSV from the product of the sine and cosine of the n + 1 bit channel word and the notch frequency. A first error DSV calculator for adding the frequency error DSV and the notch frequency error DSV; In order to make peaks and notches on a specific frequency spectrum, one addition is integrated to find the peak frequency error DSV from the difference between the n + 1 bit channel word and the square wave of the peak frequency, and then the absolute value of the integrated error DSV is obtained. Integrate to find the notch frequency error DSV from the product of the additional n + 1 bit channel word and the sine and cosine of the notch frequency, and then obtain the absolute value of the integrated error DSV and add the peak frequency error DSV and the notch frequency error DSV. A second error DSV generator for; And selecting the channel word having the smallest error DSV by comparing the error DSVs of the 0 additional n + 1 bit channel words and the 1 additional n + 1 bit channel word respectively obtained by the first and second error DSV calculators. And a comparator for supplying a control signal to said switching means. 3. The digital signal recording apparatus according to claim 2, wherein the signal input for integrating in said first and second error DSV calculators is integrated every n + 1 bits and is reset by said reset signal. A bit appender for adding 0's and 1's to the n-bit information word input; A precoder which is reset every 2 (n + 1) bits and converts the 0 additional n + 1 bit information word and the 1 additional n + 1 bit information word output from the bit adding unit into a channel word, respectively; It is reset every 2 (n + 1) bits, and the error DSV and 1 part n + 1 bit channel word for DSV of n + 1 bit channel word and DSV of signal having desired frequency component outputted from the precoder A control signal generator for generating a selection control signal for selecting a channel word having a small error DSV by comparing an error DSV with respect to a DSV of a signal having a desired frequency component; And a switch for selecting and outputting a channel word having a small error DSV among 0 additional n + 1 bit channel words and 1 additional n + 1 bit channel word output from the precoder according to a selection control signal output from the control signal generator. Digital signal recording apparatus comprising a means. 5. The control signal generator of claim 4, wherein the control signal generator integrates to obtain a peak frequency error DSV from a difference between a zero addition n + 1 bit channel word and a square wave of peak frequency to make peaks and notches on a specific frequency spectrum. The absolute value of the integrated error DSV is obtained, the zero-integration is integrated to find the notch frequency error DSV from the product of the sine and cosine of the n + 1 bit channel word and the notch frequency. A first error DSV calculator for adding the frequency error DSV and the notch frequency error DSV; In order to make peaks and notches on a specific frequency spectrum, one part is integrated to find the peak frequency error DSV from the difference between the n + 1 bit channel word and the square wave of the peak frequency, and then the absolute value of the integrated error DSV is obtained. Integrate to find the notch frequency error DSV from the product of the additional n + 1 bit channel word and the sine and cosine of the notch frequency, and then obtain the absolute value of the integrated error DSV and add the peak frequency error DSV and the notch frequency error DSV. A second error DSV calculator for; And selecting a channel word having a small error DSV by comparing the error DSVs of the 0-part n + 1 bit channel words and the 1-part n + 1 bit channel words respectively obtained by the first and second error DSV calculators. And a comparator for supplying a control signal to said switching means. 6. The digital signal according to claim 5, wherein the signal input for integrating in the first and second error DSV calculators is integrated every 2 (n + 1) bits and reset by the reset signal. Logger.