KR0164811B1 - Semiconductor memory device - Google Patents

Abstract

A memory cell array having a plurality of memory cells connected to a pair of bit lines, a pair of data lines for transferring data and complementary data, and a pair of bit lines in the memory cell array and the data lines in response to activation of a column select line A semiconductor memory device having column select gates interconnecting pairs, the invention relates to a semiconductor memory device for controlling a data bus to minimize generation of peak-current when writing data. The semiconductor memory device includes a data input control signal generator for generating a data bus control clock and an input driver control signal which are sequentially delayed, a master clock for determining an input mode, and a data signal corresponding to a mode signal defining data input. A data bus controller connected to the first and second data lines of the line pairs and selectively precharging the levels of the first and second data lines according to the state of the data bus control signal, and activating the master clock; A data bus control signal generator for generating data bus control signals corresponding to the logic of the data to be recorded in response to the data bus and blocking the output of the data bus control signal in response to the activation of the data bus control clock; In response to an activation, the column select gate is driven to phase the data line pair. And a column selector connected to the existing bit line pair.

Description

Semiconductor memory device

1 is a data bus control circuit diagram of a conventional semiconductor memory device.

2 is a timing diagram for explaining the operation of FIG.

3 is a data bus control circuit diagram of a semiconductor memory device according to the present invention.

4 is a timing diagram for explaining the operation of FIG.

5 is a data bus control circuit diagram according to another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data bus control circuit of a semiconductor memory device, and more particularly to a semiconductor memory device having a function of controlling the data bus so as to minimize the generation of peak-current when writing data into a memory cell.

Conventional semiconductor memory devices have a data bus for inputting and outputting data to and from memory cells. In order to input (store) data into the memory cell or to output data stored in the memory cell, two data lines are provided. That is, in order to transfer the potential between the data and the complementary data, a pair of data lines consisting of at least two data lines are required.

A typical semiconductor memory device senses a relative difference between voltage levels of a pair of data busses, i.e., two data lines, and stores the data level logically as a high or low value in a memory cell or a potential value from the memory cell. The data corresponding to is outputted to the outside. Accordingly, when the data output operation from the memory cell or the data input from the outside to the memory cell is performed from the viewpoint of the data bus, it can be seen that a potential value of high or low is put on each of the pair of data lines. In particular, when inputting data from the outside, for example, a signal having a level opposite to the level value of the current data bus during an input operation, the data input time takes a long time and consumes the most power instantaneously. Prior art methods for solving this problem are equalization and precharge, which are common in the art.

1 shows a block diagram of a data bus control circuit according to the prior art. As is well known, a pair of data lines DL, DLB, that is, a data line pair DL / DLB, is required to input data into the memory cells in the memory cell array 12 shown in FIG. The data line pair DL / DLB is a pair of bit lines in the memory cell array 12 through the channels of the column select transistors 14 and 16 selected by activation of a column select line (CSL) selected by column address information. It is connected to each of BL / BLB. Therefore, in the conventional circuit having the configuration as shown in FIG. 1, the data on the data line pair DL / DLB is inputted into the memory cells in the memory cell array 12 by the column select gates 14 and 16 which are switched according to the column address information. You can see that the data is output in the opposite direction. In this case, the data line pair DL / DLB is precharged to improve the data output speed from the memory cell array 12 to the data line pair DL / DLB or the data input speed from the data line pair DL / DLB to the memory cell array 12. The equalizing circuit 18 is connected.

The precharge and equalization circuit 18 generates a data bus control signal generator for generating a data bus control signal in response to an output of an address transition detector (ATD) 26 for detecting a change in an address signal input from the outside. Controlled by the output of 27. For example, when an address is changed to access data, the ATD 26 detects it and generates an address change detection pulse having a predetermined duration, and the data bus control signal generator 27 precharges in response to the address change detection pulse. And the NMOS transistors 20, 22, 24 in the equalization circuit 18. By controlling the data bus as described above, the input and output speeds are improved by maintaining the level of the data signal on the data bus at the same and constant level while the input data inputted to or outputted from the memory cell array 12 is changed. . Such operation will be more clearly understood by reference to the operation timing chart described below.

FIG. 2 is a timing diagram for explaining the operation of FIG. 1, in which signal waveform diagrams relating to the control of the data bus are shown.

As described above, when the address changes, the ATD 26 detects this, generates an address change detection pulse IOPPi, and inputs it to the data bus control signal generator 27. In the address change detection pulse IOPPi, the previous column selection line CSL-P by the previous cycle is disabled (transition to low), and the valid column selection line CSL-V is enabled by a valid column address to which the next data is to be input. All EnMOS transistors 20, 22, and 24 in the precharge and equalization circuit 18 are turned on to precharge and equalize the data line pair DL / DLB until the corresponding column select gate (column select transistor) is turned on. At this time, the level of the precharge and equalized data line pair DL / DLB has a level of about Vcc-Vtn.

When the level of the address change detection pulse IOPPi goes low, the operation of the precharge and equalization circuit 18 is terminated. When the data input driver drive signal DTCP is enabled in a logic high state, a data input driver (not shown in FIG. 1) is enabled to transfer data from an external data input pad to the data line pair DL / DLB. Send it on. At this time, before the data input driver driving signal DTCP is enabled in a high state, the corresponding column select gates 14 and 16 are turned on by the effective column select line CSL-V so that an output operation of unwanted data is performed by the data line pair. This is the state transmitted on the DL / DLB. In this state, when the data input driver is driven by the enable of the data input driver driving signal DTCP, the level of the data line pair DL / DLB is inverted to perform an input operation. do. Therefore, the power level becomes unstable, that is, noise is generated in the data bus.

Such noise on the data bus is more serious in semiconductor memory devices that seek to improve high bandwidth and latency. This is because the number of data buses in the chip is increased to improve the bandwidth and latency of the memory device. In addition, in the technical field of the semiconductor memory device, for example, such a problem is more serious because the function of the block write, which is accessed simultaneously many cells at a time is performed. The improvement of the memory structure and the operation method naturally leads to a problem in that power consumption is increased, and thus, a stable supply of power becomes difficult, and accompanied by an increase in the peak current. This phenomenon naturally leads to a decrease in the performance of the device, such as an increase in cycle time (an example of an increase in column address strobe in the technical field) and a malfunction factor.

Accordingly, an object of the present invention is to prevent sudden power consumption by allocating power consumption in time by executing the sudden power consumption and input time delay effect during data write to a plurality of memory cells at the same time through the control of the data bus. The present invention provides a semiconductor memory device for improving the write time.

Another object of the present invention is to provide a semiconductor memory device which minimizes power consumption by previously transmitting a level of data to be written in a data input mode to a data bus line pair.

It is another object of the present invention to provide a semiconductor memory device which minimizes generation of instantaneous peak current generated during data writing by distributing data writing operation in time.

It is still another object of the present invention to provide a semiconductor memory device capable of reducing the writing time of data by dividing an input operation in a precharge period during cycle time.

Another object of the present invention is to provide a semiconductor memory device capable of reducing the size of a data input driver (write driver) and improving the speed of an internal signal of the input driver.

The present invention for achieving the above object is a memory cell array having a plurality of memory cells connected to a bit line pair, a data line pair for transferring data and complementary data, and the memory in response to the activation of a column select line A semiconductor memory device having a bit line pair in a cell array and a column select gate interconnecting the data line pairs, the semiconductor memory device comprising: a master clock determining an input mode in response to a mode signal defining an input of data and a data bus sequentially delayed; A data input control signal generator for generating a control clock and an input driver control signal and the first and second data lines of the data line pair, respectively, and the first and second data are connected according to the state of the data bus control signal. A data bus controller for selectively precharging the level of the line and activating the master clock; A data bus control signal generator for generating data bus control signals corresponding to the logic of the data to be recorded in response to the data bus and blocking the output of the data bus control signal in response to the activation of the data bus control clock; And a column selector for driving the column select gate in response to activation to connect the data line pair to the bit line pair.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings of the embodiments of the present invention, those having substantially the same configuration and function as those in the above-described drawings will use the same reference numerals.

FIG. 3 is a data bus control circuit diagram of the semiconductor memory device according to the present invention, in which a signal path for data bus control in a data input mode for transferring data to memory cells in a memory cell array 12 is shown.

4 is a timing diagram for explaining the operation of FIG.

First, the operation of FIG. 3 will be described in detail with reference to the operation timing diagram of FIG. 4.

Now, as shown in FIG. 4, when the mode signal DSFi (Define Specal Function) (where i denotes natural numbers 1,2 and 3) indicating the input mode of the semiconductor memory device is input, the NOA gate 38 in the input mode signal generator 36 A negative signal of the mode signal DSFi is generated to generate the master clock? WR in the input mode as shown in FIG. In this case, the signal of the mode signals DSF1, DSF2, and DSF3 are signals for determining the operation mode of the semiconductor memory device, and the operation mode is determined by a combination thereof. In the present invention, it is assumed that the three mode signals DSF1, DSF2, and DSF3 are all in the input mode.

In the branched device for positive setup time, the mode signals DSF1, DSF2, and DSF3 are signals that transition to a level at which a signal such as a column address of a memory cell is determined and operated as shown in FIG. 4, as shown in FIG. This signal is input faster than setup time by setup time. Therefore, when the mode signals DSF1, DSF2, and DSF3 are all low as described above, the NOA gate 32 activates and outputs the master clock ψWR to a logic high as shown in FIG.

The master clock ψ WR is supplied to one node of the NOA gate 42 through the inverter 40 and to the input node of the inverter 56 in the data bus control signal generator 52. Therefore, when the column address strobe signal CASB is activated low as shown in FIG. 4 and the full-scale input operation is started, the NOA gate 42 negatively joins the master clock ψWR and activates the logic high as shown in FIG. Generate and print At this time, the data bus control clock pdtcp is supplied to an input node of an inverter chain in which four inverters 44 to 50 are connected in series, and to the input node of Noah gate 58 in the data bus controller 52. The inverter chain is used as the data input driver control signal DTCP for driving the data input driver 94 by delaying the input data bus control clock pdtcp.

When the input mode signal generator 36 starts to operate as described above, the data selector 66 operates. The data selector 66 selects one of the data EDIN input to the external data input pad of the data input and the data IDIN of the internal register according to the mode of input operation, and selects the data WD to be recorded by the data in the data bus control signal generator 52. To the line. The data bus control signal generator 52 recognizes the value of the input data to be used in the input mode according to the information of the data WD output from the data selector 66. The data selector 66 is a signal for selecting whether to use the data IDIN of the internal register as the data WD to be written or to use the data EDIN input through the external data input buffer. It is made by a combination of external clocks to determine the type of. For example, when the selection signal? SEL is input to logic high, the transmission gate T1 is turned on to supply the external data EDIN through the external data input buffer to the input node of the inverter 64 in the data bus control signal generator 52 as data WD to be recorded. do. On the contrary, when the selection signal? SEL is input to a logic low, the transfer gate T1 is turned off and the transfer gate T2 is turned on so that the data IDIN of the internal register is selected and output as the data WD to be written.

On the other hand, the inverter 56 in the data bus control signal generator 52 which inputs the master clock? WR activated high as shown in FIG. 4 inverts the master clock? WR and supplies it to one node of the NOA gate 58. At this time, the initial input of the data bus control clock pdtcp supplied to another input node of the noah gate 58 is input as a low state, so that the noah gate 58 is activated until the data bus control clock pdtcp is activated high. The high signal is supplied to one node of the NAND gates 60 and 62. That is, the NAND gates 60, 62 are enabled. Each of the NAND gates 60 and 62 enabled by the above operation generates the data bus control signals IOPW and IOPWB corresponding to the data WD and the complementary data WDB to be written to another input node to the data bus controller 70. Supply.

Each of the data bus control signals IOPW and IOPWB is loaded on the data line pair DL / DLB before the value corresponding to the level of data to be recorded is loaded on the data line pair DL / DLB by the data input driver 94. . This operation is interrupted by activation of the data bus control clock pdtcp when the column address strobe signal CASB is enabled and starts full-scale operation, and is switched to full-scale input operation after the data bus control clock pdtcp is activated high. For example, if master clock ψWR is activated high while data WD on the input node of inverter 64 shown in FIG. 3 is logic high, the data bus control signal IOPW is high and IOPWB is low. Is output.

As described above, when the data bus control signals IOPW and IOPWB are output as high and low, the NMOS transistors 72 and 78 in the data bus control unit 70 are turned on, and the NMOS transistors 74 and 76 are turned off to turn off the data line pair DL / DLB. The first data line DL is precharged to the level of the power supply voltage Vcc, and the second data line DLB is precharged to the level of the ground voltage Vss. In other words, the potential levels of the data line pair DL / DLB are each shifted to a level in accordance with the logic of the data WD to be written before the data input driver 94 is operated. In the state of the data line pair DL / DLB, the data bus control clock pdtcp outputted from the input mode signal generator 36 is activated high so that the column select gates 14 and 16 are turned on, and the data input driver control signal DTCP is logically high. It lasts until the input driver is driven.

At this time, the NAND gate 84 in the column selector 80 which inputs the master clock? WR output from the input mode signal generator 36 in a logic high state by the inverter 82 and inputs the data control clock pdtcp outputs a signal of logic high. As a result, the inverter 90 outputs a signal transitioned to logic high as in the CSL-V of FIG. 4 to turn on the column select gates 14 and 16 connected to the bit line pair BL / BLB of the memory cell array 12. The column selector 80 operated as described above activates the column select line CSL in the input mode for inputting data into the memory cell array 12, and activates the column select line CSL by the input of the column address CAi in the output mode.

Therefore, the circuit configured as shown in FIG. 3 utilizes the time of equalizing with the precharge prior to the full-scale input operation and performs the input operation in advance so that the potential of the data line pair DL / DLB is fully developed as shown in FIG. By improving the cycle time of the input operation and temporal dispersion effect of instantaneous power consumption, instantaneous peak current and noise dispersion effect can be brought.

The above operation will be briefly described with reference to only the timing diagram of FIG. When the master clock ψ WR of the input mode is activated by input of the input mode signals DSF1, DSF2, DSF3, the master clock ψWR is connected to the memory cell array 12 and the data line pair DL / DLB by the column address signal CAi. Disable CSL to turn off column select gates 14 and 16 and at the same time start loading the information of data WD to be written in the input cycle onto the data line pair DL / DLB. This operation is completed before the column address strobe signal CASB is activated and the data input driver 94 is driven by the activation of the data bus control clock pdtcp to perform the data input operation. That is, the circuit shown in FIG. 3 has a primary input and input cycle in which the level of the data line pair DL / DLB in the circuit shown in FIG. 1 starts inputting to the data bus using the time of precharge and equalization. Since the second input is started and the input operation is started by the input driver, the input operation time can be reduced by performing the input operation twice.

In addition, the data input control circuit according to FIG. 3 allows the input to proceed slowly during the first input time by using a driver having a smaller size when the data is inputted first, distributing the current consumption as much as possible in time, thereby rapidly discharging the current. The change in the power supply level, that is, the noise phenomenon can be improved, and data can be input by the data input driver having a small size.

FIG. 5 is a data bus control circuit diagram according to another embodiment of the present invention, which shows a configuration in which the data bus control circuit shown in FIG. 3 is combined with the configuration of the data path in the output mode. That is, an example is shown in which the circuit of FIG. 3 is combined with the circuit of FIG. 1 used in the output mode so that data is actually input and output to the memory cell array in the semiconductor memory device.

In the output mode, the master clock? WR generated from the input mode signal generator 36 goes low, thereby disabling the input mode control paths of the column selector 80, the precharge and equalization control 92, and the data bus control 70. That is, the column selector 80 controls the column select line CSL by the input of the column address signal CAi to turn on / off the column select gates 14 and 16 to connect the bit line pair BL / BLB and the data line pair DL / DLB. The precharge and equalization circuit 92 controls the data bus by precharging and equalizing the level of the data line pair DL / DLB by the address change detection pulse IOPPi.

Contrary to the above, in the data input mode, the master clock? WR output from the data input mode signal generator 36 becomes high, so that the potential of the data line pair DL / DLB is not controlled by the address change detection pulse IOPPi, The data bus is controlled by the operation process as described above to perform the data input operation as described above.

As described above, in the data input mode, the present invention detects the logic state of data to be written to the memory cell before the column selection gate connected between the memory cell array and the data line pair is opened, and advances the potential of the data line pair in advance. In addition, the peak current may be reduced when data is input by driving the column select gate to transfer data to a memory cell by a data input driver. In addition, there is an advantage that the size of the data input driver can be reduced by performing data input operation by transferring data to the data line over two orders.

Claims (3)

A data line pair consisting of a memory cell array having a plurality of memory cells connected to a pair of bit lines, first and second data lines for transferring data and complementary data, and the bits in response to activation of a column select line A column select gate interconnecting the line pair and the data line pair, a predetermined input driver is connected to the data line pair, and the input driver operates by receiving an input driver activation signal to operate the first and second data. A semiconductor memory device characterized by an input operation for inputting a value corresponding to a logic value of data to be input to each line, comprising: a master clock for determining an input mode and a sequential delay in response to a mode signal defining input of data A data bus control clock and a column select gate control signal and separate the data from the input driver. When the data bus controller connected to the first and second data lines controlled by the switch control clock enables the delayed column selection gate control signal and the data bus control clock in response to the activation of the master clock determining the input mode. The column select gate is turned off by the column select gate control signal to disconnect the bit line pair from the data line pair, and a value corresponding to the logic value of the data to be input by the data bus control number corresponding to the signal of the data bus control clock. After input to the first and second data lines, respectively, the column selection gate is turned on by the input driver activation signal to connect the bit line pair and the data line pair, and the input by the input driver receiving the input driver activation signal is started. As a structure, the input operation is applied to two or more different input control signal generators and the input control unit. A semiconductor memory device, characterized in a structure. The data bus control signal of claim 1, wherein the semiconductor memory device selects at least one of external data and internal data supplied from an external data input buffer and an internal register as data to be written according to a logic state of a selection control signal. And a data selector for supplying the generator. 3. The data transmission control apparatus of claim 2, wherein the data selector comprises: a first transfer gate configured to transmit data from an external data input buffer to a data input node of the databus control signal generator in response to a first state of the data select control signal; And a second transfer gate configured to transfer output data of an internal register to a data input node of the data bus control signal generator in response to a second state of the data selection control signal.