KR0163542B1 - Bitline sensing and equalizing circuit for dram device - Google Patents

Abstract

According to the present invention, the voltage difference V _GS between the bit lines BL, / BL and the latch drive lines LA, / LA of the bit line sense amplifier circuits 40, 50, and 60 of the DRAM is equal to that of the MOS transistor. drain enters in action (Threshold) voltage (V _T) is more lowered the operating voltage of the memory operation to be to improve the problem because doemeuro the V _GS decreases slower detection speed, bit line sense amplifier circuit of the present invention P latch circuit 50 The bias line PBOOST for providing well bias to the PMOS transistors MP1 and MP2 of the PMOS transistors and the gate of each of the PMOS transistors MP1 and MP2 is disposed in the well guide ring, and is a bit line voltage during an initial sensing operation. Depletion-type MOS capacitors C10 and C20 and a control signal PLAPG are applied to the gate, and a source and a drain are connected between the power supply voltage Vcc and the bias line PBOOST to raise the control signal PLAPG. Depending on the level of PMOS transistor MP10 that is not conducting, another PMOS transistor MP20 having a gate grounded and a source and a drain connected between bias line PBOOST and driving line LA, and a predetermined control signal PLANG) or the supply voltage Vcc and the source and drain also include an NMOS transistor MN30 connected between the bias line PBOOT and the drive line LA, thereby initial sensing operation without increasing the layout. In the city, the fast sensing speed is obtained by making the voltage difference V _GS between the bit lines BL and / BL and the latch driving lines LA and / LA larger than before and lowering V _T. It becomes possible.

Description

Bit Line Sense / Equalization Circuit of DRAM Device

1 is a sense / equalization circuit of a conventional sense amplifier shared structure.

2 is a sense / equalization circuit of sense amplifier shared structure comprising a bit line sense amplifier in accordance with the present invention.

3 is an operation timing diagram of a bit line sense amplifier circuit in accordance with the present invention.

4 is a layout of a P latch region of a sense amplifier circuit according to the present invention.

5A is an operational waveform diagram of a conventional circuit.

5b is an operational waveform diagram of a circuit according to the present invention;

FIG. 6 is a graph showing the bit line detection speed according to the change of the power supply voltage Vcc.

* Explanation of symbols for main parts of the drawings

10, 10a: memory cell array 20, 20a: bit line precharge equalization circuit

30, 30a: separation gate circuit 40: N latch circuit

50: P latch circuit 60: transfer gate circuit

70: amplifier drive line precharge equalization circuit

TECHNICAL FIELD The present invention relates to DRAM devices, and more particularly, to a bit line sense / equalization circuit having a structure in which a bit line sense amplifier circuit is shared by neighboring memory cell arrays.

As semiconductor devices, especially DRAM devices, become more integrated, vertical design rules as well as horizontal design rules of devices are reduced, so that the operating voltage of the device is gradually lowered. This lowering of the operating voltage naturally leads to a lowering of the current driving capability of the transistors in the device, which is not an exception in the bit line sense amplifier circuit, so that its sensing ability is reduced, i.e., cell data sensing speed. This causes a problem of slowing down the sensing speed.

1 shows a sense / equalization circuit of a sense amplifier shared structure as an example of a conventional sense / equalization circuit mainly employed in highly integrated DRAM. In FIG. 1, reference numerals 10 and 10a denote adjacent memory cell arrays. In each memory cell array, one transistor (eg, MN1) connected to a point where word lines WLi, WLj, WLm, and WLn and bit lines BL ', / BL', BL, and / BL cross each other, One capacitor (eg C1) forms a memory cell. Referring to FIG. 1, this sensing / equalization circuit pre-registers a pair of bit lines (e.g. BL ', / BL') connected to each of the memory cell arrays 10, 10a to VBL (1/2 Vcc), respectively. Precharge equalization circuits 20, 20a for precharging and equalizing, bit line sense amplifier circuits 40, 50, 60, and bits on sense amplifier circuits 40, 50, 60 Line pairs BL and / BL (hereinafter referred to as 'first bit line pairs') and bit line pairs BL 'and / BL' toward memory cell arrays 10 and 10a (hereinafter referred to as 'second' Bit line pairs') are each composed of isolation gates 30, 30a for electrically connecting or electrically insulated. The bit line sense amplifier circuit includes an N latch circuit (also referred to as a 'sense amplifier') 40 consisting of MOS transistors MN15 and MN16, as shown in FIG. 1, and a PMOS transistor. P latch circuit (also referred to as a 'restore amplifier') 50 composed of the fields MP1 and MP2, and for transferring the amplified bit line signals to the data input / output lines IO and / IO. It consists of a transfer gate circuit 60. Although not shown in FIG. 1, the PMOS transistors MP1 and MP2 of the P latch circuit 50 are provided with Vcc as well-bais. In this circuit, the N latch drive line / LA, the P latch drive line LA, and the first and second bit line pairs BL and / BL (BL 'and / BL') are respectively VBL. (I.e. 1 / 2Vcc).

Next, an operation of the sensing / equalization circuit having the configuration as described above will be described. For simplicity, in FIG. 1, one word line WLi of the left memory cell array 10 is enabled. For example, let's take a look at the operation. First, the equalization signal PEQi and the split gate signals PISOi and PISOj are respectively 'high level' so that the bit line pair is precharged and equalized to VBL, and then the word line WLi is 'enabled'. If enabled, charge sharing is performed between the memory cells C1 and MN1 and the bit line BL '. As a result, a voltage difference ΔV _BL is generated between the bit lines BL ′ and / BL ′. Due to such a voltage difference ΔV _BL , the transistor MN6 of the N latch circuit 40 and the transistor MP2 of the P latch circuit are turned on. In this state, the N latch drive line (or sense node) / LA becomes 'low level (Vss)' and the P latch drive line LA becomes 'high level (Vcc)', and the bit line The voltage difference ΔV _BL between them becomes Vcc.

In order to operate the sense amplifier circuit as described above, the voltage difference V _GS between the bit lines BL and / BL and the latch driving lines LA and / LA on the amplifier side is the threshold voltage of the MOS transistor. (threshold voltage) (V _T ) or higher, but as the operating voltage of the memory device is lowered, the V _GS becomes smaller, so that the drain current (Id) of the MOS transistor becomes very small at the beginning of the sensing operation, so that the sensing speed is increased. Will slow down.

Accordingly, an object of the present invention is to improve a decrease in detection speed due to a decrease in operating voltage.

In order to achieve the above object, the present invention provides a bit line sense amplifier circuit having an N latch and a P latch connected between a first bit line pair BL and / BL, respectively, and in response to a predetermined first control signal. Sensing / equalizing a DRAM device having isolation means for electrically connecting or isolating the second bit line pair BL ', / BL' on the side of the memory cell array and the first bit line pair BL, / BL. A circuit comprising: switching means coupled between a bias line for well biasing of said PMOS transistors and a predetermined power supply voltage (e.g., Vcc) and responsive to a predetermined second control signal; Voltage boosting means connected between said bias line and said first bit line pair (BL, / BL), respectively, for raising a voltage level of said bit lines; The drive line and the bias when the voltage level of the bias line and the drive line becomes the power supply voltage level, respectively, connected between the bias line and the drive line of the P latch and the switching means is 'on'. And delay means for delaying the transfer of the power supply voltage level to the drive line to prevent the line from forward-biasing.

In the circuit of this aspect, the boosting means is disposed in a well guard-ring of the latch.

In the circuit of this aspect, the P latch includes a gate connected to a first bit line (eg, / BL) of the first bit line pair BL and / BL and the bit lines BL and / BL. A first PMOS transistor having a second bit line (eg, BL) and a drain and a source connected to the driving line, a gate connected to the second bit line, and a first bit line and the driving line, respectively. A second PMOS transistor having a drain and a source connected thereto; The boosting means includes a first MOS capacitor connected between the gate and the bias line of the first PMOS transistor, and a second MOS capacitor connected between the gate and the bias line of the second PMOS transistor. .

In the circuit of this aspect, the separating means is further configured so that the first bit line pair BL, / BL and the second bit line pair BL are in response to the second control signal being at a predetermined level at the beginning of the sensing operation. ', / BL') is electrically insulated.

For the present invention as described above, it will be described in detail based on the accompanying drawings.

Figure 2 shows a preferred embodiment of the sensing / equalization circuit according to the invention, in which reference numeral 70 is already well known for precharging and equalizing the latch drive lines LA, / LA. The drive line precharge equalization circuit is shown, and components having the same function as each component of the conventional sensing / equalization circuit described above are denoted by the same reference numerals and symbols as in FIG. Therefore, description of the same components as in the prior art will be omitted here in order to avoid duplication in the description. Referring to FIG. 2, the sense amplifier circuit according to the present exemplary embodiment includes a bias line PBOOST and PMOS transistors for providing well bias to the PMOS transistors MP1 and MP2 of the P latch circuit 50. Depletion-type MOS capacitors C10 and C20, which are connected between the gates of MP1 and MP2 and act as a boosting means for raising the bit line voltage during the initial sensing operation, and a predetermined control signal PLAPG are applied to the gate. And PMOS transistors MP10 connected to a source and a drain between a power supply voltage Vcc and the bias line PBOOST, and acting as a switch by being turned on or off depending on the level of the predetermined control signal PLAPG. Another PMOS transistor MP20 having a gate grounded and a source and a drain connected between the bias line PBOOST and the driving line LA, and a gate having a predetermined control signal PLANG or The power supply voltage Vcc is applied and the source and the drain also include NMOS transistors MN30 connected between the bias line PBOOST and the driving line LA. In the circuit of this embodiment, the transistors MP20 and MN30 have the bias line PBOOST and the drive line LA raised from the precharge level 1 / 2Vcc to the power supply voltage level Vcc by the switching PMOS transistor MP10. Acts as a delay means for delaying charge transfer from the bias line to the drive line to prevent forward bias on the bias line of N ⁺ and the drive line of P ⁺ .

In the circuit of this embodiment as such, the layout of the P latch circuit area is shown in FIG. In FIG. 4, reference numeral 1 denotes an N well region, 2 denotes a well guard ring of N ⁺ , and 3 denotes a P ⁺ region. Capacitors C10 and C20 are disposed in the well guard ring 2.

The operation timing of the sensing / equalization circuit according to the present embodiment having the above configuration is shown in FIG. Referring to Figures 2 and 3, the operating principle of this embodiment will be described. Prior to the detailed description, in order to simplify the description, the operation of the word line WLi of the left memory cell array 10 is enabled in FIG. 2 as an example.

First, as shown in (a) of FIG. 3, the equalization signal PEQi and the separation gate signal PISOj become 'low level' from 'high level', respectively, and as shown in (b) of FIG. 3, the word line signal WLi is When enabled, the first bit line pair BL, / BL and the second bit are at this time because the isolation gate signal PISOi is at a level higher than 1 / 2Vcc, so the isolation gate circuit 30 is in a conductive state. Charge distribution is made between the line pairs BL 'and / BL'. When this charge distribution is completed, as shown in (c) and (e) of FIG. 3, the isolation gate signal PISOi is 'low level', causing the isolation gate 20 to be conducting and the well bias signal PBOOST becomes It becomes Vcc from 1 / 2Vcc. As a result, the voltage of the first bit line pair BL and / BL is increased by the ratio of the parasitic capacitance of the bit line pair BL and / BL and the boosting capacitance C10 and C20. At the same time, the sensing operation is started by setting the voltage of the driving line / LA to the 'low level' and the voltage of the LA to the 'high level'. By the sensing operation, after the voltage of the first bit line pair BL and / BL is developed to a predetermined level, as shown in (c) of FIG. 3, the separation gate signal PSIOi is 'high level'. Charge distribution is performed between the first bit line pair and the second bit line pair BL 'and / BL'. In (c) of FIG. 3, a denotes an interval in which the bit line voltage is increased by the boosting capacitors C10 and C20 at the beginning of the sensing operation, and b denotes a first bit line pair and a second bit line pair ( The section in which charge distribution between BL 'and / BL') is made is shown.

As described above, according to the present invention, the voltage difference between the bit lines BL and / BL and the latch driving lines LA and / LA in the period a (ie, in the initial sensing operation) without increasing the layout. reference V _GS) is a conventional (first 5a even) more (see Fig claim 5b by increases relative to), and to ensure that well bias the transition from 1 / 2Vcc (conventionally, there was well bias is fixed to Vcc), V _T is By lowering, a faster detection speed can be obtained (see Fig. 6).

Claims (4)

A bit line sense amplifier circuit having N latches and P latches coupled between the first bit line pairs, a second bit line pair on the memory cell array side, and the first bit line pair in response to a predetermined first control signal. A sensing / equalization circuit of a DRAM device having isolation means for electrically connecting or isolating a circuit comprising: a connection between a bias line for well biasing the PMOS transistors and a predetermined power supply and responsive to a predetermined second control signal; Switching means; Boosting means connected between the bias line and the first bit line pair, respectively, for boosting a voltage level of the bit lines; Is connected between the bias line and the driving line of the P latch, and the driving line and the bias line when the voltage level of the bias line and the driving line respectively become a power supply voltage level by turning on the switching means; And delay means for delaying the transfer of said power supply voltage level to said drive line to prevent this forward biasing. 2. The bit line sensing / equalization circuit of claim 1, wherein the boosting means is disposed in a well guard ring of the latch. 3. The P latch of claim 2, wherein the P latch has a gate connected to a first bit line of the first bit line pair, a drain and a source connected to the second bit line and the driving line of the first bit line pair, respectively. A second PMOS transistor having a first PMOS transistor, a gate connected to the second bit line, a drain and a source connected to the first bit line and the driving line, respectively; The boosting means includes a first MOS capacitor connected between the gate and the bias line of the first PMOS transistor, and a second MOS capacitor connected between the gate and the bias line of the second PMOS transistor. And a bit line detection / equalization circuit of a DRAM device. 4. The method of claim 3, wherein the separating means electrically insulates the first bit line pair and the second bit line pair in response to the second control signal being at a predetermined level at the beginning of the sensing operation. A bit line sensing / equalization circuit of a DRAM device.