KR0163142B1 - Apparauts for testing clocks in a digital exchanger - Google Patents

Abstract

Synchronous clock test apparatus according to the present invention, the clock generator for generating a T1 / E1 reference clock for the test; A T1 / E1 clock distributor (12) for supplying a T1 / E1 clock generated by the T1 / E1 clock generator (11) to the test target synchronization device (1); A monitor clock generator 13 which receives a clock of the clock generator 11 and generates a monitor clock of a predetermined frequency; A clock to be measured receiver 14 which receives a clock to be measured from the test target synchronization device 1; A clock to be selected unit (15) which selects one clock for testing among clocks received from the clock to be measured unit (14); A clock monitor unit (16) for monitoring the selected clock under test by the monitor clock and outputting a result; A processor interface unit 18 which receives the output of the clock monitor unit 16 and temporarily stores the output of the clock monitor unit 16 and outputs the output to the processor 2 according to a request of the processor 2; The display unit 17 which displays the count result of the clock monitor unit 16 can automatically test the synchronization device.

Description

Synchronous clock automatic tester of digital electronic exchanger

1 is a block diagram showing the configuration of an automatic synchronous clock tester according to the present invention.

FIG. 2 is a detailed block diagram of the monitor clock generator shown in FIG.

3 is a first embodiment of the clock monitor unit shown in FIG.

4 is a second embodiment of the clock monitor unit shown in FIG.

FIG. 5 is a detailed block diagram of the processor interface unit shown in FIG.

* Explanation of symbols for the main parts of the drawings

1: Test target board 2: Processor device

10: test apparatus 11: T1 / E1 clock generator

12: T1 / E1 clock distribution unit 13: monitor clock generator

14: clock unit to be measured 15: clock unit to select

16: clock monitor 17: display

18 processor matching unit 21 phase comparator

22: voltage controlled oscillator 23: divider

24: monitor clock division and buffer section 31: clock reception and selection section

32: clock count unit 33,43,46: shift register

41: Frame pulse receiving and selecting section 42, 45: Frame pulse counting section

44: phase comparator 51: dual port RAM

52: processor matching unit

The present invention relates to a synchronous clock test apparatus for testing the clocks of synchronous boards in a digital electronic switch.

In general, it is essential to test and inspect the boards constituting the synchronous device in the production of the digital electronic exchanger, and the reduction of the test and inspection time leads to the reduction of the manufacturing cost.

By the way, the conventional synchronous clock test apparatus was to check (manual test) with an oscilloscope or frequency counter at the test point in order to test the corresponding board (manual test) was inconvenient, it takes a lot of time.

Accordingly, the present invention has been made in order to solve the above-mentioned problems, and the object of the present invention is to provide a synchronous clock test apparatus for a digital electronic switching device that can improve productivity and quality by automating the test of the synchronous clock. .

In order to achieve the above object, the test apparatus of the present invention includes a clock generator for generating a T1 / E1 reference clock for a test; A T1 / E1 clock divider for supplying a T1 / E1 clock generated by the clock generator to a test target synchronizer; A monitor clock generator which receives a clock of the clock generator and generates a monitor clock of a predetermined frequency; A clock to be measured receiver configured to receive a clock to be measured from the test target synchronizer; A clock to select unit for selecting one clock for a test from among clocks received from the clock to be measured unit; A clock monitor configured to compare the output of the monitor clock generator with a selected clock under test and output the result; A processor interface unit which receives the output of the clock monitor unit, temporarily stores the output of the clock monitor unit, and outputs the output to the processor as required; And a display unit for displaying the monitor result of the clock monitor unit.

That is, according to the present invention, after generating a T1 or E1 clock, which is a reference clock of a synchronizer, the apparatus is supplied to a device under test (ie, a PBA associated with a produced synchronization device), and then a plurality of measured clocks generated by the device under test are generated. The input is counted by the monitor clock, and the counted result is temporarily stored in the memory and then read by the processor or displayed on the display module.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

Synchronous clock test apparatus according to the present invention, as shown in Figure 1, the clock generator for generating a T1 / E1 reference clock for the test; A T1 / E1 clock distributor (12) for supplying the T1 / E1 clock generated by the T1 / E1 clock generator (11) to the test target synchronization device (1); A monitor clock generator 13 which receives a clock of the clock generator 11 and generates a monitor clock of a predetermined frequency; A clock to be measured receiver 14 which receives a clock to be measured from the test target synchronization device 1; A clock to be selected unit (15) which selects one clock for testing among clocks received from the clock to be measured unit (14); A clock monitor unit (16) for monitoring the selected clock under test by the monitor clock and outputting a result; A processor interface unit 18 which receives the output of the clock monitor unit 16 and temporarily stores the output of the clock monitor unit 16 and outputs the output to the processor 2 according to a request of the processor 2; The display unit 17 is configured to display the count result of the clock monitor unit 16.

In addition, the monitor clock generator 13 is an analog PLL circuit, a phase comparator 21 which receives the T1 / E1 clock from the T1 / E1 clock generator 11 and compares it with the returned monitor clock; A voltage controlled oscillator 22 which receives the output of the phase comparator 21 and generates a predetermined monitor clock; A divider 23 for dividing the monitor clock oscillated by the voltage controlled oscillator 22 and feeding it back to the phase comparator 23; And a clock clock divider and buffer section 24 for distributing and buffering the monitor clock of the voltage controlled oscillator 22.

In addition, according to an embodiment of the clock monitor unit 16, as shown in FIG. 3, a clock receiver and selector 31 which receives N clocks to be measured and selects one clock to be measured according to a selection signal is provided. ; A clock counting unit 32 for counting a clock selected by the clock receiving and selecting unit 31 by a monitor clock; A shift register 33 is configured to sequentially store and shift the counted result according to the clock to be measured. The clock counting unit 32 may be implemented as an EPLD.

In another embodiment of the clock monitor unit 16, as shown in FIG. 4, the FP reception unit receives N frame pulses FP and selects one frame pulse FP to select according to a selection signal. And a selector 41; An FP clock counting unit 42 for counting the FP clocks selected by the FP receiving and selecting unit 41; A shift register 43 for sequentially storing and shifting the frame pulse count result according to the frame pulse clock; A phase comparator 44 for receiving a frame pulse FP selected by the FP receiving and selecting unit 41 and a frame pulse FP of the other side to compare phases; An FP clock counting unit 45 for counting the output of the phase comparator 44; The shift register 46 is configured to sequentially store and shift the FP clock count result according to the FP clock. Here, the phase comparator 44 can be easily implemented as an oragate, and the clock count units 42 and 45 can be implemented using EPLD.

The processor matching unit 18 further includes a dual port RAM (DP RAM) 51 for storing test result data according to an address generated as a clock to be measured as shown in FIG. The dual port RAM 51 is configured with a processor matching circuit 52 for matching with the processor 2.

Next, the effect of this invention comprised as mentioned above is demonstrated.

In FIG. 1, the T1 / E1 clock generator 11 generates the T1 or E1 clock required by the synchronization device to be tested, and the generated clock is controlled by the clock divider 12 (see FIG. Is output to 1). That is, the synchronization device 1 under test receives T1 / E1 from the outside and generates various clocks and frame pulses FP required by the system. Therefore, the synchronization device 1 needs to be supplied from the test device 10.

The monitor clock generator 13 is an analog PLL circuit as shown in FIG. 2, and generates 65.536 MHz for counting the clock under measurement, and the generated monitor clock is supplied to T1 / E1 supplied to the device under test. As it is synchronized, the clock under test and the monitor clock are synchronized with each other.

In order to monitor the clock, the clock monitor unit 16 includes a clock reception and selection unit 31, a clock counting unit 32, and a shift register 33 as shown in FIG. After measuring the clock repeatedly x times, the result is stored in the shift register 33, and the FP reception and selection unit 41, FP clock, as shown in FIG. The counting section 42, the shift register 43, and the phase comparing section 44, and on one side, the FP clock count section 42 counts the frame pulse to be measured selected by the selection signal, and then shifts the shift register 43. The output pulse is output as A output, and the frame pulse inputted from the other side is inputted from the other side (the A side and the B side different from the A side currently being tested in the synchronization device duplexed to the A and B side). Phase ratio After phase comparison in the grant section 44, the count is counted in the FP clock count section 45 and output as the B output through the shift register 46. At this time, the abnormality of the redundant state can be confirmed by comparing the A output and the B output. For example, if the frame pulses on the A side and the B side are out of phase, the A output and the B output will be different.

As such, the result stored in the shift register of the clock monitor unit is stored in the RAM of the processor matching unit so that the processor may read the TD-BUS periodically or aperiodically, and the test result may be displayed on the LED display module.

As described above, according to the present invention, it is possible to check whether there is an abnormality by testing the clock of the synchronizing device, and in particular, it is possible to automatically test the clock generation performance of the synchronizing device, thereby reducing the manufacturing cost according to the test labor reduction. The test can be repeated several times, which has the effect of improving the reliability of the test.

Claims (7)

A clock generator 11 generating a T1 / E1 reference clock for a test; A T1 / E1 clock distributor (12) for supplying the T1 / E1 clock generated by the T1 / E1 clock generator (11) to the test target synchronization device (1); A monitor clock generator 13 which receives a clock of the clock generator 11 and generates a monitor clock of a predetermined frequency; A clock to be measured receiver 14 which receives a clock to be measured from the test target synchronization device 1; A clock to be selected unit (15) which selects one clock for testing among clocks received from the clock to be measured unit (14); A clock monitor unit (16) for monitoring the selected clock under test by the monitor clock and outputting a result; And a processor interface unit 18 which receives the output of the clock monitor unit 16, temporarily stores the output of the clock monitor unit 16, and outputs the output to the processor 2 according to a request of the processor 2. Test equipment. The apparatus of claim 1, wherein the test apparatus further comprises a display unit (17) for displaying a count result of the clock monitor unit (16). The monitor of claim 1, further comprising: a phase comparator (21) for receiving a T1 / E1 clock from a T1 / E1 clock generator (11) and comparing it with a returned monitor clock; A voltage controlled oscillator 22 which receives the output of the phase comparator 21 and generates a predetermined monitor clock; A divider 23 for dividing the monitor clock oscillated by the voltage controlled oscillator 22 and feeding it back to the phase comparator 23; And a clock clock frequency divider and buffer unit (24) for distributing and buffering the monitor clock of the voltage controlled oscillator (22). The clock monitoring unit (16) of claim 1, further comprising: a clock reception and selection unit (31) for receiving N clocks to be measured and selecting one clock to be measured according to a selection signal; A clock counting unit 32 for counting a clock selected by the clock receiving and selecting unit 31 by a monitor clock; A synchronous clock automatic test apparatus for a digital electronic switching system comprising a shift register (33) which sequentially stores and shifts a counted result according to a clock to be measured. The clock monitor unit (16) of claim 1, further comprising: an FP receiver and a selector (41) for receiving one frame pulse (FP) and selecting one frame pulse (FP) to be selected according to a selection signal; An FP clock counting unit 42 for counting the FP clocks selected by the FP receiving and selecting unit 41; A shift register 43 for sequentially storing and shifting the frame pulse count result according to the frame pulse clock; A phase comparator 44 for receiving a frame pulse FP selected by the FP receiving and selecting unit 41 and a frame pulse FP of the other side to compare phases; An FP clock counting unit 45 for counting the output of the phase comparator 44; A synchronous clock automatic test apparatus for a digital electronic switching system comprising a shift register (46) which sequentially stores and shifts an FP clock count result according to the FP clock. 6. The apparatus of claim 5, wherein the phase comparator (44) is implemented as an oragate. The processor of claim 1, wherein the processor matching unit (18) comprises: a dual port RAM (51) for storing test result data according to an address generated as a clock to be measured; And a processor matching circuit (52) for matching the dual port ram (51) with the processor (2).