KR0158966B1 - Apparatus for displaying kbps data in a tv with a pip ic - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a KBPS data display apparatus for a TV having a PIP circuit. The present invention relates to a television having a PIP circuit, having a KBPS circuit including a synchronous separator (20) and a data slicer (30). A KBPS decoder 50 which receives and decodes a synchronization signal and KBPS data and transmits KBPS data; A memory 90 that stores decoded KBPS data; A memory controller (100) for controlling the memory (90); A microcomputer 40 for controlling the KBPS decoder 50 and controlling the memory controller 100; A D / A converter 110 for converting the stored digital KBPS data into an analog signal; An encoder 120 for encoding a D / A converted signal; And a second switching circuit 10b that combines and outputs the encoded KBPS data signal when it is input, and the user can view the broadcast screen on the mother screen of the television and the KBPS data on the child screen. (Representative drawing: Figure 4)

Description

KBPS data display device in TV with PIP circuit

1 is a block diagram of a typical PIP circuit.

2 is an exemplary view showing a screen selected by various keys of the KBPS remote control.

3 is a block diagram of KBPS data on a horizontal synchronization signal inserted during a vertical retrace period.

4 is a block diagram of a KBPS data display apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

10a: first switching circuit 10b: second switching circuit

20: synchronous separator 30: data slicer

40: micom 50: KBPS decoder

60: Font ROM 70: Program ROM

80: DRAM 90: memory

100: memory controller 110: D / A converter

120: encoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a KBPS data display apparatus, and more particularly, to a KBPS data display apparatus configured to display a broadcast screen on a mother screen and to display KBPS data on a child screen in a television having a PIP circuit.

In general, a picture-in-picture (PIP, abbreviation PIP) displays a video signal corresponding to one channel among broadcast signals transmitted from two broadcasting stations on the mother screen on the screen, and corresponds to another channel. The video signal is displayed on the child screen on the screen.

FIG. 1 is a block diagram of a general PIP circuit, which converts an input video signal into a digital signal by the A / D converter 1 and stores it in the memory 2, and then stores the stored digital video signal in D / A. The converter 3 converts the analog signal back.

The video signal converted into the analog form is input to the switching circuit 4, and is then displayed on the monitor 5 in combination with other video signals input to the switching circuit 4.

On the other hand, the Korean Broadcasting Program System (abbreviated as 'KBPS') converts data for broadcast program reservation recording into a digital signal on a television signal to generate an arbitrary number of vertical blanking intervals. It is inserted into one line and transmitted, and the transmitted signal is demodulated at the receiving side to perform a scheduled recording and automatic time setting function of a broadcast program. The transmitted KBPS data includes Korean standard time information, daily program schedule operation information, program information currently being broadcast, information for updating in the case of a continuous program, and information for canceling / changing / adding / preceding.

Looking at the main features of KBPS, accurate scheduled recording can be performed, scheduled recording data can be preserved even after a power failure, time can be set automatically, as well as continuous program recording. In addition, it provides program detailed guide information, classifies broadcast programs, and reserve recording confirmation function.

In other words, the characteristics of KPBS is that even if a program is changed due to broadcasting station, each program is given a unique code, so when a code data comes in without a user changing time, only the program corresponding to the code data is recorded. Even in the event of a power failure, the reserved recording data is stored in the memory device, so that accurate reservation recording can be executed even after the power failure returns, and when the broadcast station standard time information is received, the current time information contained in the data packet can be automatically set in the VCR set. It is supposed to be.

2 is an exemplary view showing a screen selected by various keys of the KBPS remote control, the two screens of (a) are the initial KBPS screen appears when the K button is directly pressed on the KPBS remote control.

When the program data is received in the initial screen state of KBPS for about 5-6 minutes, the screen as shown in (b) appears, and when the △ and ▽ buttons are pressed in the KBPS remote control keys, the cursor moves up and down, and the ◁ and ▷ buttons Is used to change the date.

If you move the cursor to the program you want to record and press the setup button among the KBPS remote control keys, the screen like (c) will appear.If the program you want to record is a daily drama, you need to record the program every day. The number of recordings must be changed continuously.

If you want to cancel the reservation recording, press the 0 button. If you want to end the recording reservation, press the K button on the KBPS remote control key to switch to the broadcasting screen.

On the other hand, if you press the sort button of the KBPS remote control key while the screen as shown in (b) appears, the screen as shown in (d) appears, and if you press the number button by selecting the desired program number, the classification corresponding to the broadcast date Only programs by will appear.

For example, if one of the KBPS remote control keys is selected while the screen shown in (d) is displayed, only the news program is displayed for each time zone as shown in (e).

Also, the program with ⊙ mark on the screen as shown in (b) includes detailed guide data, move the cursor to the position of the program with ⊙ mark, and press the detailed guidance button among the KBPS remote control keys. Similarly, detailed guide information is displayed on the screen.

3 is a configuration diagram of KBPS data on a horizontal synchronization signal inserted during the vertical retrace period. The clock frequency of KBPS data is 5.7272 MHz, and the KBPS signal is composed of 36 words having 8 bits as one word.

Of the 36 words, the first and second words W1 and W2 are clock synchronization signals for synchronizing the clocks of the decoder, the third word W3 is a byte synchronization signal for data classification, and the fourth word ( W4) is a field counter for checking the continuity of the outgoing signals, and the rest are data headers W5 to W10 and data W11 to W36.

However, such a KBPS is generally embedded in a video set for pre-recording a program transmitted from a broadcasting station, and if the video having the KBPS circuit is not connected to the television, the television alone cannot see the KBPS data transmitted from the broadcasting station. There is a problem.

Accordingly, the present invention has been made to solve the above-mentioned problems, and the present invention is directed to a TV having a PIP circuit configured to display a broadcast screen on a mother screen of a television with a PIP circuit and display KBPS data on a child screen. The object is to provide a KBPS data display device.

In order to achieve the above object, the present invention includes a first switching circuit for selectively receiving a tuner video input or Y / C video input;

A synchronization separator for separating a composite synchronization signal, a horizontal synchronization signal, and a vertical synchronization signal from the video input signal of the first switching circuit;

A data slicer which receives the video input signal of the first switching circuit and the synchronous signal of the synchronous separator and outputs a shaped signal by comparing the level of the video input signal with a predetermined reference level;

A KBPS decoder configured to receive and decode KBPS data from the sync signal and the data slicer separated by the sync separator, and transmit KBPS data;

A program ROM providing program data to the KBPS decoder;

A font ROM providing a font of character data to the KBPS decoder; A memory for storing KBPS data decoded by the KBPS decoder;

A memory controller controlling the memory to input and output KBPS data stored in the memory;

A microcomputer that outputs a control signal to control the KBPS decoder and a memory control command to control the memory controller;

A D / A converter converting KBPS data stored in the memory into an analog signal;

An encoder for encoding the D / A converted signal; And

And a second switching circuit for combining and outputting the KBPS data signal encoded by the encoder.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

4 is a block diagram of a KBPS data display apparatus according to the present invention, comprising: a first switching circuit 10a for selectively receiving a tuner video input or a Y / C video input;

A sync separator 20 for separating a complex sync signal, a horizontal sync signal, and a vertical sync signal from the video input signal of the first switching circuit 10a; A data slicer (30) which receives the video input signal of the first switching circuit (10a) and the synchronization signal of the synchronization separator (20) and outputs a shaped signal by comparing the level of the video input signal with a predetermined reference level; A KBPS decoder (50) which receives and decodes the synchronous signal separated by the synchronous separator (20) and KBPS data from the data slicer (30) and transmits KBPS data; A program ROM (70) for providing program data to the KBPS decoder (50); A font ROM (60) for providing a font of character data to the KBPS decoder (50); A memory (90) for storing the KBPS data decoded by the KBPS decoder (50); A memory controller (100) for controlling the memory (90) to input and output KBPS data stored in the memory (90); A microcomputer 40 for outputting a control signal for controlling the KBPS decoder 50 and a memory control command for controlling the memory controller 100; A D / A converter 110 for converting KBPS data stored in the memory 90 into an analog signal; An encoder (120) for encoding the D / A converted signal; And a second switching circuit 10b which combines and outputs the KBPS data signals encoded by the encoder 120 when they are input.

Operation and effects of the present invention configured as described above are as follows.

Since the data must always be input to the KBPS decoder 50, when the power is turned off, the tuner video input is input from the first switching circuit 10a, and the Y / C video input through the video module is input when the power is turned on. .

The video input signal is sent to the synchronous separator 20 and the data slicer 30. The data slicer 30 compares the level of the transmission signal with a predetermined reference level and outputs a standardized signal, and the synchronous separator 20 The output is separated into a composite sync signal (Composite Sync), a horizontal sync signal (Horizontal Sync), a vertical sync signal (Vertical Sync).

The separated synchronization signal is sent to the data slicer 30 and the KBPS decoder 50 to synchronize synchronization of data slices and to synchronize OSD (On Screen Display).

The digital data sliced by the data slicer 30 is input to the KBPS decoder 50 to be decoded.

When the address is given to the program ROM 70 by the KBPS decoder 50, data corresponding to the address is transmitted to the KBPS decoder 50, while the font of the character data is obtained from the font ROM 60.

The KBPS enable signal, the clock signal, and the KBPS DATA IN signal are provided by the microcomputer 40. The KBPS decoder 50 recognizes the KBPS DATA IN signal and then outputs a digital KBPS video output. At this time, the digital video output data is converted into an analog signal through the D / A converter 90, and the final video output converted by the D / A converter 90 is output by the second switching circuit 10b.

The KBPS decoder 50 receives KBPS data from the data slicer 30 and decodes KBPS data according to the control signal of the microcomputer 40, and the decoded KBPS data is stored in the memory 90.

At this time, the memory controller 100 controls the input / output of the KBPS data stored in the memory 90 according to the memory control command output from the microcomputer 40 and the synchronization signal separated from the synchronization separator 20.

As a result, the D / A converted KBPS data signal is encoded by the encoder 120. At this time, the signals output from the second switching circuit 10b display the broadcast screen on the mother screen of the television using the PIP function, It will display KBPS data.

As described above, the present invention is advantageous in that it is convenient to allow a user to simultaneously view a broadcast screen and KBPS data on one screen of a television by providing a KBPS data display apparatus in a television having a PIP circuit.

Claims (1)

A first switching circuit 10a for selectively receiving a tuner video input or a Y / C video input; A sync separator 20 for separating a complex sync signal, a horizontal sync signal, and a vertical sync signal from the video input signal of the first switching circuit 10a; A data slicer (30) which receives the video input signal of the first switching circuit (10a) and the synchronization signal of the synchronization separator (20) and outputs a shaped signal by comparing the level of the video input signal with a predetermined reference level; A KBPS decoder (50) for receiving and decoding the synchronous signal separated by the synchronous separator (20) and KBPS data from the data slicer (30) and transmitting KBPS data; A program ROM (70) for providing program data to the KBPS decoder (50); A font ROM (60) for providing a font of character data to the KBPS decoder (50); A memory (90) for storing the KBPS data decoded by the KBPS decoder (50); A memory controller (100) for controlling the memory (90) to input and output KBPS data stored in the memory (90); A microcomputer 40 for outputting a control signal for controlling the KBPS decoder 50 and a memory control command for controlling the memory controller 100; A D / A converter 110 for converting KBPS data stored in the memory 90 into an analog signal; An encoder (120) for encoding the D / A converted signal; And a second switching circuit (10b) for combining and outputting the combined KBPS data signal encoded by the encoder (120).