KR0158942B1 - Ipc control logic of vme bus system - Google Patents

Abstract

The present invention relates to a means for performing an IP process in a bus company such as a computer system. In the related art, a method of generating and processing a plurality of interrupts and a means using a semaphore and polling method are known. In this type, the former requires a large number of interrupt actions, thereby degrading the system processing efficiency. In the latter case, it is difficult to guarantee isochronous processing because the execution is performed by polling.

The present invention provides an address selector switch 12 for selecting a lower address for an IP from an IP region 19a allocated to a shared memory 19, and the address selector switch so as to solve such a conventional problem. 12), if the contents set by this switch 12 and the contents of the address bus side coincide with each other, the address decoder provides VAM address match (VAM) signal to the local interrupter 15 side. (13), a local interrupter (15) for receiving the signals provided from the address decoder (13) and the sixteen mode decoder (14) and providing an interrupt clear (INTC) signal to the local processor (16) side of the system; When the bus and the local bus request access to the shared memory 19, the local mediator 18 arbitrates and processes the local bus and provides the INTC signal to the local interrupter 15 by receiving the local bus. And that the interrupt logic 17 to stop, V M, consisting of a structure, including the local processor 16, such as the system control is integral to provide the IP when the control logic of the bus system.

Description

IP Control Logic of VMB System

1 is a circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

11: VMB 2: Address selection switch

13: Address decoder 14,16: Mode decoder

15: local interrupter 16: local processor

17: Interrupt recognition logic 18: Local mediator

19: shared memory

The present invention relates to Inter Processor Communication (VME) of Versa Moudule Europe Bus (VME) system, which in particular allocates a portion of shared memory for IP arbitration in such a system to reduce the number of system interrupts. The present invention relates to an IP control logic that can ensure a good processing efficiency of such a system.

There are two known types of techniques for performing IP Fish in these systems.

One of them is to use the interrupts provided by VMBus. This means that when the board wanting IP is interrupted by a specific board, the board receiving the interrupt executes the interrupt service routine to execute the VMB. It is the type that executes IP board and interrupted board on this bus.

In the above means, the board which wants the IP first writes data to be transmitted through the IP in its memory, and also stores information indicating the start address and size of the data in the memory.

Afterwards, the VPC interrupt is used to execute the IP to another board.

The board receiving this interrupt reads a specific memory area (predefined) of the board that generated the interrupt, recognizes the start address and size of the data, and reads the data into the memory in its board. The board that has finished reading the data is the board that started the IP, and interrupts the bus to inform this fact.

On the other hand, another type of method is to configure the semaphore in a specific memory area in a board to perform an IP, which is performed by the processor periodically polling a specific area of the memory to set a specific bit, and then through the corresponding processing means. It is in the form of performing a poem.

That is, here, a semaphore is formed in a specific memory area in each board, and the specific area is divided into a transmit memory area and a receive memory area for an IP, and a board that wants an IP reads the semaphore of the other board and receives the receiving memory of the other board. It determines whether the area is available, and if it is available, sets the semaphore by writing the IP data and the size of the data in the receiving memory area of the partner board.

On the other hand, a board receiving data periodically checks through a semaphore whether data is received from another board in its receiving memory. If the semaphore is set, it reads data from the depth memory and stores it in its local memory, and then clears the received semaphore and informs other boards on VMB that the received memory is empty.

However, in the prior art, the following problems are not preferred.

In other words, the former technique causes many buses to interrupt when performing the IP, which causes bus arbitration, resulting in a decrease in system processing efficiency.

In addition, in the latter case, it is difficult to solve the problem of slowing data transmission because the processor needs to process polling IP requests one by one.

An object of the present invention is to provide an IP control logic developed to improve the problems of the prior art as described above.

In particular, the present invention relates to an IP region unit in which a specific area is allocated from a shared memory region accessible to other boards on a bus, and a local interrupt is generated when another board approaches the IP region region. It is characterized by an IP control logic that is related to the local interrupt portion provided to the side.

Hereinafter, by referring to this in more detail with the accompanying drawings will be understood more specific features of the present invention.

That is, the accompanying drawings show a V-bus 11 of the system equipped with the IP control logic according to the present invention.

Here, the address selection switch 12 which selects a lower address for the IP from the IP area 19a allocated to the shared memory 19 and the address selection switch 12 are connected to this switch 12. If the contents set by the VMS and the contents of the address bus side coincide, the VME receives the VME Address Match (VAM) signal to the local interrupter 15 and the VME control bus. The address 16 mode decoder 14, which sends an A16M (Address 16 mode Match) signal to the local interrupter 5 when the VME address 16 mode is recognized and matched, the address decoder 13 and the 16 mode decoder 14 The local interrupter 15, which receives the signal provided from the system, provides the interrupt clear (INTC) signal to the local processor 16 side of the system, and the VMS and the local bus request access to the shared memory 19. A local mediator 18 to arbitrate this process, an interrupt acknowledgment logic 17 to stop the INTC signal by receiving an local bus and supplying an INTC signal to the local interrupter 15, and a local processor for system control. 16) It consists of a structure including the back integrally.

The present invention of such a configuration is as follows.

When a write operation is performed on the V bus 11 in the address 16 mode from another board on the V bus, the address value for accessing the shared memory 19 appears on the V bus.

This address is compared with a value set in advance on the address selection switch 12 side, and if it matches, the address decoder 13 generates a VAM signal.

At this time, the 16 mode decoder 14 side of the address receives the control signal of the bare bus and checks whether the access from the V bus is the address 16 mode, and in the case of the 16 mode, the A16M (Address 16 Mode) signal. Generates.

The local mediator 18 arbitrates the conditions of use of the processor 16 accessing the shared memory 19 or another board on the V bus, and only one side of the local mediator 18 can use the shared memory 19 at a specific time. It is.

Here, the VAM, A16M signal and the local bus (16) receive the local bus (LB) signal that the shared memory 19 can access, so if another board on the bus uses the shared memory 19, the VG ( VME Bus Grant) signal and LG signal when local processor 16 side is used.

On the other hand, the VAM and A16M signals inputted to the local interrupter 15 are negated when the access from the bus to the shared memory 19 is terminated.

At this time, the local interrupter 15 generates the INTR signal to the local processor 16, and the local processor 16 receiving the signal reads the shared memory 19 through the LB.

At this time, the interrupt acknowledgment logic 17 outputs an INTC (Interrupt Clear) signal to the local interrupt 15, and the local interrupt 15 receiving the INTC signal outputs the INTR (Interrupt Request) signal to the local processor 16 side. To get rid of everything.

The present invention is a problem that the means for performing the IP on the bus bus V as the conventional way to interrupt the significantly increased number of interrupts when performing the interrupt or in the case of the semaphore method polling means Since the checking must be done, it is possible to actively solve the problems that the IP isochronism cannot be guaranteed.

In addition, the board that wants the IPP can read the lower 64 bytes of the shared memory that the other board has put on the VB bus to understand the contents of the IPP. This read operation also has the advantage of automatically terminating the local interrupt. In this way, it is possible to provide convenience of use in software of such a function.

Claims (2)

In a VME bus system having a means for performing an IP on a bus, the VME has an IP area 19a which allocates a specific area from a shared memory area accessible to other boards on the bus. When the shared memory 19 and the other IP or local processor 16 approaches the IP region 19a, a local interrupt is generated, which generates a local interrupt and processes an IP function. IP Control Logic of VMB system, characterized in that. The IP control logic includes an address select switch 12 for selecting a lower address for performing an IP in the IP region 19a allocated to the shared memory 19, followed by the address select switch 12; When the contents set by the switch 12 and the contents of the address bus side coincide with each other, the address decoder 13 which provides the VME Address Match (VAM) signal to the local interrupter 15 side; An address 16 mode decoder 14, which sends an A16M signal to the local interrupter 5 when the VME control bus receives the VME address 16 mode and is matched, and the address decoder 13 and the 16 mode decoder 14 The local interrupter 15, which receives the signal provided from the CDMA) and provides the interrupt clear (INTC) signal to the local processor 16 side of the system, and the VMBus and the localbus require access to the shared memory 19. A local mediator 18 for arbitration when obtaining the data, an interrupt acknowledgment logic 17 for stopping the INTC signal by receiving an local bus and providing an INTC signal to the local interrupter 15, and a local processor for system control. 16) IP Fish control logic of VMB system, characterized in that the configuration including a single body.