KR0157479B1 - Circuit for extracting header from the bit stream of mpeg-2 - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

A technology related to a video processing system.

2. The technical problem to be solved by the invention

To easily extract various header data from the compressed bit stream by any image compression algorithm.

3. Summary of Solution to Invention

In a moving picture processing system that generates a compressed bit stream by performing an arbitrary image compression algorithm, the bit stream data is shifted and written by one bit in synchronization with the shift clock to generate sequence-extension, sequence-display-extension, and sequence- 32-bit shifter to extract bit syntax of scalable-extension and geo-header, and start to detect start code of each of the sequence-extension, sequence-display-extension, sequence-scalable-extension, and geo-header A code enabler, a shift enable signal generator that generates a shift enable signal for extracting a corresponding syntax based on the detected start code, and a bit that is reset by the start code detection signal and corresponding to a syntax type The MPEG bit stream to generate as many shift enable signals as possible. It consists of a counter for counting and a plurality of shift register files, and a shift register group for shifting each shift register file by the required bits from a bit stream using enable pulses generated by the shift enable signal generator. do.

4. Important uses of the invention

Used to extract various header data from the compressed bit stream by any image compression algorithm.

Description

Circuit for extracting header data from MPEG-2 bit stream

1 is a block diagram of a header data extraction circuit according to an embodiment of the present invention.

2 is a block diagram of an embodiment of a start code detector of FIG.

3a-e are operational waveform diagrams in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

10: 32-bit shifter 20: Shift register group

30: start code detector 40: shift enable signal generator

50: counter 60: comparator

The present invention relates to a circuit for extracting various header data from a bit stream compressed by an arbitrary video compression algorithm in a moving picture processing system.

There are many video compression methods for HD-TV or DBS (Direct Broadcasting Satellite). One of them, the Moving Picture Expert Group (MPEG), is an international standard for compressing and encoding digital video, which is a key technique in the multimedia environment. MPEG can be broadly classified into MPEG1 and MPEG2. MPEG1 was created with the goal of viewing 70 minutes of video on a compact disk-sized data storage device. Generally, the screen size is limited to 352 × 240 or less (SIF: Source Input Format) and the bit rate is about 1.5Mbps. Although defined, the actual image quality surpasses the general analog VTR by digitally processing the entire video. MPEG2 is a standard that is intended for use in digital broadcasting (terrestrial, satellite), high-definition video telephony, and video conferencing. . After all, MPEG1 is a video compression algorithm capable of VHS video quality, but MPEG2 is a video compression algorithm capable of VHS video quality as well as HD-TV quality.

An MPEG bit stream is an image signal encoded in the form of bits. That is, the video signal output from the camera is encoded using a compression algorithm established by MPEG.

The MPEG2 bit stream includes a sequence-header, a sequence-extension, a sequence-display-extension, a sequence-scalable-extension, and a group of picture (GOP). It consists of a header and a picture-header.

The sequence-header is a 32-bit sequence-header code with hexa 00000B3, 12 bits of horizontal size, 12 bits of vertical size, and 4 bits of information-ratio-information. It consists of a 4-bit frame rate code. Of course, the remaining sequence-extensions, sequence-display-extensions, sequence-scalable-extensions, geopi-headers, etc. are composed of similar syntax.

It is an object of the present invention to provide a circuit for extracting various header data from a bit stream compressed by an arbitrary image compression algorithm.

In order to achieve the above object, the present invention provides a video processing system that generates a compressed bit stream by performing an arbitrary video compression algorithm, and shifts the MPEG2 bit stream data by one bit in synchronization with a shift clock to sequence- 32-bit shifter for extracting bit syntax of extension, sequence-display-extension, sequence-scalable-extension, geopi-header, and sequence-extension, sequence-display-extension, sequence-scalable-extension, geofi- A start code detector for detecting a start code of each header, a shift enable signal generator for generating a shift enable signal for extracting a corresponding syntax based on the detected start code, and the start code detection signal The shift enable signal corresponding to the corresponding bit according to the syntax type is reset. A counter for counting the MPEG2 bit stream to be generated, and a plurality of register files and using as an enable pulse generated by the shift enable signal generator, as many bits as necessary from the MPEG2 bit stream And a group of register files for shifting each register file.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In addition, in the following description, many specific details such as components of specific circuits, number of bits of a specific code, etc. are shown, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. It will be apparent to those skilled in the art. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

1 is a diagram showing the configuration of a header data extraction circuit according to an embodiment of the present invention.

The 32-bit shifter 10 shifts the MPEG2 bit stream data Sdata by one bit in synchronization with the shift clock Sclk as shown in FIG. 3A, so that the sequence-extension, sequence-display-extension, Allows you to extract the bit syntax of sequence-scalable-extensions and geopi-headers.

However, each start code is detected before the corresponding syntax is detected. In other words, it is necessary to first extract the start code SCo as shown in FIG. 3B to determine which part of the syntax. For example, the start code of the sequence extension is hexa 00000B3, and the start code of the sequence display extension is hexa 00001B5. This start code is detected by the start code detection unit 30.

2 is a diagram illustrating an embodiment of the start code detector 30.

As shown, the start code detector 30 may be implemented as a comparator 60. The comparator 60 may include 32-bit data output from the following first to fifth start codes SC1 to SC5 and a 32-bit shifter 10. Compares with and outputs the start code detection signal SCo. The first to fifth start codes SC1 to SC5 are referred to when extracting one of the following five syntaxes from the MPEG2 bit stream, and are syntax start codes pre-assigned for each syntax. The five syntaxes are sequence-header, sequence-extension, sequence-display-extension, sequence-scalable-extension, and geo-header.

Referring to FIG. 1 again, the start code detection signal SCo is input to the shift enable signal generator 40 having a finite state machine (FSM) type as a reference to start extraction of the syntax. The shift enable signal generator 40 determines an operation state according to how many bits are input from the start code detection signal SCo. For example, in the case of a sequence header, the bits as described above are input to the stream after the 32-bit start code. Therefore, you can decide how many bits to extract from that register file.

The counter 50 is reset by the start code detection signal SCo as shown in FIG. 3C, and then generates an enable pulse in accordance with the syntax form to generate the shift enable signal by the corresponding bit. .

In the shift register group 20, the enable register generated by the shift enable signal generator 40 may be used to shift the shift register file by the required bits from the bit stream.

FIG. 3D is a shift enable signal waveform of a shift register file having a horizontal size of a sequence-header, and FIG. 3E is a shift enable signal waveform of a shift register file having a vertical size of a sequence-header.

As described above, the present invention has an advantage of efficiently extracting header data from a transmitted bit stream.

Claims (5)

A moving picture processing system for generating a compressed bit stream by performing an arbitrary video compression algorithm, comprising: shifting means for shifting the bit stream by one bit in synchronization with a shift clock, and starting code of each syntax from the bit stream. A shift register group consisting of a detection means for detection, a plurality of register files, receiving bits output from said shift means, and breaking them in each syntax unit under predetermined control, and counting said start code And enable means for detecting a corresponding syntax and generating a shift enable signal so that the syntax can be stored in a corresponding register file of the shift register group. The start code of claim 1, wherein the detection means stores 32-bit data output from the shift means in sequence-header, sequence-extension, sequence-display-extension, sequence-scalable-extension, and geopi-header. And a comparator for outputting a start code detection signal in comparison with. The method of claim 1, wherein the shift means is a 32-bit shifter for extracting a bit syntax of a sequence-extension, a sequence-display-extension, a sequence-scalable-extension, and a geo-header from an MPEG2 bit stream. Header data extraction circuit. In a moving picture processing system that generates a compressed bit stream by performing an arbitrary video compression algorithm, the sequence-extension, sequence-display-extension, and sequence are written by shifting the MPEG2 bit stream data by one bit in synchronization with the shift clock. A 32-bit shifter for extracting the bit syntax of the scalable-extend and geo-header, and for detecting the start code of each of the sequence-extension, the sequence-display-extension, the sequence-scalable-extension, and the geo-header The start code detection unit, a shift enable signal generation unit for generating a shift enable signal for extracting a corresponding syntax based on the detected start code, and a reset enable signal generation unit, are reset by the start code detection signal and correspond to a syntax type. The MPEG2 bit switch to generate a shift enable signal by a bit amount. Each shift register file includes a counter for counting a rim and a plurality of shift register files, and each bit is required as much as necessary bits from the MPEG2 bit stream by using a pulse-type enable signal generated by the shift enable signal generator. And a shift register group shifted to the header data extracting circuit. 5. The header data extraction circuit according to claim 4, wherein the start code detection unit comprises a comparator for comparing the 32-bit data output from the shift means with the start code of each syntax.