KR0157391B1 - Atm switch using binary grouping network - Google Patents

Abstract

The present invention relates to a scalable high-capacity ATM switch structure using a small-capacity unit switch, and more particularly, to an ATM switch using a binary grouping network for grouping input cells through binary radix alignment in a binary grouping network.

In general, ATM switches are configured to pre-classify the cells to be input to the unit switch by placing the grouping network in front of the forwarding network. This configuration eliminates the internal blocking in the multistage interconnect only structure and ensures cell ordering. It becomes complicated and becomes a problem.

Accordingly, the present invention reduces the complexity of hardware by performing binary radix sorting, which repeats binary grouping, in a binary grouping network, thereby facilitating the configuration of a large-capacity switch having hundreds and thousands of input / output ports, thereby improving the performance of an ATM switch. Let's do it.

Description

ATM Switch Using Binary Grouping Network

1 is a structure of an ATM switch using a general grouping network.

2 is an embodiment of the operation of the grouping network in FIG.

3 is a structure of an ATM switch using a binary grouping network of the present invention.

4 is the structure of the binary concentrator in FIG.

5 is an embodiment of the operation of the grouping network in FIG.

FIG. 6 is a graph comparing the number of grid points of switches according to a general grouping network and a switch structure according to the binary grouping network of the present invention.

* Explanation of symbols for main parts of the drawings

N: Number of I / O of total ATM switch L: Number of cells per group

LM: Number of inputs of unit switch module M: Number of outputs of unit switch module

SM: Unit Switch Module BC: Binary Concentrator

S: unit switch element

The present invention relates to an extensible large capacity ATM (Asynchronous Transfer Mode) switch structure using a small capacity unit switch. The present invention relates to an input cell through binary radix sorting in a binary grouping network. The present invention relates to an ATM switch using a binary grouping network.

In general, ATM is a new communication mode that takes advantage of so-called circuit switching and packet switching. It is a kind of packet communication method and transmits all information using a packet called a cell. Accordingly, regardless of the transmission speed of each information, it is possible to transmit according to its characteristics, thereby enabling information exchange between each subscriber to one ATM repeater. In addition, in ATM, it is possible to transmit the required amount of information at the required time, and its property also has a good influence on the encoding of the image.

In other words, ATM is adaptable to communication in which information requiring various information speeds or time rigors is mixed.

A typical ATM switch using such an ATM is configured to pre-classify a cell to be input to a unit switch by placing a grouping network in front of a routing network. However, the grouping network eliminates internal blocking in a multistage interconnection network structure and ensures cell order, but has a problem of increasing hardware complexity.

FIG. 1 is a switch structure using a general grouping network. A multiplexing effect can be obtained by grouping and transmitting cells output to M output ports. That is, by grouping the cells output to the M output port to the LM × M unit switching module (SM: Switching Module) to be independent switching for each group.

In general, a grouping network consists of N x LM gridpoints to separate the N inputs into L groups with M outputs. At each lattice point, cells belonging to the group are down and cells not belonging to the group are switched to the right to separate the maximum M cells in each group. At this time, the value of M is generally determined by the size of the unit switch module (SM) that can be implemented, L is a value determined by the performance of the grouping network.

When the implementable unit switch module SM has 64 outputs at a maximum of 64 inputs, the value of L decreases as the value of M in the grouping network increases. That is, let the input load be 90%, L value having the same cell loss rate at M = 2 is less than 8, and the value is about 2 when M = 32. L values for M satisfying the cell loss rates of 10 ⁻¹⁰ and 10 ⁻⁸ or less at each input load are shown in Table 1 below.

An example of a grouping network state operating on the principle described above will be described with reference to FIG.

In the example grouping network, the number of input / output (N) is 4, the number of groups (M) is 4, and the number of ports belonging to one group, that is, the number of cells (L) is 2.

First, look at the output address of the input cell and switch down only the zero cells in the first two stages, and the rest to the right. In the 3rd and 4th stages, the cell with the output address of 1 is outputted down. In FIG. If the number of cells belonging to one group exceeds 2, the cells are switched incorrectly and cell loss occurs. Therefore, as the number of L increases, the performance of the grouping network increases.

In general, the number of unit lattice points of the grouping network is N × LM as described above. Typically, the cell loss rate of an ATM switch is 10 In order to configure a 1024 × 1024 switch using a 64 × 64 unit switch module, the number of unit grid points is calculated as shown in Table 1 below.

1024 × (1.55 × 1024) = 1,550,000

This is about 1.55 times more complicated than hardware in a 1024 × 1024 ATM switch.

As a general grouping network does not need a buffer inside the network, the unit grid point configuration is simple, but it is disadvantageous in terms of cost to construct a large-capacity ATM switch using a grid point whose number is greatly increased.

The present invention has been devised to solve the above problems, and it is easy to configure a large-capacity switch having hundreds and thousands of input / output ports by reducing the complexity of hardware by performing binary radix sorting that repeats binary grouping in a binary grouping network. For the purpose of

Here, binary radix sorting is a method of obtaining an ordered permutation by repeating a process of dividing an ordered value into binary numbers and dividing the value into two groups of 0 or 1 for each bit value.

A feature of the present invention using such a binary radix alignment is that, in an ATM switch using a grouping network in which input cells are grouped and then input to a transmission network, the M × M unit switch module switches each unit for the total number of input / output cells. It configures a large capacity switch by arranging the number of module outputs (N / M) and grouping them into binary concentrators, which are divided into two groups of 0 or 1 for each bit value by expressing them as binary in advance. . At this time, the cell is classified into N / M groups in the grouping network before being input to the unit switch module. That is, since there is no queue delay variation of the grouping network, the cell order of the entire switch network is guaranteed as long as the unit switch module guarantees the cell order.

In addition, the binary concentrator has the same number of input and output cells, 2 × 2 units (number of input / output cells / 2) for inputting a cell and separating the cells into odd-numbered zero cells and even-numbered zero cells. Two (number of input / output cells / 2) x (number of input / output cells / 2) for inputting a switch element and a cell switched by the 2x2 unit switch element and sequentially outputting the output address bit from 0 It consists of a binary concentrator.

Here, among the binary concentrators performing grouping in the grouping network, the first binary concentrator concentrates the assigned cells and performs grouping by dividing the bits of the output address into two groups of 0 to 1 from the second binary concentrator. .

Hereinafter, an embodiment of the present invention will be described in more detail with reference to the accompanying drawings.

3 is a schematic diagram of an ATM switch using a binary grouping network according to an embodiment of the present invention. A binary concentrator for arranging N / M M × M unit switch modules (SMs) and grouping the inputted cells in advance is shown in FIG. (BC: Binary Concentrators). Here, the binary concentrator (BC) sorts each cell using a binary radix sorting method, by repeating a process of dividing the sorted values into two groups of 0 or 1 for each bit value by expressing the sorted values in binary. Find an ordered permutation. At this time, the cells are classified into N / M groups in the grouping network of the binary concentrator BC before being input to the unit switch module SM.

4 shows the binary concentrator BC as an N × N capacity binary concentrator BC, two N / 2 × N / 2 binary concentrators BC and N / 2 2 × 2 units. The switch element S can be comprised. Therefore, the number of 2x2 unit switch elements S in the NxN binary concentrator BC becomes N / 2 logN.

The 2 × 2 unit switch element S of the N × N binary concentrator BC switches a cell having an odd number 0 to a binary concentrator at the top of the N / 2 × N / 2 binary concentrator BC, The even-numbered zero cells switch to the lower binary concentrator of the N / 2 x N / 2 binary concentrators BC. The N / 2 × N / 2 binary concentrator outputs the switched cells in order from the top when the output address is zero.

Therefore, the output address bits are divided into 0 and 1, and when the number of binary groups is set to a value of N / 2 or more, some divided cells may belong to all groups and the cell loss rate is low.

Referring to the operation of the ATM switch using a binary grouping network of the present invention made as described above are as follows.

Concentrate the assigned cells in the first binary concentrator (BC1) of the grouping network for the configuration of the N × N switch, and the most significant bit (MSB) of the output address in the second binary concentrator (BC2). ) Sort by value. For example, a 1024 × 1024 switch concentrates allocation cells in the first binary concentrator (BC1) of the grouping network, and the most significant bit (MSB) of the output address on the 1024 input port in the second binary concentrator (BC2) Separate into two groups of ones. The cell loss rate is the probability that the number of cells in each of the two groups separated by 90% of the input load exceeds 562, that is, 10 It is as follows. When the input load is 90%, the average number of cells input to the third binary concentrator (BC3) is 461 (= 1024 × 0.9 / 2), and the number of input ports is 562, so the input load is 82%. To (461/562). Accordingly, the output of the third binary concentrator BC3 can be divided into two groups having up to 305 cells. If such binary radix alignment is continued, it can be grouped by the capacity of the M × M unit switch module SM. For example, when M = 64, in order to expand to a large-capacity switch with a capacity of 1024 or 256 ports, a grouping network is formed by a binary concentration process of 5 or 3 steps, respectively.

As such, the binary radix alignment is performed in the binary concentrator BC, and the cells separated in the binary concentrator BC are input to the next stage binary concentrator BC as shown in FIG. That is, for grouping, the first binary concentrator BC-16 concentrates allocation cells, and the actual grouping procedure is performed through the binary concentrator after the second stage. For example, as shown in FIG. 5, a cell inputted to 16 ports is divided into two groups of output ports 0 to 7 and 8 to 15 in the second binary concentrator (BC-16). The probability that cells beyond the number of input ports of the third stage binary concentrator (BC-10) enter the switch should be set to a value less than the desired cell loss rate. By repeating this process, the input cells are divided into a number of groups that can be accommodated by the unit switch module SM. In the binary concentrator, the number of cells in each grouping group is variable, so a range of cells belong to both groups and mistransmitted cells are removed by a filter.

At this time, the header of the cell input to the switch is composed of one bit for distinguishing allocated / non-allocated cells and logN bits representing an output address. Here, all bit values of the unassigned cell are defined as one.

Accordingly, looking at the grouping state of the input and output cells of each binary concentrator is shown in Table 2 showing an example of the operation of the 16 × 16 grouping network.

That is, the first bit is used to separate the allocated / unallocated cells in the first binary concentrator BC-16 of the grouping network. It is assumed here that the unassigned cell is 11111. The separated cell is input to the second binary concentrator BC-16 and separated into two groups of output ports 0-7 and 8-15 using a second bit.

The second group is entered in reverse order from the lower port so that the cells of the classified two groups can be grouped in the same process. At this time, since the number of inputs of the third binary concentrator BC-10 is greater than the number of output ports of the second binary concentrator BC-16, the boundary portions of the two groups overlap. Subsequently, the binary grouping process is performed in the same manner as in the third binary concentrator BC-10, and classified into four groups of output ports 0 to 3, 4 to 7, 8 to 11, and 12 to 15. Finally, four groups of cells are delivered to the 6 × 4 unit switch module (SM) to be switched to the destination output port.

As described above, the cells grouped in the binary grouping network of the 16 × 16 ATM switch are classified into four groups and transmitted to the corresponding output port by each 6 × 4 unit switch module.

On the other hand, in the binary grouping network of 1024 × 1024 ATM switches, the grouped cells are classified into 32 groups and transmitted to the corresponding output ports by each 64 × 64 unit switch module. In this case, the hardware complexity of the existing grouping network, that is, the number of grid points is LN Therefore, the number of switch lattice points having N = 1024 and M = 32 is about 2 million. In the number of grid points, there are 1 million grid switches. Here, the number of lattice points according to the switch structure is compared with FIG. This shows that the cell loss rate in binary grouping networks is 10 Hereinafter, the number of grid points is about 40,000, which is superior to the complexity of the existing switch structure.

As described above, there is a problem that the number of grid points increases as the number of cells increases as the number of cells increases due to the conventional switching operation by the grouping network. However, the number of grid points is determined by binary grouping according to the present invention. The reduced hardware configuration simplifies the ATM switch's performance and increases its capacity.

Claims (3)

In an ATM switch using a grouping network that groups input cells and inputs them to a transport network, the M × M unit switch module (SM) is listed by the number of unit switch module outputs (N / M) for the total number of input / output cells. In addition, the inputted cells are represented in binary in advance and grouped by binary concentrators (BCs) that divide into two groups of 0 or 1 for each bit value, thereby enabling the construction of a large capacity switch. ATM switch using binary grouping network. The first binary concentrator (BC1) of the binary concentrator (BC) concentrates allocated cells, and sets the bits of the output address from the second binary concentrator (BC2) to 0 to 1. ATM switch using a binary grouping network, characterized in that performing grouping while separating into groups. According to claim 1, wherein the binary concentrator (BC) has the same number of input and output cells, and inputs a cell to switch to separate cells with odd zeros and cells with even zeros (input and output cells) Number of 2/2) 2x2 unit switch elements S and cells (switched by the 2x2 unit switch element S) are input and two (input and output) are sequentially output from the case where the output address bit is 0. ATM switch using a binary grouping network, characterized in that it consists of a binary concentrator (BC), which is the number of cells / 2) × (the number of input / output cells / 2).