KR0156402B1 - Data transmissin system multiplizing apparatus & frame structure - Google Patents

Abstract

The present invention relates to a data transmission system, and more particularly, to a multiplexing apparatus and a frame structure of a data transmission system adapted to multiplex an E2 signal using an error correction code so as to be suitable for a wireless transmission apparatus affected by external environmental factors.

This object of the present invention is to scrambling a framer for multiplexing high-speed 8MHZ data obtained from multiplexing means, a channel for remote monitoring, an order / wire channel, a channel for data communication, and an error correction feature, and a transmission signal multiplexed and output from the framer. Detects the position of the frame word from the received data output from the descrambler, the descrambler that decodes the received data and clock, the 8MHZ data and the remote monitoring and order-wire data and services. This is achieved by having a deframer that demultiplexes into channel data for data and data communication.

Description

Multiplexing Device and Frame Structure of Data Transmission System

1 is a block diagram of a conventional E2 multiplexing device.

2 is a multiplexed frame structure diagram according to FIG.

3 is a block diagram of a multiplexing device according to the present invention.

4 is a multiplex frame structure diagram according to FIG.

* Explanation of symbols for main parts of the drawings

103: Framer 105: Scrambler

107: descrambler 108: deframer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system, and more particularly, to a multiplexing apparatus and a frame structure of a data transmission system adapted to be adapted to a wireless transmission apparatus affected by external environmental factors by multiplexing E2 signals using error correction codes.

FIG. 1 is a schematic diagram of an E2 multiplexing device recommended in the CCITT. As shown in FIG. 1, a first line interface unit 10 receiving a low-speed E1 signal obtained from a line side and a first line interface unit 10 are provided. The code conversion unit 21 converts the obtained line-side line code into a non-return to zero signal, and buffers the speed difference between the E2 signal and the E1 signal generated during multiplexing. A transmitter 20 comprising a speed buffer 22, a stuffing controller 23 for controlling the speed buffer 22, and a multiplexer 24 for multiplexing and transmitting the low-speed subscriber data into 8MHZ high-speed data; A receiver 30 comprising a demultiplexer 31 for demultiplexing the received 8MHZ high-speed data and a code converter 32 for converting the E1 signal demultiplexed by the demultiplexer 31 into a line code; Reverse at the receiver 30 A second line interface unit 40 for transmitting the neutralized received data to the connected subscriber line, a controller 50 for controlling the transmitter 20 and the receiver 30, and a multiplexer in the transmitter 20 And a clock generator 60 for providing a synchronous clock to the numeral 24.

The operation of the conventional E2 signal multiplexing device constructed as described above will be described in detail with reference to FIG. 2.

First, the first line interface unit 10 receives an E1 signal obtained from the subscriber line E1 # 1 and inputs it to the code conversion unit 21 in the transmitter 20.

Accordingly, the code converting section 21 codes the input 2MHZ low speed line code into an NRZ signal and inputs it to the speed buffer section 2.

The speed buffer 22 adjusts the speed difference between the signal E1 and the signal E2 under the control of the stuffing controller 23 and inputs the result to the multiplexer 24.

The multiplexer 24 multiplexes four input 2MHZ low-speed data into a clock obtained by the clock generator 60 and multiplexes the data to 8MHZ high-speed data and transmits the data together with the clock.

The frame structure of the multiplexed data transmitted at this time is as shown in FIG.

This multiplexed frame structure is in accordance with CCITT G.743 Recommendation.

In Figure 2, F: Frame alignment signal (1111010000), A: Bit for alarm transmission (Alarm ---- 0, Non-alarm ---- 1), N: Bit reserved for national use, # 1 # 205: Bits from tributaries, C1, C2, C3: Justification control bits (Positive Justification ---- 111, No Justification ---- 000), V: Bits from tributaries available for justification.

The tributary bit rate is 2048 Kbit / s, the number of tribuaries is 4, the frame length is 848 bits, the bits per tributary is 206 bits, and the nominal justification ratio is 0.424.

The frame rate is 9.96 Kbit / s.

Therefore, the stuffing S is 8448 = 2048 * (848/824) * (206 / (206-S), so S = 0.424.

Meanwhile, the multiplexed high-speed 8MHZ E2 signal is demultiplexed into four 2MHZ low-speed data by the demultiplexer 31 in the receiver 30.

The demultiplexed received data is converted into a code corresponding to the line code in the code switching unit 32 and transferred to the subscriber connected through the second line interface unit 40.

However, the conventional E1 signal multiplexing device is simply multiplexed with four E1 signals, which is not suitable for wireless communication with a large change in external environmental factors.

In addition, there is a disadvantage that a new frame structure is required to provide a monitoring channel, a service channel, and an order wire channel.

Accordingly, the present invention is to solve the above problems of the conventional multiplexing device, and an object of the present invention is to use an error correction code and multiplex the E2 signal so as to be suitable for a wireless transmission device affected by external environmental factors. The present invention provides a multiplexing device and a frame structure of a transmission system.

The technical means for achieving the object of the present invention is a framer for multiplexing the multiplexed high-speed 8MHZ data, remote monitoring channel, order wire channel, data communication channel and error correction feature, and multiplexed from the framer A scrambler that scrambles a transmission signal to transmit data and a clock, a descrambler that decodes received data and a clock, and detects the position of a frame word from the received data output from the descrambler. It consists of a deframer that demultiplexes into wire data and channel data for data communication.

A frame structure for achieving the object of the present invention is the multiplexing of the frame word area for multiplexing the position data of the frame, the service channel area for multiplexing the service data, and the data for adjusting the speed difference of the signal generated during the multiplexing And a parity area for multiplexing the presence or absence of error data on the transmission path.

Hereinafter, described in detail with reference to the accompanying drawings of the present invention.

3 is a schematic diagram of a multiplexing apparatus according to the present invention, and as shown, a first line interface unit 100 receiving a low-speed E1 signal obtained from a line side, and a line obtained from the first line interface unit 100. A code converter 101a for converting the side line codes into a non-return to zero signal, a speed buffer 101b for buffering a speed difference between the E2 signal and the E1 signal generated during multiplexing; A multiplexing unit 101 including a stuffing control unit 101c for controlling the speed buffer unit 101b, a multiplexer 101b for multiplexing and transmitting the low-speed subscriber data into 8MHZ high-speed data, and the multiplexing unit 101 A first clock generator 102 for applying a synchronous clock to the multiplexer, multiplexed high-speed 8MHZ data output from the multiplexer 101, a channel for remote monitoring, an order wire channel, a channel for data communication, and an error; A framer 103 for multiplexing the regularity, a scrambler 105 for scrambled transmission signals multiplexed and outputted from the framer 103 to transmit data and a clock, and a descrambler for decoding the received data and clock. And a descrambler 108 for detecting the position of the frame word from the received data output from the descrambler 107 and demultiplexing the 8MHZ data with the channel data for remote monitoring and order wire data and data communication. A demultiplexer 109 for demultiplexing 8MHZ high-speed data demultiplexed by the descrambler 108 into four low-speed data, and an E1 signal demultiplexed by the demultiplexer 109 to a connected subscriber line Control the second line interface unit 110, the multiplexer 101, the demultiplexer 109, the framer 103 and the deframer 108 for transmission. For the control unit 106.

The operation and effects of the multiplexing apparatus according to the present invention configured as described above will be described with reference to FIG. 4.

First, the first line interface unit 100 receives four E1 signals E1 # 1, E1 # 2, E1 # 3, and E1 # 4, which are obtained from the subscriber line E1 # 1, and receives the multiplexer 20. Input to the code conversion section 101a.

Accordingly, the code converter 101a codes the input 2MHZ low speed line code into an NRZ signal and inputs the inputted code to the speed buffer 101b.

The speed buffer 101b adjusts the speed difference between the signal E1 and the signal E2 under the control of the stuffing controller 101c and inputs the same to the multiplexer 101d.

The multiplexer 101d multiplexes four input 2MHZ low-speed data into a clock obtained by the first clock generator 102 to multiplex the data to 8MHZ high-speed data and output the same together with the clock.

Thus, the framer 103 multiplexes the transmission data multiplexed with 8MHZ in synchronization with a clock obtained from the second clock generator 104, a remote monitoring channel having a bandwidth of 64 Kbps, an order wire channel data and a data communication channel, and an error correction parity. Multiplexing with and outputs the same frame structure as the fourth degree.

That is, as shown in FIG. 4, the frame structure is 132 bits horizontally and 9 lines vertically to multiplex 1188 bits into one frame.

In this case, F is an area for multiplexing a frame word indicating a frame position (Frame alignment signal (00010111)), and a total of 9 bits are allocated.

In addition, 01-08 multiplexes the order wire data and consists of two channels in the service channel region (Order Wire data).

In addition, D1-D9 (Service Channel for DCU) and M1-M9 (Service Channel for MCU) are service channel regions in which service data are multiplexed, and D1-D9 are composed of two channels, and M1-M9 are composed of one channel.

The service channel areas 01 to 08, D1 to D9, and M1 to M9 in which the above service data are multiplexed are divided into five parts.

In addition, C1, C2, and C3 (justification control bits (Positive Justification ---- 111, No Justification ---- 000)) are stuffing control bits that control the speed difference from 8.448MHZ data generated by multiplexing. It is composed.

In addition, PRY1 to PRY9 (Parity bit) are error correction parity bits that can correct 1-bit errors within 127 bits, and are divided into nine parts and each area is composed of seven bits.

In addition, P1-P9 (Parity bit) is a parity bit that determines the presence or absence of an error on a transmission path, and is divided into nine pieces and is composed of one bit.

In addition, A: Bit for alarm transmission (Alarm ---- 0, Non-alarm ---- 1), N: Bit reserved for national use, # 1-# 1038: Bits form tributaries, V: Bits from tributaries available for justification, X: Don't CARE.

The frame of the present invention has a tributary bit rate of 844 Kbit / s, a number of tributaries of 1, a frame length of 1188 bits, a bits of tributary of 1055 bits, a nominal justification ratio of 0.332, and a frame rate of rate) is 8.01 Kbit / s.

The final rate of the multiplexed data is 9.516MHZ, which can be solved by the equation: 9.516MHZ = 8.448MHZ * 1 * (1188/1055) * (1055 / (1055-S), resulting in S = 0.332.

This results in 33 stuffings per 100 frames.

In addition, by sending seven permissions every 127 bits, 1-bit error in 127 bits is 100% corrected.

In addition, C1-C3 is a stuffing control bit that controls the speed difference with 8.44MHZ signal generated while multiplexing. When 8MHZ data is inputted quickly, C1-C3 bits are all multiplexed to V bits and 8MHZ data is input slowly. If the C1-C3 bits are all 0, the speed is controlled by not multiplexing information on the above-mentioned V bits.

The transmission data multiplexed with such a frame structure is encrypted by the scrambler 105 to transmit data and a clock.

On the other hand, the received multiplexed high speed 8MHZ E2 signal is decoded in the descrambler 107 and the decoded received data is demultiplexed in the deframer 108.

That is, the liquid crystal panel 108 first detects the position of the frame word from the received data, and extracts 8MHZ data and remote monitoring data or order wire data or data for a channel for data communication at each position.

Using PRY1 to PRY9, 1-bit error within 127 bits is 100% corrected.

The extracted 8MHZ data is input to the demultiplexer 109, and the demultiplexer 109 demultiplexes the input 8MHZ high-speed data into four 2MHZ low-speed data and delivers it to the second line interface unit 100. Done.

The second line interface unit 11 transmits the low speed data to be connected to the connected subscriber line.

As described above, the present invention can multiplex the error correction code and the service channel to the E1 signal or the multiplexed 8MHZ E2 signal, which is suitable for a wireless communication network in which the external environment is severely changed.

Claims (9)

A high-speed 8MHZ data obtained from the multiplexing means, a framer for multiplexing the remote monitoring channel, the order / wire channel, the data communication channel, and the error correction ferriment, and the scrambled transmission signal multiplexed and outputted from the framer to scramble the data and the clock. Including a scrambler to transmit and a deframer to detect the position of the frame word from the received data output from the received descrambler and to demultiplex the 8MHZ data into the channel data for remote monitoring and order-wire data, service data and data communication. Multiplexing device of a data transmission system, characterized in that configured. 2. The framer of claim 1, wherein the framer is configured to generate a stuffing control signal using a clock obtained by the multiplexing means, and a speed of the stuffing control unit 103b and the data multiplexed by the multiplexing means under control of the stuffing control unit 103b. Framer 103c which multiplexes and outputs the 8 MHZ data obtained from the speed buffer 103a, the channel for remote monitoring, the order / wire channel, the channel for data communication, and the error correction parity. Multiplexing apparatus of a data transmission system, characterized in that consisting of. The deframer according to claim 1, wherein the deframer detects the position of the frame word from the received data obtained by the descrambler and demultiplexes the 8MHZ data and the channel data for remote monitoring and order-wire data, service data, and data communication. A phase comparator 108c for comparing the phase of the reception clock output from the deframer 108a and the oscillation clock obtained from the oscillator 108e and outputting a data rate adjustment signal according to the result; According to the speed control signal of the phase comparator 108c, the speed buffer 108b for buffering and outputting the speed of the demultiplexed data in the deframer 108a and the phase difference obtained in the phase comparator 108c are low ranged. And a low pass filter 108d for filtering and applying the oscillator clock adjustment signal to the oscillator 108e. System multiplexer. A frame word area for multiplexing position data of a frame, a service channel area for multiplexing service data, a service channel area for multiplexing data for adjusting a speed difference of a signal generated when multiplexing, and an error correction signal are multiplexed A multiplex frame structure of a data transmission system, characterized by comprising a frame comprising an error correction area which is formed and a parity area for multiplexing error data on a transmission path. 5. The multiplexed frame structure of claim 4, wherein the frame comprises a total of 1188 bits of 132 bits horizontally and 9 vertically. 5. The multiplexed frame structure of claim 4, wherein the frame word area (F) is located at the front of the frame and consists of 9 bits. 5. The multiplexed frame structure of a data transmission system according to claim 4, wherein the service channel areas (01-08, D1-D9, M1-M9) are divided into five and each divided area is composed of 8 or 9 bits. 5. The multiplexed frame structure of claim 4, wherein the error correction areas (PRY1 to PRY9) are divided into nine pieces and each partition area consists of seven bits. 5. The multiplexed frame structure of claim 4, wherein the parity areas (P1-P9) are divided into nine pieces and each partition area consists of one bit.