KR0155532B1 - Cache memory system - Google Patents

Abstract

The present invention relates to a cache consistency guarantee for data being rewritten in a multiprocessor system, and a feature of the present invention is a cache consistency guarantee for data being rewritten in a multiprocessor system. Latch means for storing a cache value likely to be stored at a time of a control signal from a dual directory, and a latch comparison means for receiving an output value of the latch and an address value currently being executed on the bus and comparing them to output a latch matching signal. And identifier comparison means for outputting an identifier matching signal indicating whether or not a source identifier, which is a unique number of a processor module, which has requested a cycle in progress on the bus and a magnetic identifier, which is its own number, is the same, and a type of cycle in progress on the bus. Check if this is a cache-related type or not Transmission type comparison means for outputting a transmission type cache signal indicating an associated cycle, an exclusive read signal indicating an exclusive read cycle, a coherent read signal indicating a coherent read cycle, and a writeback signal indicating a writeback cycle, and identifier matching Signals and Transmission Types Cache Signals, Exclusive Read Signals, Coherent Read Signals, Writeback Signals, and Rewrite Enable Signals that indicate the actual cycle of rewriting, the Status Response Signal of the Memory Module, and the Status Response Signal and Bus of the Processor Module. First control means for receiving a bus enable signal indicating that the cycle in progress is successfully completed, a stop signal indicating that the cycle has not been completed successfully, and a bus clock, and outputting a control response signal; and a control response signal and the bus clock. Enter the current string Second control means for outputting a rewrite progress signal indicating that a rewrite cycle is in progress; and a snooping prohibition signal generating means for generating a snooping prohibition signal by receiving a latch matching signal, a transfer type cache signal, and a rewriting progress signal; As a result, the effect is that when a new cache line is read, the cache line pushed by the new cache line must be rewritten because the data has changed, so that a read on the new cache line is performed first and then continues. The performance of the write is processed so that the cache miss access period includes only the new cache line read time and does not include the rewrite time, thereby increasing performance.

Description

Cache consistency guarantee for data being rewritten in multiprocessor systems

1 is a block diagram of an entire system to which the present invention is applied.

2 is an illustration of read and write operations on a nested bus.

Figure 3 is a detailed configuration of the cache consistency guarantee device according to the present invention.

4 is a state transition diagram of REPON-CNTR in the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a device for ensuring cache consistency for data being rewritten in a multiprocessor system, wherein cache data is currently rewritten within one processor module in a multiprocessor system having a bus that allows nested bus operations. In the case of a writeback, the present invention relates to a cache data consistency guarantee device that accurately and effectively blocks an access request of another processor module to an address of this data from the time of rewriting until the data is completely written to the memory.

Conventionally, when a new cache line is read, when the data of the cache line pushed by the new cache line is changed because it is changed, rewrite to the memory is performed first, and then the new cache line is read continuously. did.

On the other hand, cache matching for rewrite data can be guaranteed without special measures since the cache has not yet been replaced with new data.

However, in this case, since the read of the new cache line occurs later in time than the rewrite, the cache miss access period is the sum of the rewrite time and the new cache line read time, thereby increasing the cache miss access period.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to cache data during rewriting in a multiprocessor system in which a read on a new cache line is performed first and then a rewrite is processed to shorten the cache miss access period. To provide a consistency guarantee device.

In order to achieve the above object, a feature of the present invention is a cache consistency guarantee for data being rewritten in a multiprocessor system, wherein a cache value that is likely to be rewritten is set from a dual directory to a control signal point. Latch means for storing, the latch comparison means for receiving the output value of the latch and the address value currently being executed on the bus as an input, and outputs a latch matching signal, and the unique number of the processor module requesting an ongoing cycle on the bus. Identifier comparing means for comparing the source identifier with its own unique identifier and outputting an identifier matching signal indicating whether it is the same or not, and checking whether or not the type of the cycle in progress on the bus is a cache related type. Transmission type cache signal and exclusive read cycle Transmission type comparison means for outputting a coherent read signal indicating a read exclusive signal and a coherent read cycle and a write back signal indicating a write back cycle, the identifier matching signal, the transfer type cache signal, and the exclusive read signal And a rewrite enable signal indicating that the coherent read signal, the writeback signal, and a real rewrite cycle occur, a status response signal of a memory module, a status response signal of a processor module, and a cycle in progress on a bus. First control means for receiving a bus enable signal indicating completion and a stop signal indicating successful completion of the cycle and canceling the cycle, and outputting a control response signal, and receiving the control response signal and the bus clock and rewriting the current; Cycle is in progress And a second control means for outputting a rewrite progress signal, and a snooping prohibition signal generation means for receiving a latch matching signal, the transmission type cache signal, and the rewriting progress signal to generate a snooping prohibition signal. have.

Another aspect of the present invention for achieving the above object is a cache consistency guarantee for data being rewritten in a multiprocessor system, the one on the bus in a multiprocessor system having a bus that allows nested bus operation If a memory access request from another processor module for the same address as this address is in progress while the processor module of the processor is rewriting from memory to the memory, the bus usage for that processor is changed from the start of the rewrite to the end of the process. It is not to allow permission.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of the entire system to which the present invention is applied.

Referring to Figure 1 describes the configuration of the entire system to which the present invention is applied as follows.

The system is a form of connecting n processor modules and m memory modules to a P-bus (Pipeline Bus), a bus that allows overlapping bus operation.

Each processor module has a cache, and the cache data consistency protocol is maintained in hardware between these caches.

P-Bus is a bus that divides one data transmission into request and response steps, and is a kind of pipelined bus that can carry out multiple bus cycles.

In other words, when a processor module requests a memory module to read a specific address, it does not occupy the bus until the actual memory module accesses internal memory, finds data, and passes to the response phase. When one address bus cycle proceeds, another bus cycle may proceed immediately after the next cycle.

2 is an illustration of read and write operations on an overlapping permission bus.

An embodiment of a read and write operation on the overlapping permission bus will be described with reference to FIG. 2.

In the case of writes, the processor module winning the bus arbitration drives the address on the bus in the first cycle and the data on the next bus clock.

The third bus clock drives status information indicating whether a memory module or another processor module may proceed with a write request currently in progress.

The processor module requesting the data transmission analyzes this state to determine whether the transmission is successful.

For reads, the processor module winning the bus arbitration drives the address bus on the bus in the first cycle and does nothing for the next bus clock.

The third bus clock drives status information that indicates whether a memory module or another processor module may proceed with the current read request.

If the status information is appropriate, the memory module prepares data and transmits the data to the processor module which initially requested after a while.

3 is a detailed configuration of the cache consistency guarantee device according to the present invention.

Referring to Figure 3 describes the configuration of the cache consistency guarantee device according to the present invention.

The hardware module executes the output value of REPTAG (Replacement Tag) and REPTAG, which are latches that store the cache value (DD_ADDR) that can be rewritten from DD (Dual Directory) to DD Out Enable (DD_OE). It compares REPTAG-COMP (Replacement Tag Comparator) which inputs the address value being input and compares it, and Source IDentification (SI) which is the unique number of the processor module that requested the cycle in progress on the bus, and Self IDentification (SID) which is its own number. ID-COMP (ID Comparator) and TT-COMP (Transfer Type Comparator) which checks whether the type of cycle in progress on the bus is cache-related type and ID-COMP which indicates that the comparison value is the same. MATCH, TT-COMP output signal, TT-CACHE indicating cache related cycle, EXR indicating exclusive read cycle, CRD indicating coherent read cycle, WRB indicating writeback cycle WBWE (Writeback Write Enable) indicating the cycle of rewriting, M-ACK (Memory Ackonwledge) indicating normal status as the status response signal of the memory module, and snooping failed due to the status response signal of the processor module. Processor Snoop Not Acknowledge (P-SNK), BGT (Bus Grant), which indicates that the cycle in progress on the bus has been completed successfully, and ABT (Abort), which indicates the cycle is canceled without success. As a result, the REPON-CNTR (Replacement On Want Controller), REPTAG-MATCH and TT-CACHE, and REPON-F / F output signals generate REPON-REQ, the input signal for REPON-F / F. It consists of PSNK-GEN (P-SNK Generator) that generates Processor Snoop Not Acknowledge (P-SNK), which is a prohibition of snooping by REP-ON (Replacement On) indicating progress, REPON-CNTR, REPON-F / F operates in synchronization with BCLK, the bus clock.

4 is a state transition diagram of REPON-CNTR in the present invention.

Referring to FIG. 4, the state transition of the REPON-CNTR is described as follows.

RPN_IDLE: If its address cycle is progressed on the P-Bus as a reference state (ID-COMP = 1), and if the TT is likely to replace its internal DD Tag (EXR = 1 or CRD = 1) Transition state with RPN-SKIP.

Otherwise it does not transition.

At this time, the operation in FIG. 3 does not cause any change.

RPN_SKIP: Always transitions to the next state RPN_AACK.

At this time, the operation in FIG. 3 does not cause any change.

RPN_AACK: It checks status information on the bus. If the permission response from the memory module comes (M-ACK = 1) and the response indicating the snooping failure is not received from another processor module (P-SNK = 0), then the RPN_WAIT is returned. Otherwise, transition back to the initial state RPN_IDLE.

At this time, the operation in FIG. 3 does not cause any change.

RPN_WAIT: It is a step to confirm that the operation so far completed without error. When a signal indicating the end of execution occurs (BGT = 1), the state transitions to the next state, RPF_IDLE.

At this time, the operation in FIG. 3 causes the REPON-REQ to be generated (REPON-REQ = 1) by setting the REPON-FF (REP-ON = 1) if the cycle actually occurs internally (WBWE = 1). Reads the address DD_ADDR to be replaced from the DD and stores it in the REPTAG.

From this point on, a check is made between the address of the cycle performed on the bus and the address stored in the REPTAG.

On the other hand, if the current cycle is canceled as a result of snooping by another bus cycle before this cycle ends internally and a signal indicating this is generated (ABT = 1), the cycle is RPN_IDLE state and the cycle is executed again from the beginning.

In this case, no change occurs in the operation of FIG.

There is no transition between the two cases above.

RPF_IDLE: Its own cycle of cycles on the P-Bus as a reference for monitoring the actual overwrite cycle (ID-COMP = 1), where TT is the rewrite type (TT-WRB = 1) Then transitions to RPF-SKIP.

Otherwise it does not transition.

At this time, the operation in FIG. 3 does not cause any change.

RPF_SKIP: Always transitions to the next state, RPF_AACK.

At this time, the operation in FIG. 3 does not cause any change.

RPN_AACK: It checks status information on the bus. If an authorization response from the memory module is received (M-ACK = 1) and no response indicating snooping failure is received from another processor module (P-SNK = 0), then RPF_WAIT is returned. Otherwise, the state transitions to RPF_IDLE, which is the reference state of the second cycle.

At this time, the operation in FIG. 3 does not cause any change.

RPF_WAIT: This step confirms that the operation of the second cycle is completed without error. If a signal indicating the end of execution occurs (BGT = 1), the state transitions to the first state, RPN_IDLE.

In this case, the operation in FIG. 3 resets the REPON-REQ (REPON-REQ = 0) to reset the REPON-FF (REP-ON = 0). You are free to perform the access.

On the other hand, if the current cycle is canceled as a result of snooping by another bus cycle before this cycle ends internally and a signal is signaled (ABT = 1), the cycle will be in RPF_IDLE state and the cycle will resume from the beginning of the second cycle. Will be done.

In this case, no change occurs in the operation of FIG.

There is no transition between the two cases above.

The hardware configuration in this way allows the other processor module to have the same address as the address stored in REPTAG, from the start of the rewrite until the end of the rewrite, that is, while the REP-ON signal is set (REP-ON = 1). If an access request for REPTAG-COMP = 1 is required (TT-CACHE = 1), this causes the processor module's snooping failure response (P-SNK) after two bus clocks (BCLK). By generating, the second bus cycle no longer proceeds to ensure cache matching for data being rewritten.

Therefore, as described above, the effect of the present invention is that when a new cache line is read, the read of the new cache line is performed first and continues if the data of the cache line pushed by the new cache line is changed. Therefore, the performance of the rewrite is processed so that the cache miss access period includes only the new cache line read time and does not include the rewrite time, thereby increasing performance.

Claims (2)

CLAIMS 1. A cache consistency guarantee for data being rewritten in a multiprocessor system, comprising: latch means for storing a cache value likely to be rewritten at a time of a control signal from a dual directory; Latch comparison means for receiving an output value of the latch and an address value currently being executed on a bus and comparing them with each other to output a latch matching signal; Identifier comparing means for comparing a source identifier which is a unique number of a processor module requesting an ongoing cycle on the bus with a magnetic identifier which is its own number, and outputting an identifier matching signal indicating whether or not it is the same; A transfer type cache signal indicating a cache related cycle and an exclusive read signal indicating an exclusive read cycle and a coherent read cycle indicating a coherent read cycle by checking whether a cycle in progress on the bus is a cache related type or not. Transmission mode comparison means for outputting a writeback signal indicating a writeback cycle; A rewrite enable signal and a status response signal of a memory module and a processor indicating that the identifier matching signal, the transmission type cache signal, the exclusive read signal, the coherent read signal, the writeback signal, and a real rewrite cycle occur First control means for receiving a status response signal of the module and a bus enable signal indicating that a cycle in progress on the bus has ended successfully, a stop signal indicating that the cycle is not completed successfully, and a bus clock, and outputting a control response signal; ; Second control means for receiving the control response signal and the bus clock and outputting a rewrite progress signal indicating that a rewrite cycle is currently in progress; And snooping prohibition signal generation means for receiving a latch matching signal, the transmission type cache signal, and the rewriting progress signal to generate a snooping prohibition signal. Cache consistency guarantee for A cache consistency guarantee for data being rewritten in a multiprocessor system, wherein a rewrite from one processor module to memory on a bus proceeds in a multiprocessor system having a bus that allows nested bus operations. In the multiprocessor system, when there is a memory access request of another processor module for the same address as this address, the bus usage is not allowed from the start point of the rewrite until the end point. Cache consistency guarantee for data that is being rewritten.