KR0155266B1 - Fault tolerant computer system - Google Patents

Abstract

The present invention relates to a method for constructing a parallel processing computer system, and more particularly, to a method for configuring an interconnection network of a fault-tolerant computer system, and to a fault-tolerant computer system. In a method of configuring an interconnection network of N, N nodes located at each vertex of one polyhedron in a node group composed of a plurality of nodes and interfacing in a polyhedral form (N is a natural number A first node group connected between nodes in a method of directly interfacing between neighboring nodes, including nodes located inside the polyhedron to interface the N nodes with the N nodes. It includes. Therefore, since the present invention adopts two or more channels between nodes, the reliability of Fault Tolerancy is sufficient, and it is possible to provide infinite scalability of the system with up to 24 channels for each node. In addition, even if one specific node fails, it has a plurality of shortest paths, so it cannot affect the realization of the interconnection network (IN) and thus cannot interfere with the operation of most normal systems. It works.

Description

Multiprocessor computer systems

FIG. 1A is a diagram for explaining a conventional computer system employing a tightly coupled method.

FIG. 1B is a diagram for describing a state in which a plurality of systems having the configuration of FIG. 1A are combined.

Figure 2a is a diagram showing a conventional node configuration used in the loosely coupled (Loosely Coupled) method.

FIG. 2B is a diagram for explaining a small-combined multiprocessor computer system composed of a plurality of nodes shown in FIG. 2A.

3 is a diagram showing the configuration of a node according to the present invention.

4A is a diagram illustrating a structure in which two nodes shown in FIG. 3 are connected.

FIG. 4B is a diagram for briefly describing FIG. 4A.

5 is a diagram illustrating an interconnection network of a level 0 structure according to the present invention.

6 is a diagram illustrating an interconnection network of a level 1 structure according to the present invention.

7 is a diagram illustrating an interconnection network of a level 2 structure according to the present invention.

8 is a diagram illustrating an interconnection network of a level 3 structure according to the present invention.

The present invention relates to a multiprocessor computer system, and more particularly to a fault tolerant computer system having fault-tolerant characteristics.

As various information speedups are required, faster fault tolerant computers are required. Many methods have been proposed to meet this problem, and there are efforts to meet and meet technical branches of various fields.

It also attempts to increase throughput by efficiently interconnecting more CPUs in order to improve system performance in fault-tolerant systems, a branch of the technology branch. Have been. Although there are several methods, the present invention provides a scalable fault using a new interconnect network method that can facilitate fault scalability while ensuring fault tolerance. I would like to propose a Fault Tolerant architecture.

Fault Tolerant, or Fault Tolerant, is the normal system operation that prevents the system from going down in the event of any single fault. This is approached by installing two or more channels instead of a single channel. Even if one channel is down for some reason, it is due to the fact that the remaining one channel can be used as a communication path. Also, even if two channels are simultaneously down, they can be connected using different paths, so that their reliability can be quite high.

As one of several attempts to have such a fault tolerant, several interconnection network methods have been proposed so far, but the scalability is efficient in a massively parallel processing system. Was not considered.

In the case of tightly coupled method, the scalability of the system was limited. In the case of the loosely coupled method, if one node or one path failed, the faulty node was removed. Because it operates in the state, system performance greatly decreases.

In other words, the conventional methods with fault tolerant and attempted efficient scalability of the system do not meet the expectations of large parallel processing systems that require faster processing.

Accordingly, an object of the present invention is to solve the problems of the prior art, and has a fault-tolerant and a multiprocessor capable of forming an infinite interconnection network with only a fixed channel. To provide a computer system.

A multiprocessor computer system according to the present invention comprising a plurality of nodes for achieving the above object and an interconnection network for providing a data transmission path between the nodes, the node comprising: a first bus for transmitting information; A second bus for transmitting information; A plurality of computing elements connected to the first bus and the second bus; A plurality of memory elements connected to the first bus and the second bus; A plurality of input / output elements connected to the first bus and the second bus; A first inter-network communication element connected to the first bus to provide a communication channel with another node; And a second inter-network communication element connected to the second bus to provide a communication channel with another node, wherein the interconnection network places one node at each vertex of the cube shape and the inside of the cube shape. And a pair of communication channels connecting nodes by each corner and eight pairs of communication channels between nodes located at each vertex of the cube shape and nodes located therein.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention. First, prior to describing the present invention, a conventional prior art will be briefly described for a proper understanding of the present invention.

FIG. 1A is a diagram for explaining a conventional method employing a tightly coupled method. In FIG. 1A, reference numeral 10 denotes a plurality of processing element modules (hereinafter referred to as PE), 12 denotes a plurality of memory elements (hereinafter referred to as ME), and 14 denotes a plurality of input / output elements. (Input / Output Processing Module; hereinafter referred to as IOP), 16 are two bus interface devices, and two buses, namely, A bus and A bus, are used to interface with each other. Configure the system.

FIG. 1B is a view for explaining a state in which a plurality of individual systems in FIG. 1A employing a tightly coupled method are formed. In FIG. 1B, reference numerals 20, 22, and 24 denote respective system 1 20, system 2 22, and system n 24 shown in FIG. 1A. As can be seen in the drawing, the interface between system 1 (20) and system 2 (22) is directly connected to bus A and bus B, but system 1 (20) and system n (24) are not limited to system 2 (22). The connection is made through the system. Fault Tolerant can be satisfied by using two buses, but there are many limitations in the scalability of the system.

Let's look at another conventional method.

Figure 2a is a view for explaining a conventional method adopting the loosely coupled (Loosely Coupled) method. In FIG. 2A, reference numeral 30 denotes a PE as outlined in FIG. 1A, 32 is ME, 34 is IOP, and a node (system) which performs an interface with each other as a local bus. ).

FIG. 2B is a diagram for explaining a state in which a plurality of individual nodes (systems) in FIG. 2A, which adopt a loosely coupled method, are formed. In FIG. 2B, reference numerals 40, 42, and 44 are each node 1 40, node 2 42, and node n 44 shown in FIG. 2A. As shown in the figure, the interface between the node 1 40, the node 2 42, and the node n 44 may be smoothly performed. In other words, the scalability of the system is met. However, in this case, when a fault occurs in one node, the faulty node is operated in a state in which the fault node is removed.

Then, the present invention will be described with reference to the drawings as described above.

3 is a diagram according to the present invention having the most basic structure that constitutes a node. In FIG. 3, reference numeral 50 denotes a plurality of PEs, 52 denotes a plurality of MEs, 54 denotes a plurality of IOPs, and 56 denotes an Interconnect Network Communication Module having 12 channels, respectively. Is INC X, 58 is INC Y having 12 channels, and constitutes one node (system) that performs an interface between two buses, namely, A bus and B bus.

In the present invention, the system can be expanded as much as necessary by connecting several nodes. The case where two nodes are connected is shown in FIG. 4A.

FIG. 4A is a diagram showing a case where two nodes as shown in FIG. 3 are connected. For convenience of description, FIG. 4A is shown as FIG. 4B. In the connection between nodes, channel X and channel Y are always connected in pairs at the same time, and data is transmitted to another channel even when one channel is abnormal. That is, it has a fault-tolerant.

Channel X and channel Y of FIG. 4a are grouped together to be expressed as one as shown in FIG. 4b. The reason for this simplicity is to explain the more complicated interconnection network (IN). Then, it will be shown that a plurality of nodes as shown in FIG. 3 can be infinitely connected using only a fixed number of channels.

5 is a diagram illustrating a level 0 structure constituting an interconnection network. This is a view for explaining a state in which nine nodes as shown in FIG. Then, each node of FIG. 5 is named. In FIG. 5, reference numeral 60 is C (Center), 62 is Upper North (UN), 64 is Upper East (UE), 66 is Upper West (UW), and 68 is Upper South (US). 70 is Lower North (LN), 72 is Lower East (LE), 74 is Lower West (LW), and 76 is Lower South (LS). In FIG. 5, node C 60 can directly interface with eight other nodes, and in the case of node UN 62, node UE 64, node UW 66, node LN 70, node C. It is possible to interface directly with (60), and to interface with other nodes via one node. In the case of forming the IN as shown in FIG. Then, let's look at the case of forming a more complex IN.

FIG. 6 is a diagram showing the structure of Level 1 constituting the interconnection network IN. This is a diagram for explaining a state in which 19 nodes as shown in FIG. 3 are connected. Then, each node of FIG. 6 is named.

In Fig. 6, reference numeral 80 is node C, 82 is C / W / UN, 84 is C / E / UN, 86 is C / W / UE, and 88 is C / E / UE. Naming of the remaining nodes will be omitted for simplicity. That is, in FIG. 6, two structures similar to those of FIG. 5 are connected to the left and right about the new center C. As shown in FIG. At this time, the center of the basic structure on the left and right became W (West) and E (East) for the new center, so that the unique name for each node was named in a directory manner. The eight nodes of each level 0 structure on the left and right sides are connected to each other as follows.

In this case, the node C 80 needs two pairs of X and Y channels, that is, four channels, and the node C (not designated by reference numerals) of each level 0 structure on the left and right sides has nine pairs of X and Y channels. 18 channels are needed, and the node C / W / UN 82 needs 5 pairs of X and Y channels, that is, 10 channels. In addition, each of the 16 nodes (including the node C / W / UN 82) located at the same corner as the node C / W / UN 82 is similarly paired with 5 pairs of X and Y channels, that is, 10 Channels are required. The more complicated structure will then be described.

FIG. 7 is a diagram illustrating a structure of Level 2 constituting an interconnection network. This is a diagram for explaining a state in which 37 nodes as shown in FIG. 3 are connected. Then, each node of FIG. 7 is named.

In FIG. 7, reference numeral 90 is node C, 92 is C / N, 94 is C / N / UN, 96 is C / E / UN, and 98 is C / W / UN. For simplicity, the remaining nodes will be omitted. In the level 2 structure, the nodes farthest from the node C 90 are connected to each other as follows.

In this case, node C 90 needs four pairs of X and Y channels, i.e., eight channels, and C / E (not named) and C / W in the same location, including node C / N 92. (Not named), and C / S (not named) require 11 pairs of X, Y channels, or 22 channels, and 32 nodes including node C / N / UN 94. Each node needs six pairs of X and Y channels, or 12 channels.

Let's look at a more complicated structure.

8 is a diagram showing the structure of Level 3 constituting the interconnection network IN. This is a diagram for explaining a state in which 73 nodes as shown in FIG. 3 are connected. Then, each node of FIG. 8 is named.

In FIG. 8, reference numeral 100 is node C, 102 is node C / UN, 104 is node C / UE, 106 is node C / UW, 108 is node C / US, 110 is node C / LN, 112 is node C / LE, 114 is node C / LW, 116 is node C / LS, 118 is node C / UN / UN, 120 is node C / UE / UN, 122 is Node C / UW / UN, 124 is node C / LN / UN. The following naming of nodes is omitted. In addition, in the drawing, only nodes C / UN / UN 118, node C / UE / UN 120, node C / UW / UN 122, and node C / LN / UN 124 are connected to each other. Although shown, this connection is omitted between the nodes in consideration of the ease of drawing. For the level 3 structure shown in FIG. 8, node C 100 requires eight pairs of X, Y channels, or 16 channels, and nodes 102, 104, 106, 108, 110, 112, 114, and 116. Requires 12 pairs of X and Y channels, i.e., 24 channels, and 64 nodes including node 118 need 7 pairs of X and Y channels, i.e., 14 channels. So far, we have looked at the number of channels needed for the interface between nodes from level 0 structure to level 3 structure. Nodes with up to 24 channels enable complex inter-node interfaces.

Let's look at a more complex interconnection network. This can be achieved in the following way.

The interconnection network of FIG. 8 is regarded as a cell, and each node of FIG. 5 is considered as a cell, thereby forming an interconnection network. In addition, if a larger interconnection network is to be formed, likewise, the entire interconnection network of FIG. 8 is regarded as one cell, and each node of FIG. 6 is regarded as a cell. . In this way, the interconnection network can be infinitely large. However, even the largest IN can be any number of 24 channels. In addition, it is apparent that the path between nodes should be adopted as the shortest distance, and even if a fault occurs in any one node, the shortest path is sufficient for reasons other than the only reason.

Since the present invention configured as described above employs two or more channels between nodes, the reliability of fault tolerance is sufficient, and the maximum scalability of the system is infinitely increased by 24 channels for each node. Even if a particular node fails, it has multiple shortest paths, so it can't affect the realization of the interconnection network. There is.

Claims (3)

A multiprocessor computer system according to the present invention comprising a plurality of nodes and an interconnection network for providing data transmission paths between the nodes, the node comprising: a first bus and a second bus for transmitting information; A plurality of computing elements connected to the first bus and the second bus; A plurality of storage devices connected to the first bus and the second bus; A plurality of input / output devices connected to the first bus and the second bus; A first inter-network communication element connected to the first bus and providing twelve communication channels with other nodes; And a second inter-network communication element connected to the second bus to provide twelve communication channels with other nodes, and configured to be interchanged when a failure occurs not only in relation to external nodes but also internally. The network connects each node of the cube-shaped vertex and the inside one by one pair, and each pair of communication interconnecting the nodes by the first inter-network communication device and the second inter-network communication device by each corner of the cube shape. And eight pairs of communication channels interconnecting nodes located at each vertex of the channel and the cube shape and nodes located therein by the first inter-network communication device and the second inter-network communication device. Multiprocessor computer system. A multiprocessor computer system comprising a plurality of nodes and an interconnection network providing a data transmission path between the nodes, the multiprocessor computer system comprising: a first node group having the same configuration as the multiprocessor computer system of claim 1; A second node group of the same configuration as the multiprocessor computer system; And a central node having the same configuration as a node included in the multiprocessor computer system, wherein the central node is located inside a cube shape of the first node group and a cube shape of the second node group. And a node located at each vertex of the cube shape of the first node group connected to a node located at each vertex of the cube shape of the second node group. . A multiprocessor computer system comprising a plurality of nodes and an interconnection network providing a data transmission path between the nodes, the interconnection network having nodes having the same configuration as the multiprocessor computer system of claim 1 at each vertex in the form of a cube. Locate a group, and place a central node of the same configuration as the node included in the multiprocessor computer system of claim 1, and a corresponding node included in the node groups by each corner of the cube shape. And nine pairs of communication channels connecting each of the two channels, and eight pairs of communication channels between the nodes in the cube shape formed in each node group and the central node.