KR0154801B1 - Path metric increasing rate monitor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a path metric increasing rate monitor applied to a receiving end of a digital communication system, and receives a path metric of received data through a shift register, a minimum calculation unit, an arithmetic logic unit, and an accumulator. A path metric increase rate measuring device for measuring an increase rate of a path metric, and having a comparison logic at the rear end of the accumulator and comparing the output value of the accumulator with a predetermined threshold value to determine whether the received data is valid.

Description

Path Metric Growth Rate Meter

1 is a hardware diagram of a path metric growth rate meter according to an embodiment of the present invention.

2 is a detailed block diagram of the minimum calculator shown in FIG.

3 is a hardware diagram of a path metric growth rate measuring instrument according to another embodiment of the present invention,

4 is a detailed configuration diagram of the minimum calculator and the maximum calculator shown in FIG.

* Explanation of symbols for main parts of the drawings

11, 17: register 12, 13: shift register

14, 15, 16: Minimum Calculator 18: Arithmetic Logic Unit

19: Accumulator

The present invention relates to a path metric increasing rate monitor. More specifically, the present invention is applied to a receiving end of a digital communication system so as to determine whether the received data is valid by measuring an increase rate of a path metric of the received data. It relates to a path metric growth rate meter.

In a highly developed information society, an efficient, fast and reliable information delivery system is absolutely required. This requires the restructuring of an improved communication system based on a variety of computer-involved communication means and groundbreaking technological innovations.

However, in the communication system, the occurrence of an error due to noise on a channel is one of inevitable problems, and the occurrence of such an error makes it difficult to transmit accurate information.

In order to overcome the above-mentioned problem of error occurrence and to effectively carry out information transfer, a technique has been developed for transmitting and encoding information at a transmitting side and efficiently correcting an error occurring at a transmitting side at a receiving side.

Along with this, various codes for effectively performing error correction have emerged, which are largely divided into block codes and convolutional codes.

A block code is generated by simply encoding an information sequence by a unit of a block of a predetermined length by k bits, and simply encoding n-bit codewords of the same length. In the case of convolutional code, encoding is performed in units of blocks. There is a characteristic that affects the current information block.

In other words, the encoder of the convolutional code includes a memory device. Therefore, the convolutional code has a complicated structure compared to the block code, but the error correction capability is very good.

Decoding methods of convolutional codes are broadly classified into threshold decoding, sequential decoding, and maximum likelihood decoding.

The critical decoding method was devised by Massey in 1963 and is basically the same as the majority decision logic decoding method, which is one of the decoding methods of circuit decoding. This decoding method is characterized by its simplicity and can be handled algebraically, similar to the case of block code.

The sequential decoding method by the Pano algorithm proposed by Fano in 1961 is similar to the stochastic process decoding method, which is the random variable, in which the number of calculations required for decoding is a random variable.

Based on the Viterbi algorithm published by Viterbi in 1967, the maximum likelihood decoding method is to determine the path closest to the topological structure, and to search for the path with the nearest Hamming distance to the receiver. It is a method of performing the path search as simply as possible while eliminating the path that is unlikely because of the decoding method.

In the Viterbi algorithm, when the number of natural elements or memory elements required for encoding is k, there are survival paths of k powers of 2 at each time point, and the probability values of these survival paths are expressed as relative values that are convenient for calculation. This is called a path metric. Here, k + 1 is called a constraint length.

At each time point t these non-negative numbers, called branch metrics, are added to these path metric values, so the path metric values increase with time.

In particular, it is characterized by a rapid increase when the input is not a convolutional code or when there are many transmission errors.

On the other hand, there are times when a Viterbi decoder must solve various ambiguities. When the transmission method is quadrature phase shift keying (QPSK) or quadrature amplitude modulation (QAM), there is a half-pi phase ambiguity on the incoming input data. .

For example, if the convolutional deinterleaver is used in front of the Viterbi decoder, which bits should go to the buffer (FIFO: First-In First-Out). There is ambiguity. If the data is coming in serial, we need to find out which bits represent the convolutional code.

In addition, when a function of deleting some bits is provided to increase the effective transmission rate, it is necessary to find out where the data is deleted.

To resolve these ambiguities, the Viterbi decoder determines whether the input data is valid, and if the input data is invalid, accept another input data and try again. The same process is repeated until the input data is determined to be valid.

There are several ways to determine whether input data is valid.

One of them is a method of measuring a bit error rate (BER). If the bit error rate is too large, it is determined that there is an error in the input. According to this method, the decoding delay of the Viterbi decoder is considerably long because the decoded output data must be compared with the stored original input data. Thus, the method is not suitable for achieving fast synchronization.

Another popular method is to measure the rate at which the path metric is increasing. If the path metric increases too quickly, that is, if the increase over a certain period exceeds a given threshold, it is determined that there is an error in the input data. Here, the path metric values are relative probability values in which valid data exists in each path, and a path having the highest probability is selected and a decoding operation is performed using the path.

Therefore, assuming that a path having a small path metric value has a high probability of valid data, only a path having the smallest path metric value is meaningful.

Assuming that the received signal is encoded by convolutional code and there is no error at all, the minimum value of the path metric does not increase. If there is some error, the minimum value will increase very slowly.

And, if it is not encoded by convolutional code or there is too much error, it increases rapidly. Using this method, we need to compare the path metric values by k powers of 2 when the constraint is k + 1 to extract the minimum value, and if we need to process it in one clock, we need a lot of fast logic.

In addition, interconnection is more important than logic in the implementation of very large scaled integrated circuits (VLSIs), and a significant amount of interconnection is required to compare multiple values to one clock.

Accordingly, in the decoder for determining whether the received data is valid, the increase rate of the path metric is required to be performed by a simple circuit.

The present invention has been made under the conventional technical background as described above, and determines a minimum value in a predetermined number of units of periodically input path metric data, calculates a difference value between the minimum value and the minimum value one step before, and accumulates the path. An object of the present invention is to provide a path metric increase rate measuring instrument for outputting the increase rate of the metric to the outside.

It is still another object of the present invention to provide a path metric increase rate measuring device for determining an approximate minimum value by comparing only some values of periodically input path metric data, and outputting an increase rate of the approximate minimum value to the outside.

As a means for achieving the above object, the configuration of the present invention comprises: a shift register unit for dividing periodically supplied route metric data into bundles of a predetermined length, and sequentially providing one route metric data belonging to each divided bundle one by one; ;

A minimum value calculator for determining a minimum value among path metric data of each bundle provided by the shift register unit and sequentially providing the minimum value;

A register for storing data output from the minimum value calculating unit in one step;

A detailed logic unit for performing a subtraction operation between the two minimum values to calculate and calculate a difference value between the minimum value provided by the minimum value calculator and the minimum value stored in the register;

And an accumulator for accumulating and summing difference values between two minimum values obtained as a result of the operation of the arithmetic logic unit.

As a means for achieving the above another object, the configuration of the present invention,

A register for storing a predetermined number of path metric data and refreshed periodically;

A minimum calculator for determining a minimum of two path metric data stored at a predetermined position of the register;

A maximum value calculator which determines a data having a larger size among the minimum value determined by the minimum value calculator and a maximum value one step before, and outputs the larger data;

And a counter for counting the bit conversion of the data output from the maximum calculator and providing the counted value to the outside in the same manner as the refresh period of the register.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

1 is a hardware diagram of a path metric growth rate meter according to an embodiment of the present invention.

2 is a detailed block diagram of the minimum calculator shown in FIG.

3 is a hardware diagram of a path metric growth rate measuring instrument according to another embodiment of the present invention,

4 is a detailed configuration diagram of the minimum calculator and the maximum calculator shown in FIG.

First, a path metric increase rate measuring device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

As shown in FIG. 1, a path metric increase rate measuring device according to an embodiment of the present invention includes a register 11 having a predetermined byte of storage space; Two shift registers 12 and 13 having predetermined bytes corresponding one-to-one with each byte of the register 11; First and second minimum calculators (14,15) coupled to receive data output from the respective shift registers (12, 13) and feedback output data; A third minimum calculator 16 coupled to receive output data of the first and second minimum calculators 14 and 15; A register (17) for storing output data of the third minimum calculator (16); An Arithmatic Logic Unit (ALU) 18 coupled to receive the output data of the third minimum calculator 16 and the data stored in the register 17; And an accumulator 19 connected to receive the output data of the arithmetic logic unit 18.

In the path metric growth rate meter according to the embodiment of the present invention, the register 111 is 8 bytes, the two shift registers 12 and 13 are 4 bytes, and the register 17 is configured to 1 byte. However, the technical scope of the present invention is not limited thereto, and the number of bytes of the registers 11 and 17 and the shift registers 12 and 13 can be increased or decreased as necessary. The registers 11 and 17 and the shift registers 12 and 13 store the path metric data in bytes, but may be configured in bits or in a predetermined number of bits.

On the other hand, the detailed hardware structures of the first to third minimum calculators 14 to 16 are the same, and the detailed configuration of the first minimum calculator 14 is shown in FIG.

As shown in FIG. 2, the first minimum calculator 14 applied to the path metric increase rate measuring instrument according to an embodiment of the present invention includes: a comparator 141 connected to receive two input data In1 and In2; A multiplex 142 connected to receive two input data In1 and In2 while inputting an output signal of the comparator 141 to a selection terminal; And a register 143 having a storage space for storing output data of the multiplex 142.

Next, the operation of the path metric increase rate measuring device according to the embodiment of the present invention will be described with reference to the configuration shown in FIGS. 1 and 2.

When the power is applied and the operation of the circuit starts, the data stored in the 8-byte register 11 is transferred to each shift register 12, 13 at regular intervals. At this time, each byte of the register 11 corresponds to a byte of each of the shift registers 12 and 13.

Each shift register 12, 13 shifts data in response to a clock being supplied, and the last byte of each shift register 12, 13 is the first minimum value calculator 14 and the second minimum value calculator 15. Is entered.

The first and second minimum value calculators 14 and 15 accept the output data of the minimum value calculators 14 and 15, while the output data of one step before each minimum value calculator 14 and 15 is fed back.

Each minimum calculator 14, 15 outputs the smaller data of the two inputs, the detailed operation of which will be described with reference to the first minimum calculator 14 shown in FIG.

The two inputs In1 and In2 are input to the comparator 141 and the multiplex 142 of the first minimum calculator 14. In the comparator 141, the sizes of the two inputs are compared, and the two inputs In1 and In2 are compared. If one (In1) is smaller than the other (In2), the high level ('1') is output to the multiplex 142, otherwise the low level ('0') is output to the multiplex (142). Is output.

In the multiplex 142, when the output of the comparator 141 is at the high level ('1'), the input In1 is selected and outputted, and when the output of the comparator 141 is at the low level ('0'). An input In2 is selected and output.

The output data of multiplex 142 is stored in register 143, and the data in register 143 is provided to third minimum calculator 16. The second minimum value calculator 15 and the third minimum value calculator 16 operate similarly to the third minimum value comparator.

Therefore, the third minimum value calculator 16 outputs the smallest value among the values output from the shift registers 12 and 13 and the minimum value one step earlier.

The output data of the third minimum calculator 16 is simultaneously input to the register 17 and the arithmetic logic unit 18. At this time, the minimum value one step before is stored in the register 17.

Accordingly, in the arithmetic logic unit 18, the current minimum value output from the third minimum calculator 16 and the minimum value one step before stored in the register 17 are inputted, and a subtraction operation is performed on the two inputs. In addition, the register 17 is updated to a new minimum value output from the third minimum calculator 16.

The difference value between the two minimum values obtained in the arithmetic logic unit 18 is output to the accumulator 19, and in the accumulator 19, the values output from the arithmetic logic unit 18 are accumulated and stored. The value of the accumulator 19 represents the rate of increase of the route metric data.

On the other hand, a comparative logic may be connected to the accumulator 19 to determine whether the received data is valid from the increase rate of the path metric data obtained by the accumulator 19.

The comparison logic is provided with a threshold value for determining whether the reception data is valid, and in the comparison logic, the output value of the accumulator 19 and the threshold value are compared to determine whether the reception data is valid.

In addition, the value of the register 17 is the minimum value so far of the path metric data stored in the shift registers 12 and 13, and the value of the register 17 is provided to the arithmetic logic unit 18, while the Viterbi decoding Can be provided externally for.

Next, a path metric increase rate measuring device according to another embodiment of the present invention will be described with reference to FIGS. 3 and 4.

Unlike the embodiment of the present invention, the path metric increase rate measuring device according to another embodiment of the present invention compares a part of the path metric data to calculate an approximate minimum value, and thereby measures the increase rate of the path metric data.

In particular, another embodiment of this invention utilizes that the route metric data does not differ much from each other.

First, the principle of the path metric increase rate measuring instrument according to another embodiment of the present invention will be described.

The function of the path metric data stored in the i th register at time t is assumed to be PMi (t), and the minimum value when all path metric data is compared at time t is min_i {PMi (t)}.

At this time, the path metric function PMj (t) of the arbitrary j th register at time t is bounded as follows.

Here, if the constraint k + 1 and the value of the branch metric is the maximum D, then C is not greater than kD. The value to be obtained in this invention is min_i {PMi (t)}, and PMj (t) can be used as an approximation.

However, the values of the registers that store the path metric data do not increase continuously because they represent different paths over time, so it is not desirable to measure this value as it is and measure the rate at which the path metric increases.

If the maximum value of the path metric data of the j-th register stored up to that time at time t is max_ (s≤t) {PMj (s)}, it has the following properties.

And

therefore,

Since it can be expressed as, it can be used as an approximation of min_i {PMi (t)}. Also,

Because of, Increases constantly.

finally It can be an approximation of, with some errors, but the error is bounded, and the rate of increase of the path metric can be easily measured by checking the bit transform of the approximation.

In addition, if several path metrics are used instead of one path metric, a more accurate approximation can be obtained.

max_ (s≤t) {min {PMj1 (s)}, PMj2 (s),... }} Has a tighter boundary condition if the path metric is properly selected, and can measure the growth rate of the path metric data with a relatively small hardware complexity.

A path metric growth rate meter following the principle described above is described.

As shown in FIG. 3, the path metric increase rate measuring device according to another embodiment of the present invention includes a register 20 having a predetermined byte of storage space; A minimum calculator 22 coupled to receive two predefined bytes of data in the register 20; A maximum value calculator 24 connected to receive the output data of the minimum value calculator 22 and the maximum value data before one step as feedback; And a counter 26 connected to receive the output data of the maximum calculator 24.

The minimum calculator 22 is shown in detail in FIG. 4A and the maximum calculator 24 in detail in FIG. 4B in the path metric growth rate meter according to another embodiment of this invention described above.

The minimum calculator 22 shown in FIG. 4A is identical in configuration and operation to the minimum calculators 14, 15 and 16 according to the embodiment of the present invention.

The maximum comparator 24 shown in FIG. 4B also has the same components as the minimum calculator 22. However, in the operation of the comparator 241, when the input In2 of the two inputs In1 and In2 is larger, the high level '1' is output, and the multiplex 242 is output from the comparator 241. According to the output high level ('1'), select the larger input and output.

That is, the comparator 241 outputs a high level when the predefined one of the two inputs is larger, and the multiplex 241 selects and outputs the predefined one input when the output of the comparator 241 is high level. do.

Next, referring to FIG. 3, the operation of the increase rate measuring instrument of the path metric will be described.

When power is applied and operation of the circuit starts, data stored in any two bytes of the register 20 is input to the minimum calculator 22.

The minimum value calculator 22 determines the smaller value of the two inputs and outputs the smaller value to the maximum value calculator 24. The maximum value calculator 24 inputs the output data of the minimum value calculator 22 and the maximum value before the fed back step.

The maximum calculator 24 determines the value of the larger of the two inputs, and the determined value is output to the counter 26.

The number of bit conversions of the input data of the counter 26 is counted, and this count value is provided externally.

On the other hand, in order to determine whether the received data is valid, a comparison logic having a predetermined threshold value may be added after the counter 26, and the count value and the threshold value are compared by the comparison logic. It is determined whether the data received by the comparison operation is valid.

On the other hand, even if the error of the path metric increase rate is negligible to some extent, when it is necessary to increase the processing speed at the counter 26, a predetermined bit or less of data output from the maximum calculator 24 is ignored and the data after the predetermined bit is ignored. The number of bit conversions can be counted for. This configuration not only increases the processing speed but also makes the hardware configuration simpler.

As described above and according to the embodiment of the present invention, the path metric data is received at predetermined intervals, the received path metric data is compared by a predetermined byte, and the minimum value is obtained, and the increase rate of the path metric is measured by accumulating the difference between the obtained minimum values. can do.

According to another embodiment of the present invention, only a predetermined byte of each of the various path metric data inputs is read, the minimum value of the read data and the maximum value of the minimum value are sequentially obtained, and the number of bit conversions of the obtained maximum value is counted. As a result, the rate of increase of the route metric can be measured.

In addition, according to embodiments of the present invention and other embodiments, it is possible to determine whether the received data is valid from the rate of increase of the route metric.

Claims (8)

A shift register unit for dividing path metric data supplied periodically into a bundle of a predetermined length and sequentially providing path metric data belonging to each divided bundle one by one; A minimum value calculator for determining a minimum value among path metric data of each bundle provided by the shift register unit and sequentially providing the minimum value; A register for storing data output from the minimum value calculating unit in one step; A detailed logic unit for performing a subtraction operation between the two minimum values to calculate and calculate a difference value between the minimum value provided by the minimum value calculator and the minimum value stored in the register; And an accumulator for accumulating and summing difference values between two minimum values obtained as a result of the operation of the arithmetic logic unit. The path metric increase rate measuring device according to claim 1, further comprising a register provided at the front end of the shift register to store path metric data. The path metric growth rate measuring apparatus of claim 1, wherein the shift register unit comprises at least two shift registers. The apparatus of claim 1 or 2, further comprising a comparison logic connected to a rear end of the accumulator and comparing the output data of the accumulator with a predetermined threshold value to determine whether the received data is valid. Path metric growth meter. 4. The apparatus of claim 1 or 3, wherein the minimum calculator comprises at least two minimum calculators for determining a smaller value among data output from each shift register and a minimum value one step before; A path metric increase rate meter for accepting the output of said at least two minimum value calculators and for determining a minimum among them. 6. The apparatus of claim 5, wherein each of said minimum calculators comprises: a comparator that accepts two inputs and outputs a high level if one of the predefined ones is larger; A multiplex for selecting and outputting an input of a predefined side if the output of the comparator is high level; Path metric growth rate meter, characterized in that consisting of a register for storing the data output from the multiplex. A register for storing a predetermined number of path metric data and refreshed periodically; A minimum calculator for determining a minimum of two path metric data stored at a predetermined position of the register; A maximum value calculator which determines a data having a larger size among the minimum value determined by the minimum value calculator and a maximum value one step before, and outputs the larger data; And a counter for counting the number of bit conversions of the data output from the maximum value calculator and providing a count value equal to the refresh period of the register to the outside. 8. The path metric increase rate measuring instrument according to claim 7, wherein the counter is operable to count bit conversions for data of a predetermined bit or more of data output from the maximum calculator.