KR0153057B1 - Dc offset automatic calibrating apparatus - Google Patents

Abstract

The present invention provides an apparatus for automatically measuring DC offset of a digital signal processing system having an analog / digital converter, a first adder located after the analog / digital converter, a second adder located after the analog / digital converter, and a digital / analog converter. A third adder for adding data continuously outputted from the analog / digital converter and data fed back; A first operation of outputting data output from the third adder and outputting an average value obtained by dividing a value output from the third adder by a predetermined number of times when the data provided by the third adder reaches a predetermined number of times; Transmission means; The digital / analog converter F7 and the first of the data output from the first transmission means at the offset value of the positive component of the second adder and the offset value of the positive component of the analog / digital converter among the data output from the first transmission means. First storage means for storing the offset of the pure digital-to-analog converter subtracted by the offset value of the synthesized (+) component through the two adders and the analog / digital converter; Second storage means for storing an offset value of the analog / digital converter; Second transmission means for selectively providing a signal output from said first and second storage means and a voltage of a ground potential as feedback data of a third adder; A first inverter for inverting the value output from the second storage means; A third transmission for selectively outputting the offset value of the synthesized positive component and the data output from the analog / digital converter through the digital / analog converter, the second adder, and the analog / digital converter output from the first inverter; Way ; A second inverter for inverting the value output from the first storage means; Fourth transmission means for selectively outputting a voltage of the offset value and the ground potential of the digital-to-analog converter output from the second inverter to a second adder; And a fifth transmission means for selectively outputting the offset of the analog-to-digital converter outputted through the first inverter and the voltage of the base potential to the first adder, the digital signal processing system such as an audio codec for multimedia. In order to remove the DC offset generated through the D / A converter and the A / D converter in order to automatically measure the DC offset.

Description

DC offset automatic measuring device

1 is a detailed block diagram of a DC offset automatic measurement apparatus according to the present invention.

2 is an operation timing diagram of FIG.

* Explanation of symbols for main parts of the drawings

101, 103, 105, 107, 108: multiplexer 102: the adder

104: register A 106: register B

IN1, IN2: Inverter

The present invention provides an automatic DC offset in a system such as a codec (COOED) or a multimedia audio codec equipped with a digital / analog converter (hereinafter referred to as an A / D converter) and a digital / analog converter (hereinafter referred to as a D / A converter). And a device for calibrating a DC offset by measuring.

To date, the DC offset measuring device has been mainly implemented in an analog manner. That is, the DC offset generated in the analog OP amplifier is detected by comparing with the reference voltage, and the DC offset is removed by calculating the value of the opposite sign corresponding to the detected DC offset value on the analog.

However, as all electronic devices are digitalized and the devices incorporating A / D converters and D / A converters become commonplace, a digital DC offset measurement device for removing DC offsets generated from A / D converters and D / A converters is required. It became.

Therefore, an object of the present invention is to automatically measure the DC offset in order to remove the DC offset generated through the analog block inside the D / A converter and the A / D converter in a system such as a multimedia audio codec It is to provide a measuring device.

The DC offset automatic measuring device according to the present invention is a DC of a digital processing system having an analog / digital converter, a first adder located after the analog / digital converter, a digital / analog converter and a second adder located after the digital / analog converter. An offset automatic measuring apparatus, comprising: a third adder for adding data continuously outputted from an analog / digital converter and data fed back; Outputting data output from the third adder and outputting the average value obtained by dividing the value output from the third adder by a predetermined number of times when the data provided to the third adder is a predetermined number of times; Transmission means; The digital / analog converter and the first among the data output from the first transmission means at the offset value of the positive component of the second adder and the offset value of the positive component of the analog / digital converter among the data output from the first transmission means. First storage means for storing the offset of the pure digital-to-analog converter subtracted by the offset value of the synthesized (+) component through the two adders and the analog / digital converter; Second storage means for storing an offset value of the analog / digital converter; Second transmission means for selectively providing a signal output from said first and second storage means and a voltage of a ground potential as feedback data of a third adder; A first inverter for inverting the value output from the second storage means; A third transmission for selectively outputting the offset value of the synthesized positive component and the data to be output from the analog / digital converter through the second adder of the digital / analog converter output from the first inverter and the analog / digital converter A second inverter for inverting a value output from the first storage means; a fourth for selectively outputting a voltage of a ground potential and an offset value of the digital / analog converter output from the second inverter to a second adder Transmission means; And fifth transmission means for selectively outputting the voltage of the offset and the ground potential of the analog / digital converter output through the first inverter to the first adder.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a detailed block diagram of a DC offset automatic measuring device according to the present invention applied to a digital system such as a multimedia audio codec, and is transmitted from an unshown analog / digital converter (hereinafter referred to as an ADC) embedded in the digital system. The first multiplexer 101 for selectively outputting the data transmitted through the inverter IN2 to be described later, the first multiplexer 101 outputs the data from the third multiplexer 105 to be described later. A second multiplexer 103 and a second multiplexer (103) for selectively outputting an average value for the adder 102, the data output from the adder 102, and the data transmitted from the adder 102 for a predetermined period of time to add to the data; DAC stores the data output from the register A 104 and the second multiplexer 103, which temporarily stores the data output from the 103 as an ADC offset value. A third multiplexer that selectively outputs the register B 106, the OV level Vss value, and the data output from the registers A 104 and B 106, which are temporarily stored as a preset value, and is fed back to the adder 102 ( 105), selectively outputting the data output from the first inverter IN1 and the first inverter IN1 for inverting the data output from the register A 104 and the above-described Vss to an adder after the DAC not shown. A fourth multiplexer 107 for inputting, a second inverter IN2 for inverting the data output from the register B 106, an adder after the ADC selectively showing the data output from the second inverter IN2 and Vss. And a fifth multiplexer 108 for outputting.

2 is an operation timing diagram of the detailed block diagram of FIG.

Next, the operation of FIG. 1 will be described in detail with reference to the operation timing diagram of FIG.

First, in order to measure the ADC offset value and DAC offset value by measuring the DC offset generated when power-on or all conversions are performed, 16 data transmitted after the first 256 data are taken three times in succession. will be. For this process, the first 16 input data provided from the ADC applied to the first multiplexer 101 are set when the attenuator of the applied system's DAC is set to mute state and the ADC is transmitted with the output of the DAC set to 0. The next 16 input data sets the attenuator of the DAC to 0dB and the DAC offset value outputted from the DAC is provided by adding the DAC offset and the ADC offset as it passes through the ADC. The next 16 input data are outputted from the ADC with the attenuator of the DAC muted and 0 set to input to the ADC.

In this order, the input data provided from the ADC is transmitted to the first multiplexer 101. As shown in part (b) of FIG. 2, the first multiplexer 101 is configured from the time point at which the 0th clock signal of the register clock signal RCLK shown in part (a) of FIG. Select and transmit data to be applied from the ADC not shown. The transmitted data is sent to the adder 102.

The adder 102 adds the data transmitted from the first multiplexer 101 and the data fed back through the third multiplexer 105, which will be described later. The third multiplexer 105 is configured to generate a 0 th clock signal. As shown in (f) of FIG. 2, Vss applied through the input terminal is selected and output. At this time, since Vss has a value of 0V, the adder 102 adds and outputs a value of 0 provided from the third multiplexer 105 to data transmitted from the first multiplexer 101. The output data is transmitted to the second multiplexer 103.

The second multiplexer 103 selects and outputs the data transmitted from the adder 102 during the 0th to 16th clock signal intervals as shown in (c) of FIG. The output data is first transferred to register A 104. Register A 104 stores the stored data to the input terminal (a) of the third multiplexer 105 in synchronization with the register clock signal RCLK shown in (a) of FIG. 2, as shown in (I) of FIG. send.

At this time, the third multiplexer 105 is operated such that the data transmitted from the register A 104 through the input terminal (a) is output as shown in (d) of FIG. The output data is transmitted to the adder 102 and added to the data transmitted from the first multiplexer 101 and then transmitted to the second multiplexer 103 as described above. After the addition process is performed on the 16 input data and the addition (or accumulation) operation on the 16 input data is completed, the second multiplexer 10 ÷ as shown in (c) of FIG. 2. Sixteen passages are operated to be selected. Therefore, the average value obtained by dividing the added value up to 16 by the second multiplexer 103 is output, and the output value is transmitted to and stored in the register A 104. The stored value then becomes the offset and ADC offset of the second adder.

Meanwhile, data output from the ADC transmitted through the first multiplexer 101 is then added with data output from the third multiplexer 105 as described above in the adder 102. In this case, as shown in (f) of FIG. 2, the third multiplexer 105 selects and outputs Vss applied to the input terminal (C). Therefore, the value added by the adder 102 becomes a value output from the first multiplexer 101, and the added value is transmitted through the general passage (accumulation passage) of the second multiplexer 103, and the output value is then output. Is sent to register B 106.

Register B 106 registers the register clock signal RCLK and transmits the stored data to the input terminal (b) of the third multiplexer 105 as shown in FIG. 2 (j). The third multiplexer 105 is operated to output data transmitted to the input terminal (b) as shown in (e) of FIG. The data output from the third multiplexer 105 is added to the adder 102 and the ADC output data transmitted through the first multiplexer 101. This addition operation is repeated 16 times as described above, and if repeated 16 times, an average value is obtained through ÷ 16 channels of the second multiplexer 103. The average value obtained is transferred to register B 106 and stored. At this time, the stored value becomes an offset value which is combined with the offset of the DAC offset, the second adder, and the ADC offset by the above-described conditions.

Then, the ADC offset value stored in synchronization with the register clock signal and the offset of the second adder are transmitted to the adder 102 through the input terminal (a) of the third multiplexer 105, and at the same time, The DAC offset and ADC offset and the offset value of the second adder that were stored in B 106 are provided to the adder 102 through the first multiplexer 101 through the second inverter IN2.

Adder 102 adds the two applied data but substantially subtracts the value stored in register B 105 from the value stored in register A 104. Therefore, the value output from the adder 102 becomes a -DAC offset value. The subtracted value is stored in the register A 104 through the second multiplexer 103 and outputted through the inverter IN1 and the fourth multiplexer 107 in synchronization with the register clock signal. As shown in (g) of FIG. 2, the fourth multiplexer 107 selects and outputs V _SS during the measurement operation period for 32 data, and when the measurement operation is completed, the DAC transmitted through the first inverter IN1. The offset value is selected and transmitted to the adder behind the DAC. Accordingly, the adder at the rear end of the DAC, which is not shown, can remove the offset generated in the DAC when the system operates normally after the offset measurement is finished.

After this operation, the first data transmitted through the first multiplexer 101 and the zero of the third multiplexer 105 are added by the adder 102, and the added data is registered through the second multiplexer 103. Is sent to 106. The register B 106 feeds the transmitted data back to the adder 102 through the path of the third multiplexer 105 through the path of (b) and adds 16 data cumulatively 16 times by adding the data to the next applied data. The cumulatively added data is stored in the register B 106 by obtaining an average value through the ÷ 16 paths in the second multiplexer 103. At this time, the stored value becomes the ADC offset according to the above-described input data condition. The data stored in the register B 106 is supplied to the adder after the ADC not shown through the second inverter IN2 and the fifth multiplexer 108. Accordingly, the offset generated in the ADC not shown is removed as in the offset cancellation generated in the above-described DAC.

As shown in (h) of FIG. 2, the fifth multiplexer 108 selects and transmits a Vss value during the transmission of the clock signal for the 48th data, and then selects the second inverter (IN2) at the rising edge of the 49th clock signal. Select the output signal from) and output it.

As described above, the DC offset automatic measuring device of the present invention uses the data generated after 256 data generated when the operation such as power-on or mode conversion is performed in the digital signal processing system three times in succession in 16 data units. By automatically calculating the DC offset value and providing it to the adder at the rear of the ADC and the adder at the rear of the ADC, the DC offset value can be removed, thereby improving the performance of the applied system.

Claims (4)

A DC offset automatic measurement apparatus for a digital signal processing system having an analog / digital converter, a first adder located at the rear of the analog / digital converter, a digital / analog converter and a second adder located at the rear of the digital / analog converter. A third adder for adding data continuously outputted from the digital converter and data fed back; A first operation of outputting data output from the third adder and outputting an average value obtained by dividing a value output from the third adder by a predetermined number of times when the data provided by the third adder reaches a predetermined number of times; Transmission means; A digital / analog converter and a first one of the data output from the first transmission means at the offset value of the positive component of the second adder and the offset value of the positive component of the analog / digital converter among the data output from the first transmission means. First storage means for storing the offset of the pure digital-to-analog converter subtracted from the combined offset value of the synthesized positive component through the two adders and the analog-to-digital converter; Second storage means for storing an offset value of the analog / digital converter; Second transmission means for selectively providing a signal output from said first and second storage means and a voltage of a ground potential as feedback data of a third adder; A first inverter for inverting the value output from the second storage means; A third for selectively outputting the offset value of the positive component synthesized through the digital / analog converter, the second adder and the analog / digital converter output from the first inverter and the data output from the analog / digital converter; Transmission means; A second inverter for inverting the value output from the first storage means; Fourth transmission means for selectively outputting an offset value of the digital-to-analog converter output from the second inverter and a voltage of a ground potential to a second adder; And a fifth transmission means for selectively outputting a voltage of an offset and a ground potential of the analog / digital converter output through the first inverter to the first adder. The apparatus of claim 1, wherein the first to fifth transmission means comprise a multiplexer. The digital / analog system according to claim 1, wherein the data output from the analog / digital converter is divided into the first predetermined number of input data for the three operations by setting the attenuator of the digital / analog converter to mute state. When the output of the converter is set to 0, the data is output from the analog / digital converter when the analog / digital converter is transmitted. The second predetermined number of input data sets the attenuator of the digital / analog converter to 0 dB. The offset value output from the analog converter is obtained by adding the offset of the digital / analog converter and the offset of the analog / digital converter while passing through the analog / digital converter, and the third predetermined number of input data is the digital / analog converter. Mute the attenuator at DC offset automatic measuring device characterized in that the output data from the analog / digital converter in the state set to be input to the de-converter. The apparatus of claim 1, wherein the apparatus for automatically measuring a DC offset further includes a second inverter for inverting the value output from the first storage means and providing the input signal as one input signal of the fourth transmission means. DC offset automatic measuring device.