KR0151915B1 - Adaptor transmitting and receiving apparatus for both atm and ethernet - Google Patents

Abstract

The present invention relates to an ATM / Ethernet adapter transceiver device, which is the most widely used and inexpensive Ethernet 10 BASE-T adapter and is currently being standardized in the ITU-T and ATM forums. Adapter for low-cost twisted pair cable connection in one board allows users to connect to both Ethernet and ATM networks by user's choice, and automatically switches modes by detecting ATM carrier or Ethernet carrier even when receiving data It can be applied to PC or workstation network connection device or communication system network connection device as ATM transceiver for twisted pair cable and Ethernet LAN adapter that can automatically receive data regardless of Ethernet network or ATM network. have.

Description

Asynchronous Transfer Mode with Ethernet Adapter Transceiver

1 is a block diagram of an ATM and an Ethernet adapter transceiver according to the present invention;

2 is a block diagram of an ATM adapter transceiver according to the present invention.

3 is a block diagram of an Ethernet adapter transceiver according to the present invention.

* Explanation of symbols for main parts of the drawings

11: PC / Workstation Bus Interface

12: ATM adapter transceiver 13: Ethernet adapter transceiver

14 Relay switch 15 RJ-45 connector for twisted pair

The present invention relates to an asynchronous transfer mode (ATM) and an adapter for both Ethernet and Ethernet /

Conventional Ethernet adapter device can be connected only to the Ethernet network, and when the 10BASE 5 or 10BASE 2 connection using a coaxial cable is expensive and the flexibility of the line has a disadvantage of difficult handling. In addition, the ATM adapter device can be connected only to the ATM network, and when the connection using the optical path is expensive, the use of an optical module is expensive and the flexibility of the optical path is low, making it difficult to handle.

By the way, the future communication network will be developed into a mixture of the existing Ethernet network and ATM (Asynchronous Transfer Mode) network that can accommodate a variety of information such as voice, data as well as video. The Ethernet network can be connected to 10Base 5 (Thick Coaxial Cable), 10Base 2 (Thin Coaxial Cable), and 10Base-T (Twisted Pair Cable) connection, and it is inexpensive and convenient to use as an adapter device for a PC or workstation. Mainly use 10Base-T adapter device for twisted pair. ATM network can be connected to Single Mode Fiber, Multi Mode Fiber, and Twisted Pair Cable, but it is a cheap and convenient twist adapter for PC or workstation adapter devices. An adapter device is required. In addition, Ethernet network connection in LAN (Local Area Network) environment is most used at present, but speed is 10Mbps, and ATM network connection is fast, but it is not widely used yet. The price is expensive.

The present invention devised to solve all the problems of the prior art, the Ethernet 10 BASE-T adapter device currently used most and the adapter device for twisted pair cable connection of ATM networks to be developed in the future mounted in one board Mode can be switched to ATM adapter device or Ethernet adapter device by user's choice. ATM data using twisted pair cable by detecting mode of ATM carrier or Ethernet carrier and switching mode automatically when receiving data. An object of the present invention is to provide an ATM and an Ethernet adapter transceiver that can be used as a LAN or an Ethernet LAN adapter.

In order to achieve the above object, the present invention, the PC / workstation bus interface means for interfacing the expansion bus (Expansion Bus) of a slot (PC) embedded in a personal computer (PC) or workstation; An ATM adapter transmission / reception means connected to the PC / workstation bus interface means for converting transmission data of a CPU in a workstation into received data so that an ATM cell can be transmitted to an ATM network through a twisted pair cable; An Ethernet adapter transmitting and receiving means connected to said PC / workstation bus interface means for converting transmission data of said CPU into received data so that Ethernet frame data can be transmitted to said Ethernet network through a twisted pair cable; Relay switching means for selectively connecting to said ATM adapter transmission / reception means and said Ethernet adapter transmission / reception means by input ATM differential received data; Twisted pair RJ-45 connection means for connecting a twisted pair cable to the ATM network or Ethernet network through the relay switching means in accordance with the input signal from the ATM adapter transmission and reception means and the Ethernet adapter transmission and reception means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of an ATM and an Ethernet adapter transceiver, in which FIG. 11 is a PC / workstation bus interface, 12 is an ATM adapter transceiver, 13 is an Ethernet adapter transceiver, 14 is a relay switch, and 15 is a twisted pair RJ. -45 connectors are shown respectively.

As shown in the figure, the PC / workstation bus interface unit 11 is a personal computer (Person).

al Computer) or an expansion bus of a slot embedded in a workstation is connected to an ATM adapter transceiver 12 and an Ethernet adapter transceiver 13. That is, the address adapter, the data bus, the control signal, the interrupt signal, and the system clock signal are provided from a central processing unit (CPU) in the PC / workstation to control the ATM adapter transceiver 12 and the Ethernet adapter transceiver 13. Monitor the state of negative operation. In addition, when accessing the ATM network by the user's selection, the ATM adapter enable signal is enabled (TTL level 1) to enable the ATM adapter transceiver 12 to operate normally and the relay switch is initially turned on. , Pins 5 and 6 of 14) are connected to pins 3 and 4 so that pins 5 and 6 are connected to pins 1 and 2. The ATM adapter control signal receives various control signals such as an address, a read signal, and a write signal from a CPU in the workstation and connects only signals necessary for controlling the ATM adapter transceiver 12. In addition, when the twisted pair RJ-45 connector 15 is connected to the ATM network through a twisted pair cable, an ATM carrier is received at ATM differential reception data 1 and 2 of the ATM adapter transceiver 12, and the signal is recalled. The ATM adapter transceiver 12 converts the CPU so that the CPU can recognize the ATM carrier detection signal. This signal is connected to the interrupt signal of the CPU to generate an interrupt to the CPU so that the CPU immediately knows the reception of the ATM carrier and sends the ATM adapter enable signal of the PC / Workstation bus interface unit 11. By enabling TTL level 1, the ATM adapter transceiver 12 operates normally and the pins 5 and 6 of the relay switch 14 are switched to be connected to the pins 1 and 2. The system clock signal supplies a system clock from the CPU to the ATM adapter transceiver 12 to be used as a main operation clock of the ATM adapter transceiver 12. The data bus transmits data between the CPU and the ATM adapter transceiver 12. Depending on the capacity, it can be connected to an 8 or 16 or 32 bit (Bits) data bus. In addition, the PC / workstation bus interface unit 11 supplies a system clock from the CPU to the Ethernet adapter transceiver 13 to use as the main operation clock of the Ethernet adapter transceiver 13 and the data bus is the CPU and the Ethernet adapter transceiver Depending on the data transfer capability of (13), they are connected by 8 or 16 or 32 bit (Bits) data buses. When the user connects to the Ethernet network, the Ethernet adapter enable signal is enabled to TTL level 0 to operate the Ethernet adapter transceiver 13 normally and pins 5 and 6 of the relay switch 14 to pin 3. Switch to connect with, 4. The Ethernet adapter control signal receives various control signals such as an address bus, a read signal, and a write signal from the CPU, and connects only signals necessary for controlling the Ethernet adapter transceiver 13. In addition, when the twisted pair RJ-45 connector 15 is connected to an Ethernet network through a twisted pair cable, an Ethernet carrier is received from Ethernet differential reception data 1 and 2 of the Ethernet adapter transceiver 13. The Ethernet adapter transceiver 13 converts the signal so that the CPU can recognize the Ethernet carrier detection signal. This signal is connected to the interrupt signal of the CPU to generate an interrupt to the CPU so that the CPU can immediately recognize the reception of the Ethernet carrier and enable the Ethernet enable signal of the PC / Workstation bus interface unit 11 to TTL level 0. The Ethernet adapter transceiver 12 is operated normally and the pins 5 and 6 of the relay switch 14 are switched to be connected to the pins 3 and 4. The ATM adapter transceiver 12 converts the CPU data into an ATM cell form so that the ATM cell can be transmitted through a twisted pair RJ-45 connector 15 and performs a data scrambling function and a line encoding function. Converts the ATM differential transmission data 1, 2 to the relay switch 14 and transmits the ATM differential reception data 1, 2 received from the twisted pair RJ-45 connector 15 with a line decoding function and a line decoding function. A scrambling function and a reassembly function of an ATM cell are performed to convert the data into CPU data.

The Ethernet adapter transceiver 13 converts Ethernet frame data into Ethernet frames so that Ethernet frame data can be transmitted to the Ethernet network through the RJ-45 connector 15 for twisted pair. Is transmitted to the RJ-45 connector 15 for the twisted pair and recombines the Ethernet differential receiving data 1, 2 received from the relay switch 14 to CPU data.

The relay switch 14 is initially turned on the ATM adapter enable signal is disabled (TTL level 0) (Disable), pins 5, 6 are connected to pins 3, 4, the twisted pair RJ-45 connector (15) Receive Ethernet differential receive data 1,2. In addition, ATM adapter enable signal is enabled to TTL level 1 when ATM carrier is detected from ATM differential receiving data 1,2 when the user selects the ATM network, and pins 5 and 6 are connected to pins 1 and 2 to make ATM differential. Transmission data 1 and 2 are transmitted to the twisted pair RJ-45 connector 15.

The twisted pair RJ-45 connector 15 performs a function of connecting a twisted pair cable to an ATM network or an Ethernet network.

2 is a block diagram of an ATM adapter transceiver, in which 21 is an ATM layer protocol processing unit, 22 is a twisted pair physical layer controller, 23 is a twisted pair matching transceiver, 24 is an oscillator, and 25 is an ATM line transformer. Represent each.

1 illustrates the operation of the ATM adapter transceiver 12 in detail, the ATM layer protocol processor 21 receives the system clock from the PC / workstation bus interface unit 11 of FIG. When receiving the ATM adapter enable signal, the TTL level 1 performs normal operation, and the TTL level 0 becomes a standby state. The ATM adapter control signals are various control signals such as an address bus, a read signal, a write signal, and the like of the CPU, and the CPU controls the ATM layer protocol processing unit 21 using the ATM adapter control signals.

In addition, after receiving CPU data from the CPU and converting it into an ATM cell form, the ATM layer transmission data is transmitted to the twisted pair physical layer controller 22 in synchronization with the ATM layer transmission clock (3.2 MHz), and the ATM layer control signal is described above. The twisted pair physical layer controller 22 enables or sets a mode and receives state information from the twisted pair physical layer controller 22.

The ATM layer protocol processor 21 receives ATM layer received data in synchronization with an ATM layer reception clock (32.MHz), removes an ATM cell header, reassembles the data, and then CPU data to the CPU. Send.

The twisted pair physical layer controller 22 receives a local clock (32 MHz) from the twisted pair transceiver 23 and uses it as a main clock, and scrambles ATM layer transmission data and encodes 4B / 5B symbols. And physical layer transmission data subjected to data serial conversion and Non Return to Zero Invert (NRZI) shape conversion are transmitted to the twisted pair matching unit 23 for the twisted pair in synchronization with the physical layer transmission clock (32 MHz). The wait signal causes the twisted pair matching transmission / reception unit 23 to be in a standby state when the TTL level is 0 and operates normally when the TTL level 1 is used. Also, the physical layer reception data synchronized with the physical layer reception clock (32 MHz) is received from the transmission / reception matching unit 23 for twisted pair to perform NRZ (Non Return to Zero) shape conversion, 5B / 4B symbol decoding, and descrambling. The ATM layer reception data is made to be transmitted to the ATM layer protocol processing unit 21. At this time, if the physical layer reception data is valid data, the ATM carrier detection signal is enabled at TTL level 1 and disabled at TTL level 0.

The transmission / reception matching unit 23 for the twisted pair receives a 32 MHz clock signal from the oscillator 24 and uses it as the main operation clock, and receives the physical layer transmission data from the physical layer control unit 22 for the twisted pair to obtain a twisted pair. In order to improve the data transmission capability, the ATM differential transmission signals 1 and 2 converted into differential signals are transmitted to the ATM line transformer 25. In addition, the ATM differential receiving signals 1, 2 are received from the ATM line transformer 25, a physical layer reception clock (32 MHz) is extracted by a phase locked loop (PLL), and the ATM differential receiving signals 1, 2 are unipolar (Unipola). ) Is transmitted to the physical layer control unit 22 for the twisted pair together with the physical layer reception data converted into the signal. The oscillator 24 self-generates a 32 MHz clock and supplies it to the transmission / reception matching unit 23 for twisted pair.

The ATM line transformer 25 receives ATM differential transmission signals 1 and 2 from the twisted pair transmission / reception matching unit 23, and performs ATM differential transmission data 1 which is impedance-matched for power supply separation from the terminal side and twisted pair cable. , 2 is transmitted to the relay switch 14. In addition, ATM differential reception data 1 and 2 received from the twisted pair RJ-45 connector 15 are separated from the network side and the power is disconnected from the ATM side. , 2 is transmitted to the transmission / reception matching unit 23 for the twisted pair.

3 is a block diagram of Ethernet adapter transmission and reception, in which 31 is a CSMA / CD LAN control unit, 32 is a shared memory, 33 is an Ethernet serial interface unit, 34 is an oscillator, and 34 is an Ethernet line transformer.

Referring to the drawings will be described in more detail the operation of the Ethernet adapter transceiver 13 as follows.

The CSMA / CD LAN control unit 31 performs CSMA / CD MAC (Medium Access Control) function and receives the system clock from the PC / workstation bus interface unit 11 of FIG. When the TTL level 0 is received and the enable signal is received, normal operation is performed. When the TTL level 1 is reached, the standby state is reached. The Ethernet adapter control signals are various control signals such as an address bus, a read signal, and a write signal of the CPU. The CPU controls the CSMA / CD LAN control unit 31 and the shared memory 32 using the Ethernet adapter control signals. In addition, the CPU stores CPU data in the shared memory 32, and the CSMA / CD / LAN controller 31 reads the CPU data from the shared memory 32, converts the CPU data into an Ethernet frame, and then requests Ethernet transmission. The Ethernet transmission data is transmitted to the Ethernet serial interface unit 33 in synchronization with the Ethernet transmission clock (10 MHz) while enabling the signal to TTL level 0. In addition, after receiving the Ethernet reception data synchronized with the Ethernet reception clock (10MHz) from the Ethernet serial interface unit 33 to extract the data in the form of Ethernet frame (Frame) as CPU data, the shared memory 32 as a shared memory control signal ) And the shared data as a storage element that both the CPU and the CSMA / CD LAN control unit 31 can access.

The Ethernet serial interface unit 33 receives the 20 MHz clock signal from the oscillator 34 and uses it as the main operation clock. The Ethernet serial interface unit 33 receives the Ethernet transmission data from the CSMA / CO LAN control unit 31 and transmits the data through the twisted pair. Ethernet differential transmission signals 1, 2, 3, and 4 converted into differential signals are transmitted to the Ethernet line transformer 35 to improve transmission capability, wherein the Ethernet differential transmission signals 3 and 4 are obtained by using the Ethernet differential transmission signals 1 and 2, respectively. Inverted signal.

In addition, the Ethernet differential reception signal 1, 2 is received from the Ethernet line transformer 35, the Ethernet reception clock (10 MHz) is extracted by PLL (Phase Locked Loop), and the Ethernet differential reception signals 1, 2 are unipolized (Unipola). Along with the Ethernet received data converted into a signal is transmitted to the CSMA / CD LAN control unit 31. At this time, if the Ethernet reception data is valid data, the Ethernet carrier detection signal is enabled at TTL level 0, and if it is invalid, it is disabled at TTL level 1.

The oscillator 34 self-generates a 20 MHz clock and supplies it to the Ethernet serial interface unit 33.

The Ethernet line transformer 35 receives the Ethernet differential transmission signals 1 and 2 from the Ethernet serial interface unit 33 and performs Ethernet impedance transmission data 1 and impedance matching for power separation from the terminal side and twisted pair cable. 2 is transmitted to the twisted pair RJ-45 connector 15 of FIG. In addition, the Ethernet differential receiving data 1, 2 received from the relay switch 14 is separated from the network side, and the Ethernet differential receiving signals 1, 2 converted into a terminal connection signal after impedance matching for a twisted pair cable are converted into the Ethernet serial interface. Transfer to section 33.

As described above, the present invention is one of the most widely used and inexpensive Ethernet 10BASE-T adapters and one adapter device for low-cost twisted pair cable connection of ATM networks that is currently being standardized in the ITU-T and ATM forums and will be spread in the future. It can be connected to both Ethernet network and ATM network by user's choice by installing on board, and it automatically detects ATM carrier or Ethernet carrier and receives mode automatically when receiving data, regardless of Ethernet network or ATM network. As an adapter for both a twisted pair cable ATM LAN and an Ethernet LAN that can receive data, it can be applied to a network connection device of a PC or workstation or a network connection device of a communication system.

Claims (5)

PC / Workstation bus interface means for interfacing an expansion bus of slots built into a personal computer or workstation in an asynchronous transfer mode (ATM) and an ethernet adapter transceiver (11) ); An ATM adapter transmitting and receiving means (12) connected to said PC / workstation bus interface means (11) for converting transmission data of a CPU in a workstation into received data so that an ATM cell can be transmitted to an ATM network through a twisted pair cable; An Ethernet adapter transmitting / receiving means (13) connected to said PC / workstation bus interface means (11) for converting transmission data of said CPU into received data so that Ethernet frame data can be transmitted to said Ethernet network through a twisted pair cable; Relay switching means (14) for selectively connecting the ATM adapter transmission / reception means (12) and the Ethernet adapter transmission / reception means (13) by means of input ATM differential reception data; A twisted pair RJ-45 connection for connecting a twisted pair cable to an ATM network or an Ethernet network through the relay switching means 14 in accordance with input signals from the ATM adapter transmission / reception means 12 and the Ethernet adapter transmission / reception means 13. Adapter for transmitting and receiving asynchronous mode and Ethernet characterized in that it comprises a means (15). The ATM layer protocol of claim 1, wherein the ATM adapter transmitting and receiving means 12 receives CPU data through the PC / workstation bus interface means 11, converts the CPU data into an ATM cell form, and then transmits and receives ATM layer related signals. A processor 21; The twisted pair is connected to the ATM layer protocol processing unit 21 and converts an ATM layer related signal into a physical layer control signal for a twisted pair and transmits the data, and forms an ATM layer reception data for transmission to the ATM layer protocol processing unit 21. A physical layer controller 22; Receives a clock signal from the generator 24, the physical layer transmission data from the twisted pair physical layer control unit 22 receives and transmits to the physical layer control unit 22 through the twisted pair for the twist pair transmission and reception matching unit 23 ); ATM differential transmission signal from the twisted pair transmission / reception matching unit 23 is converted into a twisted pair transmission signal and transmitted to the relay switching means 14, and the ATM is received from the twisted pair RJ-45 connection means 15. ATM line transformer 25 which transmits the differential reception data converted into the terminal connection signal to the twisted pair transmission / reception matching unit 23. The asynchronous transmission mode and the Ethernet adapter are transmitted and received. Device. The apparatus of claim 2, wherein the oscillator 24 is a 32 MHz clock oscillator. The method of claim 1, wherein the Ethernet transmission and reception means 13, the CSMA / CD MAC (Medium Access Control) receives the Ethernet adapter enable signal from the PC / workstation bus interface means 11, the CPU is not described Read the CPU data stored in the shared memory 32, convert it into an Ethernet frame, and transmit it as Ethernet transmission data, extract Ethernet data from the Ethernet frame, and extract the data into CPU data. A CSMA / CD LAN control unit 31 for storing in the memory 32; A shared memory 32 for storing shared data for both the CPU and the CSMA / CD LAN control unit 31 to write and read; Receives a clock signal from the oscillator 34, receives the Ethernet transmission data from the CSMA / CD LAN control unit 31 and transmits the Ethernet differential transmission signal converted into a differential signal through a twisted pair, and converts the Ethernet differential reception signal to the An Ethernet serial interface unit 33 for transmitting to the CSMA / CD LAN control unit 31; Receives the Ethernet differential transmission signal from the Ethernet serial interface unit 33, converts it into Ethernet differential transmission data, transmits it to the twisted pair RJ-45 connecting means 15, and receives the Ethernet differential received from the relay switch 14. And an Ethernet line transformer (35) for converting data into a terminal connection signal and transmitting the data to the Ethernet serial interface unit (33). 5. The apparatus of claim 4, wherein the oscillator is a 20 MHz clock oscillator.