KR0151911B1 - Cell gap control apparatus and method for controlling through put band in atm network - Google Patents

Abstract

The present invention relates to an apparatus and a method for controlling cell spacing for output band control in an ATM network, comprising: cell buffering means (10) for storing a cell; Address FIFO means (30) for managing an active address of said cell buffering means (10); Idle address FIFO means (20) for managing unused addresses of the cell buffering means (10); Cell state display memory means 41 for storing a cell state of each channel; Predetermined transmission time (NDT) calculating means (42) for calculating an estimated transmission time of a cell by using the value of said cell state display memory means (41); Scheduling means 46 for registering a scheduled transmission time of a cell that has arrived for spacing of the cell; Output linked list (OLL) memory means 45 for managing cells registered in the same entry of the scheduling means 46; An output list start (OLH) memory means (43) for storing the virtual channel identifier (VCI) in front of those registered in the scheduling means (46) at the end of the transmission time; And an output list end (OLT) memory means 44 for storing the virtual channel identifier (VCI) at the end of the transmission time which is registered in the scheduling means 46, for cell buffering. Accurate maximum cell rate using cell spacing algorithms based on maximum cell rate (PCR) per channel with a more robust to error than the linked list method There is an effect that can guarantee.

Description

Cell spacing control device and method for output band control in ATM network

1 is an exemplary diagram in which the present invention is applied to an ATM network.

2 is a block diagram of a cell gap control apparatus according to an embodiment of the present invention.

3 is a block diagram of a schedule management unit according to an embodiment of the present invention.

4 is a diagram illustrating the logical operation of the present invention.

5 is a used spacing flowchart of the present invention.

6 is a diagram illustrating a transmission time scheduling operation according to an embodiment of the present invention.

7 is a flowchart illustrating an update of output list start and output list end values according to an embodiment of the present invention.

8 is an overall flowchart according to an embodiment of the present invention.

9 is a flowchart of a scheduling process according to an embodiment of the present invention.

10 is a flowchart illustrating input cell processing according to an embodiment of the present invention.

11 is a flowchart illustrating an update process of output list start and output list end values according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: cell buffer unit 20: idle address FIFO

30: address FIFO 40: schedule management unit

The present invention relates to an apparatus and method for controlling cell spacing for output band control in an ATM network. In particular, CBR (Continuous Bit Rate) traffic is transmitted in a ATM network due to cell delay variation (CDV). The present invention relates to a cell spacing control device and a method for preventing a change in characteristics or a concentration of cells to a specific output port of a switch to change characteristics of source traffic to transmit over a predetermined band or to affect other channels.

In ATM networks, spacing is performed between successive cells so that they do not exceed the maximum negotiated peak cell rate (PCR) when establishing a connection by providing a constant interval between cells when each successive cell enters the network. Should be

Acceptance of a new connection request in an ATM network is determined based on traffic parameters negotiated between the user and the network at call establishment. Surveillance, known as usage parameter control (UPC), monitors the user's traffic for good compliance with the negotiated parameter values for the duration of the connection. In the early stages of ATM, this UPC function is the maximum cell rate (PCR) of the connection. Surveillance control is performed based on this. Cell Delay Variation (CDV) due to multiplexing of data cells and insertion of Operation And Maintenance (OAM) cells changes the characteristics of the source traffic, making the cells smaller than normal, increasing the maximum cell rate (PCR), and bursting. Make the burstiness above a certain value. Due to the effect of CDV, cell-space spacing is essential for CBR traffic such as voice and video, which is affected not only by cell delay but also by the arrival interval between cells. Do.

In addition, output contention occurs when cells are concentrated in the switch's characteristic output port, which delays the transmission time and changes the cell spacing accordingly. A method for appropriately controlling the spacing of these cells is a spacing method for maintaining a constant time between transmissions of consecutive cells. In addition, even in a connectionless server used to support connectionless communication such as a local area network (LAN) through an ATM network, an interval control device is required to properly control an output band. In other words, in the early stages of ATM networks, a connectionless server is a permanent virtual connection with other connected servers, so when cells routed from a server need to be concentrated to a specific output port and transmitted over a fixed band, It also affects other channels, leading to performance degradation, so the interval control function must be provided for output band control. In addition, the UPC function in the subscriber matching device of the switch if the ATM switching system with the connectionless service function retransmits by simply transforming the cell header without output band control when the data traffic burst to the specific output virtual connection of the server is concentrated. Many cell losses can occur. Therefore, the ability to control the output band of the connectionless server is required.

The cell spacing control device controls the cell spacing based on the maximum cell rate negotiated between the user and the network when establishing a connection for each channel. The cell order must be guaranteed on the same channel. The simplest structure of the cell gap control device is to use a separate buffer for each channel, that is, to use a multi-queue, so that the control is simple, but the buffer for storing cells for each channel must be set separately. The disadvantage is that the size becomes too large.

SPACING POLICER (XIV International Switching Symposium, pp.22-25, October, 1992), proposed by E. Wallmeier and T. Worster, uses the memory address of the actual cell and the next cell to reduce the memory size of the cell gap controller. The disadvantage is that the next cell cannot be found when the link is broken because the linked list method is used by grouping it into one storage unit. Because of the way that the next transmission time of the cell is determined at the moment it is stored at, an output collision occurs when several different channels simultaneously point to the same output port during one slot, causing only one cell to be transmitted at that time and the remaining cells. Are delayed to the next slot. Considering this phenomenon only for certain channels, it is strictly higher than the maximum cell rate (PCR) used by UPC, that is, the time interval between cells is smaller than the minimum inter-interval time (MIT). As a result, it can be regarded as a cell violated by the UPC mechanism that monitors the maximum cell rate.

In addition, a cell supervisory control device with a spacing function proposed by HJ Chao in the paper Design of Leaky Bucket Access Control Schemes in ATM Networks (ICC, pp.180-187,1991) is used to schedule and manage the transmission time of a cell. We proposed a device called Sequencer. The sequencer transmits the transmission time between cells so as not to exceed the maximum cell rate (PCR), and in order to equalize the cell transmission order between channels, the transmission time of the cells is constantly stored in ascending order. It is configured to transmit in order. However, it is not easy to implement a new cell between cells already stored in order to match the transmission order of cells in the sequencer, and the algorithm used to control the transmission order between each channel and the transmission time between cells is also difficult. There is a complicated problem.

Therefore, in order to solve the above problems of the prior art, the present invention can considerably reduce the memory size for cell buffering than when using the multi-queue, has a structure that is more robust to errors than the link list method, and has a structure It is an object of the present invention to provide an apparatus and method for controlling cell spacing that can guarantee an accurate maximum cell rate using a cell spacing algorithm based on a maximum cell rate (PCR).

The present invention for achieving the above object is a cell buffering means for storing a cell; Address FIFO means for managing an active address of the cell buffering means; Idle address FIFO means for managing unused addresses of the cell buffering means; Cell state display memory means for storing a cell state of each channel; Predetermined transmission time (NDT) calculating means for calculating an estimated transmission time of a cell by using the value of said cell state display memory means; Scheduling means for registering a scheduled transmission time of a cell that has arrived for spacing of the cell; Output linked list (OLL) memory means for managing cells registered in the same entry of the scheduling means; An output list start (OLH) memory means for storing a virtual channel identifier (VCI) at the forefront of those whose transmission time has expired, among which the scheduling means have been registered; And an output list end (OLT) memory means for storing a virtual channel identifier (VCI) at the end of those registered in the scheduling means at the end of the transmission time.

Further, a cell buffering means for storing a cell, an address FIFO means for managing an active address of the cell buffering means, an idle address FIFO means for managing an unused address of the cell buffering means, and a schedule related to spacing of a cell A cell spacing control method for output bandwidth control in an ATM network applied to a cell spacing controller configured as a schedule management means, the output list starting by checking an output list start (OLH) value for every slot for cell transmission (OLH) A first step of checking whether the value is greater than '0'; If the output list start (OLH) value is greater than '0' in the first step, the cell stored in the cell buffering means is transmitted using the value of the corresponding address FIFO means indicated by the output list start (OLH) value, and the cell status is displayed. A second step of checking whether the transmitted buffer is empty after updating the last transmission time (LDT) value of the memory means; If the state of the buffer transmitted in the second step is not empty, the scheduling processing routine for the next cell of the buffer is performed. If the buffer is empty, the buffer state indication (BEI) bit of the cell state display memory means is set to ' Setting to 1 'and checking whether there is a cell input to the cell gap controller; A fourth step of indicating that there is no cell to transmit in the corresponding slot if the output list start (OLH) value is not greater than '0' in the first step, and checking whether there is a cell input to the cell interval controller; And a routine for updating an output list start (OLH) value and an output list end (OLT) value after performing an input cell processing routine when there is a cell input to the cell spacing controller in the third or fourth step. And performing a routine of updating an output list start (OLH) value and an output list end (OLT) value if there is no input cell.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 shows an exemplary diagram in which the present invention is applied to an ATM network.

In the figure, (A) is an example applied to an output buffer type ATM switching system, each output port has a buffer, and the cell gap control apparatus of the present invention is applied to control the cell gap in the buffer.

And, (B) is applied to an ATM switching system having a connectionless service function, the ATM switching system is composed of an ATM switching function having a function for exchanging ATM cells and a connectionless server that processes the connectionless data. The connectionless data sent from the ATM subscriber is sent to the connectionless server through the ATM exchange function, which is then processed by the server and buffered at the server's output for transfer to another exchange or subscriber via the ATM exchange function. At this time, the interval control device is used to control the output band of the server.

(C) is an exemplary diagram for output band control when a connectionless server is placed in an ATM network to service connectionless data. The initial connectionless connection between the server and the server uses a fixed virtual link (PVC), so the server controls the output band so that the cells that have been routed and converted to cell headers are transmitted over the limited band of the fixed virtual link (PVC). Should.

FIG. 2 is a block diagram of an apparatus for controlling cell spacing according to an embodiment of the present invention, wherein 10 is a cell buffer unit, 20 is an idle address FIFO, 30 is an address FIFO, and 40 is a schedule manager.

An apparatus for controlling cell spacing according to the present invention includes a cell buffer unit 10 for storing a cell, an address FIFO 30 for managing an active address of the cell buffer unit 10, and an unused address for the cell buffer unit 10. It is composed of an idle address FIFO 20 and a schedule manager 40 associated with spacing of cells. Here, the cell buffer unit 10 uses a shared buffer, and the address FIFO 30 uses a separate buffer for each channel. The cell entering the cell spacing controller is buffered in the cell buffer unit 10. The place where the cell buffer unit 10 is stored receives the idle address in the idle address FIFO 20 and stores it in the cell buffer unit 10. The address is stored in the corresponding channel of the address FIFO 30. The scheduled transmission time of each cell is determined by the schedule manager 40, and when the predetermined time is reached, the cell is output from the cell interval controller.

3 is a diagram illustrating a schedule management unit according to an embodiment of the present invention.

The schedule manager 40 outputs a connection for managing cells registered in the same entry of the scheduler 46 and the scheduler 46 for registering the scheduled transmission time of the cell entered into the cell interval control apparatus. List (OLL: Output Linked List) The output list head (OLH: Output List Head), each of which is registered in the memory 45 and the scheduler 46, showing the first and the last of the transfer timed ones, respectively. The scheduled transmission time of the cell is registered in order to register the memory 43 and the output list tail (OLT) memory 44 and the cell state display memory 41 and the scheduler 46 indicating the cell state of each channel. And a next transmission time (NDT) calculation unit 42 for calculating.

Since the scheduler 46 may register two or more cells in the same time zone, the scheduler entry head (SEH) 47 and the scheduler entry end (SET: Scheduler) to indicate the start and end of the registered one, respectively. Entry Tail) 48 fields. The cell status indication memory 41 has a Last Departure Time (LDT) field, a Minimum Interarrival Time (50) field used to calculate a scheduled transmission time, and a cell interval between cells. When the controller enters the control device, a buffer status indication (BEI) memory 51 indicating whether or not the corresponding channel is empty is configured.

Referring to the operation of the present invention configured as described above, the cell buffer unit 10 is the actual buffer of the cell entered into the cell interval control device and the address FIFO 30 manages the address in use of the cell buffer unit 10 The idle address FIFO 20 manages unused addresses of the cell buffer unit 10. In addition, the schedule management unit 40 performs a function of calculating and managing a scheduled transmission time of cells for spacing of cells. Here, the cell buffer unit 10 uses a shared buffer and the address FIFO 30 uses a separate buffer for each channel. In addition, all cells are once stored in the cell buffer unit 10 and then transmitted, and a delay of at least one slot occurs. The cell entering the cell gap control device receives the idle address from the idle address FIFO 20 and stores the cell address in the cell buffer unit 10 using the cell address as an index of the cell buffer unit 10. The address is stored in the address FIFO 30 of the corresponding channel according to the virtual channel identifier (VCI) value of the cell. After that, the schedule manager 40 calculates and manages the scheduled transmission time of the cell. When the transmission time of the scheduled cell is reached, the cell buffer unit 10 sends the cell out and the address of the cell buffer unit 10 returns to the idle address FIFO 20. If there is a cell waiting for the channel, the schedule manager 40 schedules and manages the scheduled transmission time of the next cell.

The scheduler 46 of the schedule management unit 10 is for registering a scheduled transmission time of a cell that has entered the cell interval control apparatus, and two or more cells may be registered in the same time zone to indicate the start and end of the registered one, respectively. It consists of the Start Scheduler Entry (SEH) 47 and End Scheduler Entry (SET) 48 fields. The output linked list (OLL) 45 is for managing several cells registered in the same entry of the scheduler 46. The internal operation is a memory that operates as a linked list. The output list start (OLH) 43 and the output list end (OLT) 44 memories are the ones registered at the output connection list memory 45 and the scheduler 46, the ones with the earliest ones having the transfer time. Used to represent each of the latter. The cell state display memory 41 is used to indicate the state of the transmitted cell of each channel, and the scheduled transmission time (NDT) calculation unit 42 is used to calculate the scheduled transmission time of the cell to register with the scheduler 46. do. For convenience of explanation of the internal operation of the schedule management unit 40, the logical operation and spacing algorithm used for the cell spacing in the interval control apparatus of the present invention will be described first.

4 illustrates a logical operation of the present invention, in which the transmission time of all cells stored in the buffer is not all scheduled, but only the head cell of each connection is scheduled. This is because when the cell arrives at the time of arrival, when the transmission time of several cells coincides with the same slot and output contention occurs, only one cell is transmitted when the actual transmission time is reached, and the other cells are one per slot. The delay is transmitted, resulting in a change in the time interval of cells belonging to the same channel. Therefore, in this case, in order to keep the inter-cell time interval constant, the present cell interval control apparatus uses a method of determining the transmission time of the next cell after transmitting the cell. That is, a method of maintaining a constant interdepature time between transmission cells. This ensures a minimum time interval (MIT). The operation of the interval control device for one slot is as follows.

All input cells may be stored in the cell buffer unit 10 and exit from the next slot. During the first half slot of one slot, the cell is transmitted. During the next half slot, the newly arrived cell is stored in the buffer. The next scheduled transmission time (NDT) to be transmitted is only immediately after transmitting the previous cell. That is, the transmission time of the next cell is scheduled only when there is a cell waiting for the transmitted channel. If there is no cell waiting, there is no process for scheduling the next scheduled transmission time for that channel. When the buffer of the newly arrived cell is empty (when the BEI field is set to 1), the process of storing the cell and scheduling the scheduled transmission time of the cell is performed together.

5 shows a spacing flowchart used in the present invention.

As the output band control method, the interval between cell minimum time (MIT) is used. Therefore, the parameters required for output band control are the minimum time between cells (MIT), the last transmission time (LDT: last time) indicating the transmission time of the last cell, and the current time (T). Here, the minimum inter-cell time (MIT) is determined from the maximum cell rate (PCR), a traffic parameter negotiated at the time of connection establishment, and the last transmission time (LDT) value is updated every time a cell is transmitted, and the current time (T) value is It shows the current slot time, which is increased by 1 for each slot, and X is the spacing time used for scheduling. The spacing algorithm of FIG. 5 uses a virtual scheduling algorithm, and if the current time (T) value is greater than the sum of the final transmission time (LDT) value and the inter-cell minimum time (MIT) value (100), the transmission interval time ( X is 0 (110), and if it is small, the difference of the sum of the final transmission time (LDT) value and the inter-cell minimum time (MIT) minus the current time (T) is determined as the transmission interval time (X) value (120). ).

Referring to the operation of the schedule management unit 40 again, if there is a cell that has already reached the scheduled transmission time in every slot, it transmits and transmits it to the last transmission time (LDT) field 49 of the cell status display memory 41. Update the current time T value. If there is a cell waiting for the channel to which the cell has been transmitted, the next transmission interval time (X) is obtained by applying the spacing algorithm of FIG. 5 in the NDT calculation unit 42, and the index of the scheduler 46 is obtained. Register in the entry corresponding to the scheduled transfer time. Since multiple entries can be scheduled in the same entry in the scheduler 46, the first scheduled one is stored in the scheduler entry start (SEH) field 47, and then stored using the output link list (OLL) memory 45. And the last scheduled one is stored in the End of Entry (SET) field 48 as a schedule. After the scheduling process for the cell to be transmitted is completed and the entry of the scheduler 46) and the entry of the output connection list 45 are newly updated, the output list starts to manage the output list of cells to be transmitted by the cell interval control apparatus every slot. (OLH) The values of the memory 43 and the output list end (OLT) memory 44 are updated.

FIG. 6 shows a method of registering with the scheduler 46 using the transmission interval time X obtained using the spacing algorithm of FIG.

Transmission time scheduling occurs only in two cases when there is a cell waiting on a channel after transmitting the cell and when a cell arrives on an empty channel. As shown in FIG. 6, the VCI value of the cell is registered in the scheduler 46 by using the next transmission interval time X value as an index from the current time T value. Here, the scheduler entry start (SEH) and the scheduler entry end (SET) are for indicating the beginning and the end of those registered in the same entry of the scheduler 46 with the same transmission time, respectively. Is for managing cells between the Scheduler Entry Start (SEH) field 47 and the Scheduler Entry End (SET) field when multiple (more than two) cells are scheduled in the same slot. Using the current time (T) and the transmission interval time (X) as the index for the scheduler 46, the value of the scheduler entry end (SET) 48 is read and if it is '0' then nothing is scheduled at that time. In other words, the corresponding VCI value is stored in the scheduler entry start (SEH) 47 and the scheduler entry end (SET) 48. If any value other than '0' is present at the scheduler entry end (SET) 48, it is already registered at that time, and the value of the scheduler entry end (SET) 48 is the VCI of the last cell registered. As the value refers, the newly scheduled value is linked to the scheduler entry end (SET) 48. When multiple cells are scheduled for entries in the same scheduler, the second scheduled schedule is newly scheduled for that entry using the value of the scheduler entry start (SEH) 47 as an index into the output connection list (OLL) 45. The VCI of the cell is stored and updated at the end of the scheduler entry (SET) 48 to point to the last registered cell. Then, when scheduled again, the value of the scheduler entry end (SET) 48 is indexed to link the new value to the output connection list (OLL) 45 and the scheduler entry end (SET) 48 is also updated. In FIG. 6, the cell with VCI 2 is first registered at the scheduler entry start (SEH) 47 of the schedule, and then the cell with VCI 3 is scheduled and stored in the output connection list (OLL) 45. Finally, the cell with VCI number N is registered at the scheduler entry end (SET) 48. Since the scheduler 46 is configured to represent up to (M + 1) slots, the current time (T) value takes a module (modulus) as (M + 1). That is, the value of the current time T starts at 0, increases by 1, and returns to 0 when M is reached. The scheduler entry start (SEH) 47 for the past slot time sets all of the values of the scheduler entry end (SET) 48 to zero.

Figure 7 illustrates an update to the output list start (OLH) and the output list end (OLT) values.

Among the cells registered in the scheduler 46, a list of cells to be transmitted when the scheduled time is reached is called an output list. Since only one cell is transmitted in one slot, multiple cells may be in the output list due to delay. have. Among the output lists, the first one is the output list start (OLH) memory 43 and the last one is the output list end (OLT) memory 44.

(A) of FIG. 7 shows that the current slot time is T-1, and the values of the output list start (OLH) memory 43 and the output list end (OLT) memory 44 are both zero. Indicates that there is no cell to transmit. In the next slot time T, three cells (cells 2, 3, and N buffers) are registered in the scheduler for transmission. That is, if the value of the end of the output list (OLT) 43 is '0', the scheduler corresponding to the T time of the scheduler 46 is updated to update the cell to be transmitted at the next slot time in the output list because the output list is empty. The value of the entry start (SEH) 47 is stored in the output list start (OLH) memory 43 and the scheduler entry end (SET) 48 value is stored in the output list end (OLT) memory 44.

(B) of FIG. 7 shows that the output list start (OLH) memory 43 and the output list end (OLL) memory 44 are newly updated as the current slot time is T, and the output list start (OLH) is performed every slot. Using the value of the memory 43 as an index of the output linked list (OLL) 45, the value in the entry is updated in the output list start (OLH) memory 43 to determine the cell to be transmitted in the next slot. If the value of the output list end (OLT) memory 44 is not '0' for each slot, the value is used as an index of the output linked list (OLL) 45 to start the scheduler entry corresponding to the next slot time in the entry. The (SEH) 47 value is stored and the scheduler entry end (SET) 48 value is updated in the output list end (OLT) memory 44.

8 shows an overall flowchart according to an embodiment of the present invention.

When the slot is started, the cell interval control device checks the output list start (OLH) value in every slot for cell transmission (200) to check whether there is a cell to be transmitted, that is, the output list start (OLH) value is greater than '0'. (201).

If the output list start (OLH) value is greater than '0', the cell stored in the cell buffer unit 10 is transmitted using the value of the corresponding address FIFO 30 indicated by the output list start (OLH) value (202). After updating the last transfer time (LDT) 49 value of the cell state display memory 41 (203), it is checked whether the transferred buffer is empty (204). If the status of the transmitted buffer is not empty, a scheduling processing routine for the next cell of the buffer is performed (205). If the transmitted buffer is empty, the buffer status indication (BEI) bit of the cell status display memory 41 is cleared. Set to '1' (206), and check whether there is a cell input to the cell spacing controller (208). In addition, if the output list start (OLH) value is not greater than '0' (201), it indicates that there is no cell to be transmitted in the corresponding slot (207), and checks whether there is a cell inputted by the cell gap controller (208). . If there is a cell input to the cell spacing controller, after performing an input cell processing routine (209), a routine for updating an output list start (OLH) value and an output list end (OLT) value is performed (210). If there is no cell, a routine for updating an output list start (OLH) value and an output list end (OLT) value is performed (210), and the process ends.

9 is a flowchart illustrating a scheduling process according to an embodiment of the present invention.

First, a cell interval is calculated by the NDT calculation unit 42 using a final transfer time (LDT) value and an inter-cell minimum time (MIT) value in a cell state display memory 41 for a cell to be scheduled (211). It is checked whether the value of the scheduler entry end (SET) of the value is 'zero' (212). If the value of the scheduler entry end (SET) is 'zero', it means that nothing has been scheduled at that time. Therefore, the VCI value of the cell to be scheduled is updated at the scheduler entry start (SEH) and the scheduler entry end (SET). Save (213), and if the value of the scheduler entry end (SET) is not 'zero', another cell is already registered at that time, so the value of the current scheduler entry end (SET) is used as an index of the output connection list (OLL). Store the VCI value of the cell scheduled in the output connection list (OLL) (214), store the zero in the output connection list (OLL) indicated by the stored VCI (215), and at the end of the scheduler entry (SET) Update to the stored VCI value (216) and end.

10 is a flowchart illustrating an input cell process according to an embodiment of the present invention.

The input cell processing routine stores the input cell in the cell buffer unit 10 (217), examines the buffer status display (BEI) bit for the corresponding channel of the cell status display memory 41 (218), and displays the buffer status. (BEI) check whether the bit is '1' (219), if the buffer status display (BEI) bit is '1', since the cell buffer unit 10 is empty, a scheduling routine is performed (220), and the buffer status is displayed. If the (BEI) bit is not '1', the input cell processing routine ends immediately.

11 is a flowchart illustrating an update process of output list start (OLH) and output list end (OLT) values according to an embodiment of the present invention.

First, it is determined whether the value of the end of the output list (OLT) is greater than '0' (221) and is not greater than '0' or is greater than '0' and the value of the end of the output list (OLT) and the value of the beginning of the output list (OLH). If the output list is empty (222), the scheduler entry start (SEH) value corresponding to the next slot is updated and stored in the output list start (OLH), and the value of the scheduler entry end (SET) is stored in the output list end ( OLT) is updated and stored (223).

If the value at the end of the output list (OLT) and the value at the beginning of the output list (OLH) are not the same, the next value of the output linked list (OLL) is updated to the beginning of the output list (OLH) (224), and the end of the output list (OLT) value. Is used as an index of the output linked list (OLL) to update the value of the scheduler entry start (SEH) corresponding to the next slot in the entry (225), and the value of the scheduler entry end (SET) is set to the end of the output list (OLT). It is updated and stored in (226).

The present invention configured and operated as described above can control the time between cells with a minimum time interval (MIT) for the service of CBR traffic sensitive to the cell transmission time and the time interval between cells in addition to the output buffer of the switch. Quality can be kept constant, and added to the output port of a connectionless server of a switching system with connectionless service capability, which is performed at the subscriber matching device when the processed cell for the connectionless cell is sent back to the destination through the exchange. It prevents loss by UPC function and adds interval control function for fixed virtual connection (PVC) from connectionless server in ATM network to other server to concentrate cells which have been routed and cell header converted to specific output channel. Even if the bandwidth is distributed evenly by the interval control per channel, the quality of service can be kept constant. Not only it has the effect that you can achieve fairness between channels.

Claims (7)

Cell buffering means (10) for storing a cell; Address FIFO means (30) for managing an active address of said cell buffering means (10); Idle address FIFO means (20) for managing unused addresses of the cell buffering means (10); Cell state display memory means 41 for storing state of each channel; Predetermined transmission time (NDT) calculating means (42) for calculating an estimated transmission time of a cell by using the value of said cell state display memory means (41); Scheduling means 46 for registering a scheduled transmission time of a cell that has arrived for spacing of the cell; Output linked list (OLL) memory means 45 for managing cells registered in the same entry of the scheduling means 46; An output list start (OLH) memory means (43) for storing the virtual channel identifier (VCI) in front of those registered in the scheduling means (46) at the end of the transmission time; And an output list end (OLT) memory means 44 for storing a virtual channel identifier (VCI) at the end of those whose transmission time has expired among those registered in the scheduling means (46). Cell spacing controller for output band control in ATM networks. 2. The scheduler entry according to claim 1, wherein said scheduling means (46) comprises a scheduler entry start (SEH) field 47 indicating the start of being registered when two or more cells are registered in the same time zone and a scheduler entry indicating the end of being registered. Cell spacing control device for output band control in ATM network, characterized in that the end (SEH) field. 2. The cell status display memory means (41) according to claim 1, wherein said cell state display memory means (41) stores a last transmission time (LDT) field 49 for storing a final time value used for calculating a predetermined transmission time and a minimum transmission time value between cells. Inter-cell minimum transmission time (MIT) field 50 and a buffer status indication (BEI) field 51 indicating whether or not the channel is empty when the cell enters the cell spacing controller. An apparatus for controlling cell spacing for output band control in an ATM network. Cell buffering means 10 for storing a cell, address FIFO means 30 for managing an active address of the cell buffering means 10, and idle address FIFO means 20 for managing an unused address of the cell buffering means 10. A cell interval control method for output bandwidth control in an ATM network, which is applied to a cell interval control device comprising a schedule management means 40 for managing a schedule related to spacing of a cell), each slot for cell transmission. A first step (200, 201) of checking the output list start (OLH) value every time to check whether the output list start (OLH) value is greater than '0'; If the output list start (OLH) value is greater than '0' in the first steps (200, 201), the cell buffering means 10 using the value of the corresponding address FIFO means 30 indicated by the output list start (OLH) value. A second step (202 to 204) of transmitting a cell stored in the CDMA), updating the last transmission time (LDT) 49 value of the cell state display memory means 41, and then checking whether the transmitted buffer is empty; If the status of the buffer transmitted in the second step (202 to 204) is not empty, the scheduling processing routine for the next cell of the buffer is executed. If the transmitted buffer is empty, the buffer of the cell status display memory means 41 A third step (205, 206, 208) of setting a status indication (BEI) bit to '1' and checking if there is a cell input to the cell spacing controller; In the first step (200, 201), if the output list start (OLH) value is not greater than '0', it indicates that there is no cell to be transmitted in the corresponding slot, and checks whether there is a cell input to the cell spacing controller Four steps (207, 208); And if there is a cell input to the cell spacing controller in the third step (205, 206, 208) or the fourth step (207, 208), after performing an input cell processing routine, an output list start (OLH) value and A fifth step (209, 210) of performing an routine to update an output list end (OLT) value and performing an update of an output list start (OLH) value and an output list end (OLT) value if there is no input cell Cell spacing control method for output band control in an ATM network comprising a. 5. The scheduling process of claim 4, wherein the scheduling processing routine in the third step (205, 206, 208) calculates the NDT using the last transfer time (MIT) value in the cell state indicating memory means 41 for the cell to be scheduled. A sixth step (211, 212) of calculating the cell interval in the means (42) to see if the value of the corresponding scheduler entry end (SET) of the scheduler is 'zero'; And if the value of the scheduler entry end (SET) is 'zero' in the sixth step (211, 212), it means that nothing has been scheduled yet at that time, so that the scheduler entry starts with the VCI value of the cell to be scheduled. ) And save at the end of scheduler entry (SET), and if the value of scheduler end (SET) is not 'zero', another cell is already registered at that time. Save the VCI value of the cell that is scheduled in the output connection list (OLL) using the index of the list (OLL), save 'zero' in the output connection list (OLL) indicated by the stored VCI, and end the scheduler entry (SET). And a seventh step (213 to 216) of updating to the VCI value stored in the cell). 5. The method of claim 4, wherein in the fifth step (209, 210), the input cell processing routine stores the input cells in the cell buffering means (10), and buffer status for the channel of the cell state display memory means (41). An eighth step (217 to 219) checking the indication (BEI) bit to check whether the buffer status indication (BEI) bit is '1'; In the eighth step (217 to 219), if the buffer status indication (BEI) bit is '1', the cell buffering means 10 is empty, so the scheduling processing routine is performed, and the buffer status indication (BEI) bit is '1'. Or a ninth step (220) of immediately ending the input cell processing routine. The routine for updating an output list start (OLH) value and an output list end (OLT) value in the fifth step (209, 210), wherein the value of the output list end (OLT) is greater than '0'. A tenth step (221, 222) of determining whether a value of an output list end (OLT) and a value of an output list start (OLH) are the same; And in the tenth step (221, 222), if the value of the output list end (OLH) and the output list start (OLH) is not greater than '0' or greater than '0', the output list is empty. Updates and saves the scheduler entry start (SEH) value corresponding to the slot at the start of the output list (OLH), updates the scheduler entry end (SET) at the end of the output list (OLT), and saves it. OLT) value and output list start (OLH) value are not the same, the next value of output linked list (OLL) is updated to output list start (OLH), and the output list end (OLT) value is output linked list (OLL) An eleventh step (223) of updating the scheduler entry start (SEH) value corresponding to the next slot to the entry and updating and storing the value of the scheduler entry end (SET) at the end of the output list (OLT) using the index of the entry. To 226) Cell spacing control method for output band control in network.