KR0151897B1 - Package with adhered surface of mould resin conductive material - Google Patents
Package with adhered surface of mould resin conductive materialInfo
- Publication number
- KR0151897B1 KR0151897B1 KR1019950019201A KR19950019201A KR0151897B1 KR 0151897 B1 KR0151897 B1 KR 0151897B1 KR 1019950019201 A KR1019950019201 A KR 1019950019201A KR 19950019201 A KR19950019201 A KR 19950019201A KR 0151897 B1 KR0151897 B1 KR 0151897B1
- Authority
- KR
- South Korea
- Prior art keywords
- package
- conductive member
- chip
- long groove
- package according
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
본 발명은 패키지의 칩이 작동시에 발생되는 열을 그 패키지의 외부로 방출시키기 위해서 패키지 표면에 전도성 부재(傳導性 部材)가 부착되어 그 패키지의 칩이 동작되는 경우에 발생되는 열을 효과적으로 방출시킬 수 있는 동시에 상기의 구조를 갖는 패키지가 복수개 적층될 경우에 그 적층형 패키지의 중심 부위로 열이 집중되는 현상을 방지할 수 있는 효과가 있다.According to the present invention, a conductive member is attached to a surface of a package to release heat generated when the chip of the package is operated to the outside of the package, thereby effectively dissipating heat generated when the chip of the package is operated. At the same time, when a plurality of packages having the above structure are stacked, there is an effect of preventing heat from concentrating on a central portion of the stacked package.
Description
제1a도는 본 발명에 전도성 부재(傳導性 部材)가 성형수지 표면에 부착된 패키지의 측단면도.1A is a side cross-sectional view of a package in which a conductive member is attached to a molding resin surface in the present invention.
제1b도는 본 발명에 의한 전도성 부재의 개략 사시도.1B is a schematic perspective view of a conductive member according to the present invention.
제2a도 및 제2b도는 종래 기술에 의한 적층형 패키지의 구조와 본 발명에 의한 전도성 부재(傳導性 部材)를 패키지 표면에 부착시킨 적층형 패키지의 구조의 열전달 상태를 모의적 방법에 의해 나타낸 등온선 그래프.2A and 2B are an isotherm graph showing the heat transfer state of the structure of the laminated package according to the prior art and the structure of the laminated package in which the conductive member according to the present invention is attached to the package surface.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 칩 20 : 다이패드10: chip 20: die pad
30 : 내부리드 35 : 와이어30: internal lead 35: wire
40 : 외부리드 50 : 성형수지40: outer lead 50: molding resin
60 : 전도성 부재 62 : 장홈60: conductive member 62: long groove
70 : 접착제 80 : 본딩패드70: adhesive 80: bonding pad
100 : 패키지100: package
본 발명은 고방열 반도체 패키지에 관한 것으로, 더욱 상세하게는 패키지의 칩이 작동시에 발생되는 열을 그 패키지의 외부로 방출시키기 위해서 패키지 표면에 전도성 부재(傳導性 部材)가 부착되어 그 패키지의 칩이 동작되는 경우에 발생되는 열을 효과적으로 방출시킬 수 있는 전도성 부재(傳導性 部材)가 성형수지 표면에 부착된 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high heat dissipation semiconductor package, and more particularly, a conductive member is attached to a surface of a package to dissipate heat generated during operation of the chip to the outside of the package. The present invention relates to a package in which a conductive member capable of effectively dissipating heat generated when a chip is operated is attached to a molding resin surface.
최근 들어, 고속 처리 워크 스테이션(workstation) 마이크로 프로세서(micro processor)와 소비 전력이 큰 화상처리용 고집적회로, 그리고 고밀도 게이트 어레이(gate array) 및 적층형 패키지, MBGA(metal-lid ball grid array) 등의 패키지가 개발되어짐에 따라, 반도체 장치의 동작시 패키지 내부에 발생되는 열을 대기 중으로보다 효과적으로 방출시키고자 하는 패키지가 필요하게 되었다.Recently, high-speed processing workstation microprocessors, high-integration circuits for high power consumption image processing, high-density gate arrays and stacked packages, and metal-lid ball grid arrays (MBGA) As packages have been developed, there is a need for packages that more efficiently release heat generated inside the package to the atmosphere during operation of the semiconductor device.
반도체 장치의 동작시 칩의 상단 액티브층(active layer)에서 발생되는 열은 그 칩에서 다이패드 및 본딩 와이어를 통하여 리드프레임으로 전달되며, 열전도성이 적은 성형수지를 통하여 그 패키지 표면까지의 열 이동은 전도의 형태로 열전달이 되며, 또한 그 패키지의 표면에서부터 대기로의 열전달은 공기에 의한 대류와 복사 효과의 형태로 열전달이 이루어진다.During operation of the semiconductor device, heat generated in the upper active layer of the chip is transferred from the chip to the leadframe through the die pad and the bonding wire, and heat transfer to the surface of the package through the molding resin having low thermal conductivity. Is heat transfer in the form of conduction, and heat transfer from the surface of the package to the atmosphere is in the form of air convection and radiation effects.
이때, 패키지의 내부에 발생한 열은 열전도성이 낮은 성형수지로 봉지되어 그 패키지의 표면으로의 열전도 및 대류 효과가 감소되어, 반도체 장치의 동작시 오동작 및 전기적 고장 등의 불량을 야기한다.At this time, the heat generated inside the package is encapsulated with a molding resin having a low thermal conductivity, thereby reducing heat conduction and convection effects on the surface of the package, thereby causing malfunctions such as malfunctions and electrical failures during operation of the semiconductor device.
더구나, 적층형 패키지의 구조에 있어서는 중앙 부위에 적층된 패키지에서 발생되는 열을 분산 및 방출하기가 곤란하다. 그러므로, 상기의 열적인 문제를 해결하기 위하여 성형수지 대신에 세라믹 또는 금속 재료를 사용하기도 하지만, 비용 면에서 비효율적이다.Moreover, in the structure of the laminated package, it is difficult to disperse and dissipate heat generated in the package laminated at the central portion. Therefore, in order to solve the above thermal problem, ceramic or metal materials may be used instead of molding resins, but they are inefficient in terms of cost.
일반적인 플라스틱 패키지에서는, 칩이 탑재되는 다이패드 하부면상에 히트 스프레더(heat spreader) 및 히트 싱그(heat sink) 또는 그 히트 싱크에 지느러미 형태의 부재(fin)를 붙인 노출형 구조를 도입하였지만, 성형 공정에 있어서 성형성의 문제 발생 또는 히트 싱크와 패키지와의 접착시에 반드시 접착력이 양호하고 열전도성이 우수한 접착성 재질을 사용해야 하는 문제가 있다.In the general plastic package, a heat spreader and a heat sink or a fin-like fin is attached to the heat sink on the bottom surface of the die pad on which the chip is mounted. In the formability problem, or when bonding the heat sink and the package there is a problem that must use an adhesive material having good adhesion and excellent thermal conductivity.
더욱이, 패키지의 밀도가 높은 적층형 패키지에 있어서는, 상하로 적층되는 패키지의 표면과 히트 싱크가 근접되게 배치되어 있기 때문에 오히려 열을 중앙 부위로 집중시키는 역효과가 발생되고, 그 히트 싱크를 내재시키므로서 적층시 패키지의 두께를 증가시키는 단점이 있다.Furthermore, in a package having a high density of packages, since the surfaces of the packages stacked up and down and the heat sinks are arranged close to each other, the adverse effect of concentrating heat to the center portion occurs, and the stacks are made while incorporating the heat sinks. There is a disadvantage of increasing the thickness of the sea package.
따라서 본 발명의 목적은 패키지의 칩이 동작될 때에 발생하는 패키지 내부의 열을 효과적으로 방출시키기 위해 그 패키지의 성형수지 표면에 전도성이 양호한 재질의 전도성 부재를 부착하여 그 발생된 열을 그 패키지의 성형수지의 외부로 방출시키는 전도성 부재(傳導性 部材)가 성형수지 표면에 부착된 패키지를 제공하는데 있다.Accordingly, an object of the present invention is to attach a conductive member of a good conductive material to the surface of the molding resin of the package in order to effectively dissipate heat inside the package generated when the chip of the package is operated to form the heat of the package. The present invention provides a package in which a conductive member for releasing to the outside of the resin is attached to the molding resin surface.
상기 목적을 달성하기 위하여, 복수개의 본딩패드들이 상면에 형성된 칩과 ; 그 칩과 접착수단에 의해 접착된 다이패드와 ; 그 칩상에 형성된 본딩패드들에 대응하여 전기적 연결된 내부리드들과 ; 그 내부리드들과 일체형으로 대응하는 외부리드들과 ; 그 칩과 다이패드와 내부리드들이 내재·봉지된 성형수지를 포함하는 패키지에 있어서, 상기 성형수지와의 접착력을 개선하기 위한 장홈을 갖으며, 상기 패키지의 내부에 발생되는 열을 그 성형수지의 외부로 방출하기 위한 전도성이 양호한 전도성 부재가 그 성형수지의 표면에 부착된 것을 특징으로하는 전도성 부재(傳導性 部材)가 성형수지 표면에 부착된 패키지에 제공한다.In order to achieve the above object, a plurality of bonding pads formed on the upper surface; A die pad bonded by the chip and the bonding means; Internal leads electrically connected to bonding pads formed on the chip; External leads corresponding integrally with the internal leads; A package comprising a molding resin in which the chip, the die pad, and the inner leads are embedded and encapsulated, the package having a long groove for improving adhesion to the molding resin, and heat generated inside the package of the molding resin. A conductive member having good conductivity for releasing to the outside is attached to the surface of the molded resin, and a conductive member is provided in the package attached to the surface of the molded resin.
이하, 첨부 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
제1a도는 본 발명에 의한 전도성 부재(傳導性 部材)가 성형수지 표면에 부착된 패키지의 측단면도이다.1A is a side sectional view of a package in which a conductive member according to the present invention is attached to a molding resin surface.
제1b도는 본 발명에 의한 전도성 부재의 개략 사시도이다. 제1도를 참조하면, 본 발명에 의한 패키지(100)는 리드프레임의 다이패드(20)와 칩이 접착제(70)에 의해 접착되어 있으며, 그 칩상에 형성되어 있는 본딩패트(80)들에 대응하여 내부리드(30)들이 와이어(35)에 의해 전기적 연결되어 있으며, 그 내부리드(30)들에 일체형으로 대응하여 외부리드(40)들이 존재되어 있으며, 상기 다이패드(20)와 칩(10)과 내부리드(30)들이 성형수지(50)에 의해 내재·봉지되어 있으며, 그 성형수지(50)의 상부면상에 전도성 부재(60)가 부착·배치되어 있으며, 그 전도성 부재(60)의 배치 위치는 상기 외부리드(40)들의 전곡 방향의 반대편에 배치되는 구조로 되어 있다.1B is a schematic perspective view of the conductive member according to the present invention. Referring to FIG. 1, the package 100 according to the present invention has a die pad 20 of a lead frame and a chip bonded to each other by an adhesive 70, and bonded to the bonding pads 80 formed on the chip. Correspondingly, the inner leads 30 are electrically connected by wires 35, and the outer leads 40 are integrally formed to integrally correspond to the inner leads 30, and the die pad 20 and the chip ( 10) and the inner lead 30 is embedded and encapsulated by the molding resin 50, the conductive member 60 is attached and disposed on the upper surface of the molding resin 50, the conductive member 60 The arrangement position of the outer leads 40 is arranged in the opposite side of the curved direction of the structure.
좀 더 상세히 언급하면, 상기 전도성 부재(60)의 내측에는 상기 성형수지(50)의 유동 방향과 동일한 방향으로 장홈(62)이 복수개 정렬·형성되어 있어서, 상기 성형수지(50)의 안정적인 유동성이 확보 및 그 성형수지(50)와의 집착력이 증가되며, 또한 전도성 부재(60)는 상기 패키지(100)의 외부리드(40)들에 접촉되지 않으며 그 패키지(100)의 측면까지 연장되어 있고, 그 장홈(62)의 길이는 그 전도성 부재(60)의 길이와 동일하게 형성되어 있다.In more detail, a plurality of long grooves 62 are arranged and formed inside the conductive member 60 in the same direction as the flow direction of the molding resin 50, so that the stable flowability of the molding resin 50 Securing and adhesion to the molding resin 50 is increased, and the conductive member 60 is not in contact with the outer leads 40 of the package 100 and extends to the side of the package 100. The length of the long groove 62 is formed equal to the length of the conductive member 60.
또한, 상기 전도성 부재에 형성되어 있는 장홈의 형성 방향은 상기 성형수지의 유동 방향에 동일 방향 또는 그 이외의 방향으로 변형·실시될 수 있으나 바람직하게는 그 성형수지의 유동 방향과 동일한 경우가 그 전도성 부재의 접착력이 증대되며, 그 장홈의 형상 또는 같은 이유로 직선형 또는 곡선형 또는 복합적인 형태로 변형·실시될 수 있다.In addition, the direction of forming the long grooves formed in the conductive member may be modified and implemented in the same direction or in a direction other than the flow direction of the molding resin, but preferably the same as the flow direction of the molding resin. The adhesive force of the member is increased, and it can be deformed and implemented into a straight line, a curved line, or a complex form for the shape of the long groove or the same reason.
상기 전도성 부재의 배치 위치는 상기 외부리드들의 절곡 방향에 무관하게 배치될 수 있으나, 패키지의 구조상 다이패드와 동일한 방향 또는 외부리드의 절곡 방향에 대해서는 반대편이 열방출에 효과적이다.An arrangement position of the conductive member may be arranged irrespective of the bending direction of the outer leads, but the opposite side is effective for heat dissipation in the same direction as the die pad or the bending direction of the outer lead due to the structure of the package.
상기와 같은 구조는, 상기 패키지의 외부리드 절곡 방향 반대편의 성형금형 표면에 전도성을 부재를 배치하여 성형 공정을 진행하는 간단한 방법으로 전도성 부재를 패키지와 일체형으로 제작할 수 있다.In the above structure, the conductive member may be integrally formed with the package by a simple method of disposing the conductive member on the surface of the molding die opposite to the outer lead bending direction of the package and proceeding the molding process.
제2a도 및 제2b도는 종래 기술에 의한 적층형 패키지의 구조와 본 발명에 의한 전도성 부재(傳導性 部材)를 패키지 표면에 부착시킨 적층형 패키지의 구조의 열전달 상태를 모의적 방법에 의해 나타낸 등온선 그래프이다. 제2도를 참조하면, 예를 들어 개별 패키지를 9개 적층한 형태이며, 그 적층형 패키지의 열분산 및 열방출 효과를 검증하기 위하여 CAE(computer adided engineering) 기법을 도입하여 열해석 모의 실험을 진행한 것으로, 자연 대류 조건에서 열해석을 실시한 결과 본 발명에 의한 전도성 부재를 부착된 패키지가 종래 기술에 의한 적층형 패키지에 비해 그 패키지의 내부 접합부 온도를 약 15% 정도 낮출 수 있었다.2A and 2B are an isotherm graph showing the heat transfer state of the structure of the laminated package according to the prior art and the structure of the laminated package in which the conductive member according to the present invention is attached to the package surface. . Referring to FIG. 2, for example, 9 individual packages are stacked, and thermal analysis simulation is conducted by introducing computer adided engineering (CAE) technique to verify heat dissipation and heat dissipation effects of the stacked packages. As a result, thermal analysis under natural convection conditions resulted in a package attached with a conductive member according to the present invention to lower the internal junction temperature of the package by about 15% compared to the laminated package according to the prior art.
이는, 패키지의 밀도가 높은 적층형 패키지에 있어서, 상하로 적층되는 패키지의 중앙 부위로 열이 집중되는 역효과를 본 발명에 의한 전도성 부재를 부착된 패키지를 적용하므로서, 그 집중된 열을 분산시켜 패키지의 신뢰성을 크게 개선하였다.This is because, in the stacked package having a high density of the package, the package having the conductive member according to the present invention is applied to the adverse effect of heat concentrating on the center portion of the package stacked up and down, thereby dispersing the concentrated heat to ensure the reliability of the package. Significantly improved.
또한, 본 발명에 의한 전도성 부재를 부착시킨 패키지를 전자기기의 시스템에 실장 되어 사용될 경우에 송풍수단에 의한 강제 대류(풍속=1~2m/s)로 인하여 대류 효과가 상승되어 열방출 효과를 상당히 개선된다.In addition, when the package to which the conductive member according to the present invention is attached is used in a system of an electronic device, the convection effect is increased due to forced convection by the blowing means (wind speed = 1 to 2 m / s), thereby significantly improving the heat dissipation effect. Is improved.
따라서, 본 발명에 따른 구조에 따르면, 패키지의 표면에 전도성 부재만을 부착하므로서 그 패키지의 열방출 효과가 증대되고, 또한 패키지에 있어서는 상하로 적층되는 패키지의 표면과 히트 싱크가 근접되게 배치되어 있는 종래의 적층형 패키지에서는 오히려 열을 중앙 부위로 집중시키는 역효과가 발생되고, 그 히트 싱크를 내재시키므로서 적층시 패키지의 두께를 증가시키는 단점을 극복할 수 있는 이점(利點)이 있다.Therefore, according to the structure according to the present invention, by attaching only the conductive member to the surface of the package, the heat dissipation effect of the package is increased, and in the package, the heat sink is disposed in close proximity to the surface of the package stacked up and down. In the laminated package, the adverse effect of concentrating heat to a central portion occurs, and has an advantage of overcoming the disadvantage of increasing the thickness of the package at the time of lamination by embedding the heat sink.
Claims (12)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950019201A KR0151897B1 (en) | 1995-07-01 | 1995-07-01 | Package with adhered surface of mould resin conductive material |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950019201A KR0151897B1 (en) | 1995-07-01 | 1995-07-01 | Package with adhered surface of mould resin conductive material |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970008526A KR970008526A (en) | 1997-02-24 |
| KR0151897B1 true KR0151897B1 (en) | 1998-10-01 |
Family
ID=19419546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950019201A KR0151897B1 (en) | 1995-07-01 | 1995-07-01 | Package with adhered surface of mould resin conductive material |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0151897B1 (en) |
-
1995
- 1995-07-01 KR KR1019950019201A patent/KR0151897B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970008526A (en) | 1997-02-24 |
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