KR0150732B1 - Apparatus for supporting oam function of atm terminal - Google Patents

Abstract

The present invention relates to an ATM terminal, and in particular, when an ATM layer processor fails to provide an OAM function, an AAM terminal having an OAM cell detection unit and an OAM first-in first-out unit to process an OAM function by a central processing unit. The present invention relates to an OAM function processing support apparatus.

There is a problem that the OAM layer processor does not provide the OAM function according to the ATM switch connected to the OAM dedicated processing device by the OAM function processing support circuit of the conventional ATM terminal.

In order to solve this problem, the present invention provides a physical layer processor for inputting and outputting a cell signal output from an ATM network as data of a physical layer, and checking whether the OAM cell is an OAM cell by checking the cell contents of a data signal input from the physical layer processor. An OAM detector for outputting, an ATM layer processor for processing and outputting OAM cell data output from the OAM detector, and a path for the central processing unit to transmit and receive all cells with respect to OAM cell data input from the ATM layer processor An OAM FIFO unit, a central processing unit for transmitting and receiving an OAM signal through the OAM FIFO unit according to the interrupt signal of the programmable logic device, and a programmable logic device for generating control signals related to the signal of the OAM FIFO unit.

Description

Apparatus for processing OAM function of asynchronous transmission mode (ATM) terminal

1 is a configuration diagram of an OAM function processing support apparatus in a conventional asynchronous transmission mode (ATM) terminal.

2 is a block diagram of an OAM function processing support apparatus in an asynchronous transmission mode (ATM) terminal according to the present invention.

3 is a detailed block diagram of the OAM detection unit of FIG.

4 is a control signal diagram related to the programmable logic device (PLD) of FIG.

* Explanation of symbols for main parts of the drawings

5: OAM cell detection unit 6: OAM first in, first out (FIFO)

7: Central Processing Unit (CPU) 8: Programmable Logic Unit (PLD)

The present invention relates to an ATM terminal. In particular, when an ATM layer processor fails to provide an OAM function, the present invention provides an OAM cell detection unit and an OAM first-in first-out unit to process an OAM function by a central processing unit. The present invention relates to an OAM function processing support apparatus.

The conventional OAM (Operation And Maintenance) function processing support apparatus of the Asynchronous Transmission Mode (ATM) terminal, as shown in Figure 1 of the accompanying drawings, the cell signal input from the ATM network (1) to the data bus of the physical layer A physical layer processor (2) for inputting and outputting, an OAM field processing device (3) for inputting and outputting by checking a cell header and a payload with respect to data input from the physical layer processor (2) to determine whether or not it is an OAM cell; It consists of an ATM layer processor 4 which processes and outputs the OAM cell data signal input from the OAM dedicated processing device 3.

In the OAM function processing support apparatus of the conventional ATM terminal configured as described above, the physical layer processor 2 receives a cell signal from the ATM network 1 and outputs the cell signal to the OAM processing dedicated device 3 through the output data bus of the physical layer. The OAM processing dedicated device 3 checks the cell header and the payload with respect to the input cell signal RCELD [0: 7], checks whether or not it is an OAM cell, and outputs it to the ATM layer processor 4.

Accordingly, the ATM layer processor 4 processes the OAM cell data signal input from the OAM processing dedicated device 3 and inputs it to the OAM processing dedicated device 3, and the OAM processing dedicated device 3 is a physical layer processor. In step (2), the OAM cell data signal is applied to the ATM cell data signal (TCELD [0: 7]) through the input cell data bus of the physical layer, and the physical layer processor (2) transmits the OAM cell to the ATM network (1). It outputs a data signal.

However, the conventional OAM function processing support circuit of the ATM terminal has a problem that the OAM layer processor does not provide the OAM function according to the ATM switch connected to the OAM dedicated processing device.

Accordingly, the present invention is to solve the above problems of the prior art, an object of the present invention is to install the OAM cell detection unit and OAM FIFO unit in the central processing unit to process the OAM function by the control signal of the programmable logic device. .

Technical means for achieving the object of the present invention is a physical layer processor for inputting and outputting a cell signal output from the ATM network as the data of the physical layer, and whether the OAM cell by examining the cell content of the data signal input from the physical layer processor An OAM cell detector for checking and outputting an OAM cell detector, an ATM layer processor for processing and outputting OAM cell data inputted from the OAM cell detector, and a path for the central processing unit to transmit and receive an OAM cell data signal inputted from the ATM layer processor OAM FIFO unit for providing a, a programmable logic device (PLD :) for controlling a signal related to the signal of the OAM FIFO unit, and transmitting and receiving OAM signal according to the control signal of the programmable logic device through the OAM FIFO It consists of a central processing unit.

Hereinafter, described in detail with reference to the accompanying drawings of the present invention.

2 is a block diagram of an OAM function processing support apparatus in an ATM terminal according to the present invention. The physical layer processor 2 inputs and outputs cell signals input from the ATM network 1 as data of a physical layer, and the physical An OAM detector 5 for checking whether the cell content of the data signal input from the layer processor 2 is an OAM cell, and outputting the OAM cell data signal inputted from the OAM detector 5; An ATM layer processor 4, an OAM FIFO unit 6 which provides a path for the central processing unit 7 to transmit and receive the OAM cell data signal input from the ATM layer processor 4, and the OAM FIFO unit 6 A programmable logic device 8 for controlling a signal related to a signal of the < RTI ID = 0.0 >), < / RTI > It is composed.

The operation and effects of the present invention configured as described above will be described with reference to FIGS. 2 through 4.

First, when a cell signal is applied from the ATM network 1, the physical layer processor 2 inputs the cell signal RCLEL [0: 7] to the OAM detector 5 through an input data bus of the physical layer.

Accordingly, the OAM detection unit 5 generates a signal generated during cell-based transmission in the UTOPIA interface, which is an interface, with respect to the inputted cell signals. By using the cell, the OAM cell type and the function type are read to check whether the cell is an OAM cell and input to the ATM layer processor 4.

Accordingly, the first AND gate 5a in the OAM cell detector 5 receives the inverted cell signal RCELD [0: 3] through the physical layer input data bus of the physical layer processor 2. The inverted cell signal and the second byte count signal Count2 of the programmable logic device 8 are received and ANDed, input to the clock terminal of the first dip-flop 5g, and the first dip-flop. (5g) receives the set high signal to the data terminal and inputs it to the seventh AND gate 5k in synchronization with the clock CLK.

In addition, the second AND gate 5b receives the inverted cell signal RCELD [0: 7] through the input data bus of the physical layer of the physical layer processor 2 and is programmable with the inverted cell signal. The third byte count signal Count3 of the logic device 8 is received and ANDed to be input to the clock terminal of the second flip-flop 5g, and the second flip-flop 5h is a set high signal. Is input to the seventh AND gate 5k in synchronization with the clock CLK.

The third AND gate 5c receives the inverted cell signal RCELD [6: 7] through the input data bus of the physical layer of the physical layer processor 2 and receives the inverted cell signal and the physical signal. The cell signal RCELD [4: 5] input through the hierarchical data bus and the fourth byte count signal Count4 of the programmable logic device 8 are applied to be ANDed to perform a AND operation on the first OR gate. 5i).

In addition, the fourth AND gate 5d receives the inverted cell signal RCELD [4, 5, 7] through the input data bus of the physical layer of the physical layer processor 2 and receives the inverted cell signal. And the cell signal RCELD [6] input through the physical layer data bus and the fourth byte count signal Count4 of the programmable logic device 8 to be ANDed to perform a AND operation on the first OR gate. 5l).

Accordingly, the first OR gate 5i performs an OR on the signals input from the third and fourth AND gates 5c and 5d and inputs them to the clock terminal of the third flip-flop 5j. The third flip-flop 5j receives the set high signal as a data terminal and inputs the same to the seventh AND gate 5k in synchronization with the clock CLK.

In addition, the fifth AND gate 5e receives the inverted cell signal RCELD [1, 2] through the input data bus of the physical layer of the physical layer processor 2 and receives the inverted cell signal and the physical signal. The signal RCELD [3] input through the hierarchical data bus and the fourth byte count signal Count4 of the programmable logic device 8 are applied and ANDed to the second OR gate 51. Will be entered.

The sixth AND gate 5f receives the inverted cell signal RCELD [2] through the input data bus of the physical layer of the physical layer processor 2 and receives the inverted signal and the physical layer data bus. The fourth byte count signal Count4 of the programmable logic device 8 is simultaneously received and ANDed together with the cell signal RCELD [1, 3] through the input to the second OR gate 51. Done.

Accordingly, the seventh AND gate 5k receives the signal inputted from the first, second, and third flip-flops 5g, 5h, and 5j, and ANDs the result, and knocks the result. NOR) is input to the gate 5m.

In addition, the second OR gate 51 performs an OR on the signals input from the fifth and sixth AND gates 5e and 5f and inputs them to the NOT gate 5m. do.

Accordingly, the NOR gate 5m negatively ORs the signals input from the seventh AND gate 5k and the second OR gate 51 and returns the result of the OAM detection signal ( oam_flag *) will be printed.

That is, the OAM cell detector 5 receives the cell count signal from the programmable logic device 8 to check 2, 3, 4 bytes at the start of the cell and checks the value of the corresponding bit.

This is because the F4 OAM cell and the F5 OAM cell have the following format.

Accordingly, when it is found that the cell is an OAM cell, the OAM detector 5 sends the OAM detection signal oam_flag * to the programmable logic device 8 in an active state.

Then, the programmable logic device 8 receives the OAM detection signal from the OAM detection unit 5, interrupts the central processing unit 7, and simultaneously outputs cells output from the physical layer processor 2 to the ATM layer processor 4. Instead of inputting the signal, the write strobe signal rf_wr * is input to the reception (RX) FIFO device 6a in the OAM FIFO section 6.

Accordingly, when the RX FIFO 6a checks the data state by the input write strobe (rf_wr *) signal and sends an empty flag or a full flag signal to the programmable logic device 8, The programmable logic device 8 inputs a read strobe rf_rd * signal.

In addition, the central processing unit 7 performs an interrupt service routine immediately upon receiving the OAM interrupt signal (oam_int *) from the programmable logic device 8, and in the interrupt service routine, the cell of the OAM FIFO from the programmable logic device 8 is executed. It reads and confirms which function to perform in the OAM cell and then performs proper operation.

That is, the central processing unit 7 reads and writes to the OAM FIFO unit 6 when the OAM FIFO unit 6 has a certain position in the memory map of the central processing unit 7 so that the corresponding address appears on the address bus. It is possible for the programmable logic device 8 to recognize this address and to control reading and writing to the RX and TX FIFO devices 6a and 6b in the OAM FIFO section 6.

For example, when the data length of the RX and TX FIFO devices 6a and 6b of the central processing unit 7 is 8 bits and the data length of the central processing unit 7 is 32 bits, the following address area is pre-allocated. Will be.

In addition, in order for the central processing unit 7 to write a specific OAM cell to the OAM FIFO unit 6 and send it to the ATM network, the central processing unit 7 needs the address (A + 4) corresponding to the TX FIFO unit 6b. You have to export the data.

Accordingly, the central processing unit 7 transmits the OAM cell signal generated by the central processing unit 7 by the programmable logic unit 8 in the OAM FIFO unit 6 when the OAM cell signal is desired to be inserted. The write strobe (tf_wr *) signal is input to the FIFO device 6b.

Then, the TX FIFO device 6a checks the data state by the input write strobe (tf_wr *) signal and sends an empty flag or a full flag signal to the programmable logic device 8. The flowable logic device 8 outputs a read strobe (tf_rd *) signal to the physical layer processor 2.

In addition, when the programmable logic device 8 recognizes an address corresponding to the TX FIFO device 6b, the programmable logic device 8 blocks the data path from the ATM layer processor 4 to the physical layer, and the OAM cell data to the central processing unit 7. Send a signal (oam_act *).

Therefore, the central processing unit 7 applies the OAM cell signal to the physical layer processor 2 through the output data bus of the physical layer, and the physical layer processor 2 outputs the input OAM cell signal to the ATM network. It will work.

As described above, the present invention minimizes unnecessary time delay by confirming whether or not the OAM cell detection unit is an OAM cell, so that when the OAM cell signal is desired to be sent to the ATM network, it is possible to perform real-time processing by using a fast FIFO instead of a memory. It is effective.

Claims (3)

A physical layer processor (2) that inputs and outputs a cell signal input from the ATM network (1) as data of a physical layer, and checks the cell contents of the data signal input from the physical layer processor (2) to determine whether or not it is an OAM cell. OAM detector 5 for processing and outputting, an ATM layer processor 4 for processing and outputting an OAM cell data signal input from the OAM detector 5, and an OAM cell data signal input from the ATM layer processor 4 An OAM FIFO section 6 providing a path for the central processing unit 7 to transmit and receive a signal; a programmable logic device 8 for controlling a signal related to a signal of the OAM FIFO section 6; and the programmable logic device ( The OAM function processing support device of the asynchronous transmission mode (ATM) terminal, which comprises a central processing unit (7) for transmitting and receiving the OAM signal through the OAM FIFO (6) according to the control signal of 8). The inverted cell signal RCELD [0: 3] is received through the physical layer input data bus of the physical layer processor 2, and the inverted cell signal and programmable logic are received. A first AND gate 5A for ANDing the second byte count signal Count2 of the apparatus 8 and inputting the result to the clock terminal of the first di flip-flop 5g; The cell signal RCELD [0: 7] input through the input data bus of the physical layer of the physical layer processor 2 is applied and the inverted cell signal and the third byte count signal Count3 of the programmable logic device 8 are counted. ) Is received and ANDed and input to the clock terminal of the second flip-flop 5g through the second AND gate 5b and the physical layer data bus of the physical layer processor 2. The inverted cell signal RCELD [4: 5] is applied and the fourth byte count signal Count4 of the programmable logic device 8 is simultaneously received. A third AND gate 5c for receiving AND AND and inputting the result to the first OR gate 5i, and an input data bus of a physical layer of the physical layer processor 2 The cell signal RCELD [4, 5, 7] inputted through the received signal and the inverted signal and the cell signal RCELD [6] inputted through the physical layer data bus are simultaneously processed. A fourth AND gate 5d for receiving a 4-byte count signal Count4 and ANDing the result and inputting the result to the first OR gate 5i, and the physical layer processor 2 The inverted cell signal (RCELD [1, 2]) is applied through the input data bus of the physical layer of the programmable logic device simultaneously with the inverted signal and the signal (RCELD [1]) input through the physical layer data bus. The fourth byte count signal (Count4) of 8) is applied and logically ANDed, and the result is input to the second OR gate 5l. The cell signal RCELD [2] input through the fifth AND gate 5e and the input data bus of the physical layer of the physical layer processor 2 is received, and the inverted signal and the physical layer data bus. A fourth byte count signal Count4 of the programmable logic device 8 is applied and ANDed simultaneously with the cell signal RCELD [1, 3] through the second OR gate 51. ) Is ORed together with the sixth AND gate 5f and the signals input from the third and fourth AND gates 5c and 5d, and the result is converted into a third flip-flop 5j. The OR of the first OR gate 5i input to the clock terminal of the signal and the signals input from the fifth and sixth AND gates 5e and 6f are ORed, and the result thereof is the seventh end. The AND signal of the second OR gate 5l input to the AND gate 5g and the signals input from the first, second, and third flip-flops 5g, 5h, 5j are ANDed. And input the result to the NOR gate (5m) Is a programmable logic device 8 for the OAM detection signal oam_flag * obtained by knocking a signal input from a seventh AND gate 5k and the seventh AND gate 5k and the second OR gate 5l. The OAM function processing support device of the asynchronous transmission mode (ATM) terminal which consists of the NOR gate (5m) output to The control signal of the programmable logic device 8 according to claim 1, wherein the OAM FIFO unit 6 transmits a signal RCELD [0: 7] applied through an input data bus of a physical layer of the physical layer processor 2. TX FIFO device 6b for transmitting and receiving the OAM cell signal of the central processing unit 7 to the physical layer processor 2 by the control signal of the programmable logic device 8 and the RX FIFO device 6a for transmitting and receiving according to the present invention. Apparatus for processing OAM function of an asynchronous transmission mode (ATM) terminal.