KR0150601B1 - High speed d flip flop - Google Patents

Abstract

The present invention limits the operation speed of the D flip-flop and designs a latch circuit with a stack structure that temporarily stores information by using a non-stacked logic method, thereby improving the operation speed of the flip flop. To reduce the load capacitance component of the clock signal by using a small number of transistors, a P-channel first MOS transistor in which an input signal D of a flip-flop is applied to a gate and a source is connected to a supply power supply V _DD . 31, an N-channel second MOS transistor 33 having an input signal D of the flip-flop applied to a gate, and a source of which is grounded, and a clock signal CLK being applied to the gate, and the source being the N-channel first source. An input terminal 3 consisting of an N-channel first MOS transistor 32 connected to the drain of the 2 MOS transistor 33 and used as a first output terminal 34 by sharing a drain with the P-channel first MOS transistor 31. 0) and a P-channel second MOS transistor 41a and a clock signal CLK having a gate connected to the first output terminal 34 of the input terminal 30 and a source connected to a supply power supply V _DD . A first raceway inverter 41 comprising an N-channel third MOS transistor 41b applied and having a source grounded and a drain shared with the P-channel second MOS transistor 41a, and the P-channel second MOS A N-channel fourth MOS transistor 42b having a gate connected to the drain of the transistor 41a and a source grounded and a clock signal CLK are applied to the gate, and a source connected to a supply power supply V _DD . It consists of an output stage 40 composed of a second raceway inverter 42 composed of a P-channel third MOS transistor 42a which is used as the second output terminal 43 by sharing a drain with the four MOS transistors 41b. It is a high-speed D flip flop characterized in that.

Description

High Speed D-Flip Flop

1 is a circuit diagram of a conventional D flip flop.

2 is a circuit diagram of a high-speed D flip flop using the present invention raceway latch.

3 is a raceway latch circuit diagram of the present invention.

4 is an operation diagram showing the operation of each part of the latch circuit in the present invention.

5 is an operation diagram showing the operation of each part of the present invention D flip flop.

* Explanation of symbols for main parts of the drawings

30: input terminal 34: first output terminal

40: output terminal 43: second output terminal

41: first raceshowwood inverter 42: second raceshowwood inverter

D: Input signal of flip flop CLK: Clock signal

Q ₁ : Input signal of the latch circuit Q ₂ : Output signal of the first layout converter

Q ₃ : Output signal of latch circuit QB: Output signal of flip flop

MP ₁ to MP ₄ : P-channel MOS transistors

MN ₁ to MN ₅ : N-channel MOS transistor

31, 41a, 42a: P channel first to third MOS transistors

32, 33, 41b, 42b: N-channel first to fourth MOS transistors

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D flip-flop of dynamic structure using a CMOS device (or process). Specifically, a latch circuit for temporarily storing information is designed by a ratiowise logic technique in which a state is determined by competition of transistors. The present invention relates to a high-speed D flip flop that can be used for a high speed prescaler or the like.

In the conventional D flip-flop having a dynamic structure using a CMOS device, as shown in FIG. 1, an input signal D is applied to a gate, and a source MP ₁ is connected to a supply power supply V _DD . The input signal D is applied to the gate, the source of which is grounded transistor MN ₁ , the clock signal CLK is applied to the gate, the source is connected to the drain of the transistor MP ₁ , the drain is the transistor ( The input terminal 10 composed of the transistor MP ₂ connected to the drain of the MN ₁ ), the clock signal CLK is applied to a gate, and the source MP ₃ connected to the supply power supply V _DD , and the clock signal. CLK is applied to the gate and is connected to the drain of the transistor MN ₃ whose source is grounded, and the first semi-conductor 21 comprising a transistor MN ₂ , whose source is connected to the transistor MN ₃ , and The output of the first inverter 21 goes to the gate And the source is supplied to the power transistor coupled with the (V _DD) (MP ₄₎ and the first output of the inverter 21 is applied to the gate of the source is grounded transistor (MN _5), a clock signal (CLK) Is applied to the gate, the drain of which is connected to the drain of the transistor (MP ₄ ) and the output terminal 20 consisting of a second inverter 22 composed of a transistor (MN ₄ ) whose source is connected to the drain of the transistor (MN ₅ ) ).

The conventional D flip-flop has a double inversion structure composed of the input terminal 10 and the output terminal 20, and thus a path for directly connecting the input signal D to the output signal QB is not formed.

When the clock signal CLK changes from 1 to 0, the output stage 20 stores the previous state while the input stage 10 receives the input signal D to be used as the next output. When the clock signal CLK is changed from 0 to 1, the output terminal 20 emits a new output value according to the stored input value.

In addition, a stack structure is used at the output stage 20 to store the signal input from the input stage 10, which increases the equivalent resistance value in the circuit, thereby increasing the RC time constant. In addition, increasing the RC time constant will limit the operating speed of the D flip flop.

In order to improve the operation speed of the conventional D flip-flop, the on-resistance value of the switch transistors MP ₂ , MP ₃ , MN ₃ and MN ₄ using the clock signal CLK as a gate input should be reduced. The size of each switch transistor MP ₂ , MP ₃ , MN ₃ , MN ₄ is increased. However, as shown in FIG. 1, the load capacitance component for the clock signal CLK is four because the number of the switch transistors MP ₂ , MP ₃ , MN ₃ , MN ₄ using the clock signal CLK as the gate input is _four . Since the size of the switch transistors MP ₂ , MP ₃ , MN ₃ , MN ₄ must be limited in order to keep the size small, the size of the switch transistors MP ₂ , MP ₃ , MN ₃ , MN ₄ may be increased. There is a problem that a limit occurs in improving the operation speed.

SUMMARY OF THE INVENTION An object of the present invention is to solve the conventional problems as described above, by using a latched logic technique to design a latch circuit for temporarily storing digital information while avoiding a stack structure and using the latch circuit. To provide a high-speed D flip flop that can be used in a high-speed prescaler.

Hereinafter, the technical configuration of the present invention in detail.

In the D flip-flop of the present invention, as shown in FIG. 2, the P-channel first MOS transistor 31 having an input signal D applied to a gate and a source connected to a supply power supply V _DD , and the input signal ( D) is applied to the gate and the N-channel second MOS transistor 33 whose source is grounded, a clock signal CLK is applied to the gate, and the source is connected to the drain of the N-channel second MOS transistor 33 and the An input terminal 30 composed of an N-channel first MOS transistor 32 used as the first output terminal 34 by sharing a drain with the P-channel first MOS transistor 31 and the first output terminal of the input terminal 30. A P-channel second MOS transistor 41a and a clock signal CLK, to which a gate is connected to a source and a source is connected to a supply power supply V _DD , are applied to a gate, a source is grounded, and a drain is connected to the P-channel second. First channel composed of an N-channel third MOS transistor 41b shared with the MOS transistor 41a A gate is connected to the showwood inverter 41, a drain of the P-channel second MOS transistor 41a, and a N-channel fourth MOS transistor 42b and a clock signal CLK having a source grounded to the gate. A second layer comprising a P-channel third MOS transistor 42a connected to a supply power supply V _DD and sharing a drain with the N-channel fourth MOS transistor 41b to be used as a second output terminal 43. It is characterized by the technical configuration of the output stage 40 composed of the showwood inverter 42.

First, FIG. 3 shows only the first and second raceway inverters 41 and 42 used in the output stage 40 of FIG. ₂ , and temporarily inputs the input signal Q ₁ without forming a stack structure. It is a raceway latch circuit to store. That is, when the clock signal CLK is 1, the output signal Q ₃ maintains its previous state regardless of the input signal Q ₁ applied. When the clock signal CLK is 0, the output signal Q _{3 is maintained.} Outputs a low voltage (0) when the input signal (Q ₁ ) is 0, and a high voltage (1) determined as a supply voltage (V _DD ) when the input signal (Q ₁ ) is 1.

Table 1 is a truth table showing the operation of the third-degree raceway latch circuit according to the clock signal CLK and the input signal Q, and with reference to Tables 1, 3, and 4, The operation of the latch circuit will be described in detail as follows.

First, the N-channel third MOS transistor 41b is turned on while the clock signal CLK is 1, and in this state, when the input signal Q of the latch circuit becomes 0, the P-channel second and N-channel third MOSs are zero. The transistors 41a and 41b are simultaneously turned on, and the output signal Q of the first racewood inverter is determined by competition between the two transistors 41a and 41b. In this case, regardless of the input signal Q of the latch circuit, the output signal Q of the first layout converter is lower than the threshold voltage V of the N-channel fourth MOS transistor 42b. If the ratio of the channel width / channel length (W / L) of the P-channel second and N-channel third MOS transistors 41a and 41b is controlled to be maintained, the N-channel fourth MOS transistor 42b is configured to control the clock. The signal CLK remains in the OFF state while being one. In addition, since the P-channel third MOS transistor 42a is also turned off while the clock signal CLK is 1, both the pull-up and pull-down of the output signal Q of the latch circuit are impossible. .

Therefore, when the clock signal CLK is 1, the raceway latch circuit does not affect the output signal Q of the latch circuit because the change of the input signal Q of the latch circuit does not affect the output signal of the latch circuit. (Q) keeps the previous state.

Secondly, the N-channel third MOS transistor 41b is turned off while the clock signal CLK is zero, and the P-channel second MOS transistor 41a when the input signal Q of the latch circuit applied in this state is zero. ) Is turned on so that the output signal Q of the first racewood inverter is raised to the supply voltage V. Then, the N-channel fourth MOS transistor 42b is turned on and the P-channel third MOS transistor 42a is also turned on, so that competition between the P-channel third and N-channel fourth MOS transistors 42a and 42b occurs. As a result of the competition between the two transistors 42a and 42b, a low voltage 0 is output to the output signal Q of the latch circuit.

When the clock signal CLK is 0 and the input signal Q of the latch circuit is 0, the low voltage of the output signal Q of the latch circuit is the next logic circuit which inputs the output signal Q of the latch circuit. It should be designed to be smaller than the maximum value of voltage that can be applied to the input side of the next logic circuit so that the output of can provide stable voltage. To satisfy this condition, the P-channel third and N-channel fourth MOS transistors 42a and 42b such that the pull-down intensity of the N-channel fourth MOS transistor 42b is greater than that of the P-channel third MOS transistor 42a. It is to be designed by adjusting the ratio of channel width / channel length (W / L).

In addition, when the input signal Q of the applied latch circuit is 1 and the clock signal CLK changes from 1 to 0, both the P-channel second and N-channel third MOS transistors 41a and 41b are turned off. Since the output signal Q of the first layout converter is a ground state. Since the output signal Q of the first layout converter is lower than the threshold voltage V of the N-channel fourth MOS transistor 42b, the N-channel fourth MOS transistor 42b is turned off and the clock is turned off. Since the signal CLK is 0, the P-channel third MOS transistor 42a is turned on so that the output signal Q of the latch circuit rises to the supply voltage V by the P-channel third MOS transistor 42a. The voltage 1 is output.

As such, the high voltage (1) of the output signal (Q) of the first racewood inverter and the output signal (Q) of the latch circuit in the raceway latch circuit is the supply voltage (V), and the low voltage (0) is grounded. There are two things: the voltage and the low voltage due to the competition of the two transistors.

However, in the raceway latch circuit of FIG. 3 that operates as described above, when the clock signal CLK is 0, the input signal Q of the latch circuit is 1 as shown in section A of FIG. When it falls to zero, the output signal Q _{3 to the} latch arc changes from 1 to 0 in response to the change of the input signal Q ₁ even though the clock signal CLK is stable to zero. Therefore, the D flip-flop whose state changes only at the transition of the clock signal CLK cannot be implemented using only the raceway latch circuit of FIG. 3.

Referring to FIG. 2, a high-speed D flip-flop having a dynamic structure using such a raceway latch circuit will be described.

In order to implement a D flip-flop whose state changes only when the clock signal CLK is transitioned using the layout wood latch circuit as shown in FIG. 3, the input signal D is applied to the gate, and the source is supplied with a power supply ( A P-channel first MOS transistor 31 connected to V _DD ), an N-channel second MOS transistor 33 having a source grounded with the input signal D applied thereto, and a clock signal CLK An N-channel first MOS transistor having a first output terminal 34 connected to the drain of the N-channel second MOS transistor 33 and sharing a drain with the P-channel first MOS transistor 31. An input terminal 30 composed of 32 and an output terminal 40 composed of the raceway latch circuit connected to the first output terminal 34 of the input terminal 30 are provided.

Then, in the fast D flip-flop of the present invention, when the clock signal CLK is 0, the N-channel first MOS transistor 32 is turned off, so that the voltage value of the input signal Q ₁ of the output terminal 40 is Since it does not fall to zero, the state changes only when the clock signal CLK is changed.

The operation of the D flip flop according to the present invention will be described in detail. When the clock signal CLK is 1, the input unit 30 receives the input signal D of the flip flop and receives the P-channel first and N-channel first MOSs. The input signal D is stored in a parasitic capacitor comprising a capacitor of the drain junction of the transistors 31 and 32 and a capacitor of the P-channel second MOS transistor 41a, and the stored input signal D is output to the output unit 40. In other words, it is used as an input signal Q ₁ input to the gate of the P-channel second MOS transistor 41a of the raceway latch circuit.

Truth therapies showing the operation of high-speed D flip flops

Table 2 shows the truth value of the fast D flip flop operated according to the clock signal CLK and the input signal D of the flip flop. The flip flop output signal QB is the input signal D of the flip flop. It is reversed.

First, referring to Table 2, the operation of the input terminal 30 will be described as follows.

The N-channel first transistor 32 is turned on while the clock signal CLK is 1, and in this state, when the input signal D of the flip-flop is 0, the P-channel first transistor 31 is turned on and N Since the supply voltage V is output from the first output terminal 34, which is the output terminal of the input terminal 30, because the channel second transistor 33 is turned off, the channel second transistor 33 is high as the input signal Q of the output terminal 40, that is, the latch circuit. Voltage 1 is applied. In addition, when the clock signal CLK is 1 and the input signal D of the flip flop is 1, the P-channel first transistor 31 is turned off and the N-channel first and second transistors 32 and 33 are turned on. The first output terminal 34 is grounded, and a low voltage 0 is applied to the input signal Q of the latch circuit.

In addition, the N-channel first transistor 32 is turned off while the clock signal CLK is 0. In this state, when the input signal D of the flip flop is 0, the P-channel first transistor 31 is turned on. Since the N-channel second transistor 33 is turned off and the supply voltage VD is output from the first output terminal 34, the high voltage 1 is applied to the input signal Q of the latch circuit. In addition, when the input signal D of the flip flop is 1 and the clock signal CLK is changed from 1 to 0, the N-channel first transistor 32 is turned off, and the P-channel first transistor 31 is turned off, N Since the channel second transistor 33 is turned on and the first output terminal 34 maintains the ground state, a low voltage 0 is applied to the input signal Q of the latch circuit.

In the state where the clock signal CLK is 0 and the N-channel first MOS transistor 32 is off, the input terminal 30 has an input signal D of flip-flop 0 as in section A of FIG. Since the voltage of the first output terminal 34 does not drop to 0 even when the value is changed to 1, the input signal Q _{1 of} the latch circuit does not fall to 0, so the input signal Q ₁ of the latch circuit is a clock signal. Only when (CLK) is changed does the state change.

Thus, the input terminal 30 supplies the supply voltage V _DD to the output terminal 40 at the high voltage 1 according to the clock signal CLK and the input signal D of the flip-flop, and the low voltage (0). The output voltage D is changed from 0 to 1 when the clock signal CLK is stabilized to 0, which affects the output terminal 40, that is, the input signal Q ₁ of the latch circuit. Therefore, the D flip flop whose state changes only when the clock signal CLK changes is implemented.

As shown in Table 2, when the clock signal CLK is 1, the output terminal 40 is connected to the second output terminal 43 regardless of the input signal Q ₁ of the latch circuit applied from the input terminal 30. The output of the previous state is maintained as it is with the output signal QB of the flip-flop.

In addition, the output terminal 40 changes the output signal QB of the flip-flop according to the input signal Q ₁ of the latch circuit applied when the clock signal CLK is zero. That is, a high voltage (1) If this is the second output supply voltage (V _DD) to an output signal (QB) of the flip-flop in the 43 of the latch circuit the input signal (Q ₁₎ to the supply voltage (V _DD) When a high voltage of 1 is outputted and a low voltage (0) is applied to the input signal Q ₁ of the latch circuit, the low voltage (0) is output from the second output terminal 43 to the output signal QB of the flip-flop. Is output.

As such, the input signal D of the flip-flop applied to the input terminal 30 is inverted and output through the D flip-flop.

Then, as in section A of FIG. 5, when the clock signal CLK is zero, the input signal D of the flip-flop is zero. In the case of changing to 1, the N-channel first MOS transistor 32 is turned off, so that the input signal Q ₁ of the latch circuit does not fall to zero, so that the clock signal CLK is stable to zero. The change of the input signal D of the flip-flop does not affect the output terminal.

As described above, in the D flip-flop of the present invention, only the input signal D of the flip-flop input at the transition of the clock signal CLK affects the output side and changes the output signal.

As described above, the high-speed D flip-flop of the present invention uses a raceway latch circuit having no stack structure to reduce the propagation delay time to improve the operation speed and to use the clock signal as the control signal of the gate terminal. It is useful to reduce the number of transistors to reduce the load capacitance component to the clock signal.

Claims (2)

A P-channel first MOS transistor having an input signal of a flip-flop applied to a gate and a source connected to a supply power supply, an N-channel second MOS transistor having an input signal of the flip-flop applied to a gate, and having a grounded source, and a clock signal Is an N-channel first MOS transistor connected to a drain of the N-channel second MOS transistor and used as a first output terminal by sharing a drain with the P-channel first MOS transistor; A P-channel second MOS transistor having a gate connected to the first output terminal of the input terminal and a source connected to a supply power supply, a clock signal applied to the gate, a source being grounded, and a drain being shared with the P-channel second MOS transistor An N-channel third MOS transistor, the first raceway inverter comprising a gate, and a gate connected to a drain of the P-channel second MOS transistor; N-channel fourth MOS transistor having a source grounded, a clock signal applied to a gate, a source connected to a supply power supply, and a P-channel third MOS used as a second output terminal by sharing a drain with the N-channel fourth MOS transistor. A second Rayshaw wood inverter composed of transistors and an output stage composed of transistors eliminates the stack structure of the output stage that limits the operation speed of the flip flop using the Rayshaw wood logic technique to improve the operation speed and load the clock signal. A high speed D flip flop, characterized by reducing capacitance components. 2. The P channel of claim 1, wherein when the clock signal is 1 and the input signal of the output terminal is 0, the P-channel second and N-channel third MOS transistors of the first layout inverter are simultaneously turned on. By adjusting the ratio of the channel width / channel length (W / L) of the N-channel third MOS transistor, the voltage output from the first layout converter and input to the second layout converter is an N-channel fourth. Since the voltage is lower than the threshold voltage of the MOS transistor, the N-channel fourth MOS transistor is kept off while the clock signal is 1, so that the change of the input signal does not affect the output signal. Flip flop.