KR0150148B1 - Performance data processing apparatus and method - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Performance data detection device for maintenance of transmission device

2. The technical problem to be solved by the invention

Ensuring the reliability of performance data representing the cumulative error of data transmission / reception of transmission device and increasing processing efficiency

3. Summary of Solution to Invention

According to the present invention, the counter buffer only counts the accumulated performance data without resetting, the performance data accumulation processing unit accumulates the valid performance data and deletes the invalid performance data, and the interrupt cycle generator generates the accumulation cycle and the reporting cycle. Since it is set arbitrarily, it ensures reliability of performance data and increases processing efficiency.

4. Important uses of the invention

Maintenance of the transmission

Description

Performance data processing device and processing method

1 is a block diagram of a conventional performance data detection device.

2 is a block diagram of a performance data processing apparatus of the present invention.

3 is a control flowchart of the timer interrupt processing unit of FIG.

4 is a control flow chart of a performance data accumulator of FIG.

5 is a flow chart of the subroutine control of the BIP, PER, and BPV data accumulators in the performance data accumulator.

6 is a control flowchart of the performance data report processing unit 70.

* Explanation of symbols for main parts of the drawings

40: accumulator for performance data 50: interrupt cycle generator

60: performance data storage unit 70: performance data reporting processing unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to maintenance of a transmission apparatus, and more particularly, to an apparatus and a method for processing performance data indicating a degree of data transmission / reception error accumulation of a transmission apparatus.

1 shows a block diagram of a performance data detection device.

The DS3 receiver 10 receives an asynchronous DS3-class (45 MHz unit) signal of a transmitter, detects a bipolar violation (hereinafter referred to as BPV) error of this signal, and outputs the signal to the BPV counter buffer 18. It performs a stuffing function to form a payload C3. When the asynchronous DS3 signal, which is an analog signal, performs the function described above, it is converted to digital and output to the receiving FIFO memory 12. The reception FIFO memory 12 stores a signal output from the DS3 receiver 10, and the mapper 14 errors a parity bit (hereinafter referred to as PER) in the signal output from the reception FIFO memory 12. Is detected and output to the PER counter buffer 22, mapped to the VC3 format specified in the CCITT Recommendation, and output to the BISDN transmitter 16. The BISDN transmitter 16 converts and transmits data of a data rate required for BISDN, for example, 51 MHz.

The BISDN receiving unit 26 is called BIP-8 in a manner of receiving data output from the BISDN and determining a path overhead error by examining B3 bytes in the path overhead when detecting a frame unit signal. An error is detected and output to the BIP counter buffer 24, and the V3 format is de-mapped to be output to the transmission FIFO memory 30. The transmit FIFO memory 30 stores the signal output from the demapper 28, and the DS3 transmitter 32 converts the signal output from the transmit FIFO memory 30 into a DS3-class signal and converts it into an analog signal. Convert it and send it to the transmission device.

At this time, the BPV counter buffer 18 accumulates the number of BPV errors output from the DS3 receiver 10, and the PER counter buffer 22 accumulates the number of PER errors received from the mapper 14, and the BIP counter buffer ( 24 accumulates the number of BIP errors output from the BISDN receiver 26. Counter buffers are generally composed of two bytes, and are designed to automatically reset when the processor 20 reads an accumulated error count or overflow occurs. (In case of reading the accumulated count, the circuit logic is implemented to reset by delaying several milliseconds.)

The processor 20 reads and stores an error accumulated value in the BPV counter buffer 18, the PER counter buffer 22, and the BIP counter buffer 24 at a predetermined interrupt period. In this case, it should be noted that the accumulated error value is performance data. The state of the performance data stored in the storage unit is transmitted to the upper processor by the module that analyzes and processes the performance data, and the upper processor provides the user with an alarm such as an alarm in response to the data value.

As described above, the performance data detection apparatus of FIG. 1 stores the detected error accumulation value in each counter buffer, and when the processor reads it, the counter buffer is automatically reset after a few milliseconds and automatically resets even if an overflow occurs. If an overflow occurs after a read, that performance data is lost. Therefore, in order to prevent loss of performance data, there is a difficulty in designing the detection circuit in consideration of the maximum storage time of the counter buffer and the period in which the processor reads the error accumulation value. That is, when the capacity of the counter buffer is increased, there is a limitation due to the existing standard, and when the processor sets the read cycle quickly, there is a problem that reliability of performance data is not secured.

Accordingly, an object of the present invention is to provide a performance data processing apparatus and processing method that ensures the reliability of the performance data.

Another object of the present invention is to provide a performance data accumulation method that does not affect the performance data even when an overflow of the counter buffer occurs.

The present invention for achieving the above object, in the performance data detection device for the maintenance of the transmission device, the first interrupt generation period signal for accumulating the performance data and the second interrupt generation period signal for the performance data reporting processing Is the interrupt cycle generating means for generating a? And first, second and third performance data accumulated values corresponding to the number of bipolar violation errors, parity bit errors, and overhead errors when the first interrupt generation cycle signal is applied? In response to the initial performance data of the city and the cumulative limit alarm value indicating that the line is broken, the storage processing, performance data accumulation cycle, and performance data reporting period are set as total accumulation values of the first, second, and third performance data, respectively. Performance data accumulation processing means for controlling the interrupt period generating means and the first, A performance data storage means for storing the total accumulated values of the second and third performance data, respectively, and a total accumulated value of the first, second, and third performance data stored in the performance data storage means when the second interrupt generation cycle signal is generated; It is characterized by comprising a performance data reporting processing means for processing and reporting according to the format of the upper processor.

In addition, the present invention, in the performance data accumulation processing method of the performance data detection apparatus, the first process for generating a first interrupt generation period signal for the performance data accumulation processing and the second interrupt generation period signal for the performance data reporting processing and First performance by reading performance data values corresponding to bipolar violation errors, parity bit errors, and overhead check errors stored in the first, second, and third counter buffers in response to the first interrupt generation cycle signal, respectively. A second process of determining whether the data is data; a third process of clearing the initial performance data value in response to the performance data in the determination of the second process; and a response of not being performance data in the judgment of the fraudulent second process. A fourth step of calculating a real cumulative value by subtracting a cumulative value up to the present of the performance data value by a previous cumulative value previously read; A fifth step of determining whether the cumulative limit alarm value is greater than the cumulative limit alarm value; a sixth step of clearing the actual cumulative value if the actual cumulative value is greater than the cumulative limit alarm value in the fifth step; and the fifth step If the actual cumulative value is less than the cumulative limit alarm value, the seventh step of storing the total accumulated data of the performance data plus the actual cumulative value in the predetermined storage area and the second interrupt generation period signal In response, an eighth step of processing the total accumulated value stored in the storage area in a message format suitable for the higher processor and reporting the same to the higher processor.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, the counter buffers 18, 20, and 22 according to the present invention are read by the performance data accumulating processor 40 by the configuration of the performance data processing apparatus of FIG. 2 and the control operations of FIGS. It is designed to only keep counting without clearing. Accordingly, when the counter buffers become full, the counter buffers count up again from the beginning.

2 is a block diagram of a performance data processing apparatus of the present invention, which is implemented in the processor 20 of FIG. 1, and includes a performance data accumulation processing unit 40, an interrupt cycle generating unit 50, a performance data storage unit 60, Performance data reporting processing unit 70 and the alarm processing unit 80 that informs the disconnection of the transmission line.

The interrupt cycle generator 50 is composed of a timer interrupt 54 and a timer counter 52. The interrupt cycle generator 50 performs a subroutine as shown in FIG. 3 to set a performance data accumulation cycle and a performance data reporting cycle. The timer counter 52 includes a cumulative timer counter and a reporting timer counter, and the cumulative timer counter sets a cumulative timer counter value under the control of the performance data accumulation processor 40, and then the reporting timer counter is a performance data reporting processor. The counting timer counter value is set by the control of 70, and then down counting is performed. The timer interrupt 54 applies the interrupt enable signal INT1 to the performance data accumulation processing unit 40 when the counting value of the cumulative timer counter is 0, and interrupts the performance data accumulation processing unit 40 when the counting value of the reporting timer counter is 0. Enable signal INT2 is applied.

The operation of the interrupt cycle generator 50 will be described in more detail with reference to FIGS. 2 and 3. The interrupt cycle generation unit 50 checks whether the cumulative timer counter flag set signal SET1 is applied from the performance data accumulation processing unit 40 in step 300, and if so, proceeds to step 302 and accumulates the accumulation data provided by the performance data accumulation processing unit 40. The count value is set in the accumulated timer counter. At this time, the cumulative count period of the performance data set may be several milliseconds. Therefore, in step 308, the value of the cumulative timer counter is down counted by one.

In addition, in step 304, the performance data report processor 70 checks whether the reporting timer counter flag set signal SET2 is applied. If it is, the controller proceeds to step 306, and the cumulative count value provided by the performance data reporting processor 70 is accumulated in the accumulated timer counter. Set. In this case, the set performance data report count period may be several seconds, for example. Therefore, in step 308, the value of the report timer counter is down counted by one.

The interrupt cycle generator 50 determines whether the cumulative timer counter count is 0 in step 310 of performing step 308. Then, in step 312, the performance data accumulation processor 40 uses the timer interrupter 54. Outputs the first interrupt enable signal INT1. In step 308, the controller determines whether the value of the reporting timer counter is 0 in step 314. Then, in step 316, the second interrupt enable signal is transmitted to the performance data reporting processor 70 using the timer interrupter 54. Output INT2.

Returning to FIG. 2 again, the performance data accumulating processor 40 responds to the first interrupt enable signal INT1 output from the interrupt period generating unit 50. The BPV counter buffer 18 shown in FIG. FIG. 4 shows whether the first, second and third performance data accumulated values corresponding to the number of bipolar violation errors, parity bit errors, and overhead errors stored in the counter buffer 22 and the BIP counter buffer 24 are valid data. And it is determined as the control flow of FIG. 5 and stored in the performance data storage 60 if valid.

The control operation of the performance data accumulator 40 of FIG. 2 will be described in more detail with reference to FIG. 4. When the first interrupt enable signal SET1 is applied in step 400 of FIG. 4, the performance data accumulating processor 40 proceeds to steps 402, 404, and 406, and includes the BPV data accumulation processor 42 and the PER data accumulation processor. 44, the BIP data accumulation processing unit 46 controls to perform the subroutine of FIG. Control operations of the BPV, PER, and BIP data accumulation processors 42, 44, and 46 in the performance data accumulation processor 40 will be performed as shown in FIG. In FIG. 5, a control operation of the BPV data accumulation processor 42 performed in step 402 of FIG. 4 is described as an example, and replaces the control operations of the remaining PER and BIP data accumulation processors 44 and 46.

Referring to FIG. 5, in operation 500, a cumulative value of performance data corresponding to the number of bipolar violation errors stored in the BPV counter buffer 18 shown in FIG. 1 is sequentially read. Thereafter, in step 502, the first performance data flag is determined to determine whether the accumulated performance data value is the first performance data to be applied. The performance data accumulator 40 automatically sets the initial performance data flag upon power-up. If the flag is set, the BPV data accumulation processor 42 recognizes the initial performance data and proceeds to step 504 to read the current performance data. The data accumulation value is stored in the previous and current performance data accumulation value storage areas in the BPV storage unit 62 of the performance data storage unit 60, and the initial performance data flag is reset. If the first performance data is not determined in step 502, the current performance data accumulated value is stored only in the current performance data accumulated value storage area of the BPV storage unit 62 of the performance data storage unit 60 by performing step 505. Proceed to step.

In operation 506, the BPV data accumulation processor 42 calculates an actual cumulative value by subtracting the accumulated value stored in the previous performance data accumulation value storage area from the accumulated value stored in the current performance data accumulation value storage area. If the read performance data is the first performance data, the actual cumulative value of the performance data will be zero. This is because the same cumulative value is stored in the current and previous performance data accumulation value storage areas.

Clearing the accumulated value of the initial performance data in the present invention can be determined that the performance data at this time is the correct error value since the performance data can be generated by the transient period of the system initial state (for example, noise generation). Because there is not.

Thereafter, the BPV data accumulation processor 42 determines whether the actual cumulative value is greater than the preset cumulative limit alarm value in step 508, and if it is large, the process proceeds to step 514 after clearing the actual cumulative value in step 510. The cumulative limit alarm value is a threshold provided by the alarm processing unit 80 of FIG. 1 when the transmission line is disconnected. The fact that the cumulative limit value is larger than the accumulation limit alarm value means that the transmission line is disconnected. In this case, since the performance data does not give reliability regarding a transmission error, the performance data is cleared at step 510. If the actual cumulative value is smaller than the preset cumulative limit alarm value in step 508, the process proceeds to step 512, and the cumulative total performance data is added by adding the actual performance data accumulated value to the accumulated performance data stored in the previous performance data accumulation value storage area. Calculate After performing step 512, the BPV data accumulation processor 42 proceeds to step 514 to store the entire accumulated value in the previous accumulated value storage area and returns to the main routine of FIG.

In the main routine of FIG. 4, the PER data accumulation processing unit 44 reads the performance data corresponding to the parity bit error temporarily stored in the PER counter buffer 22 of FIG. 1 in step 404. As an example, the control operation as shown in FIG. The stored performance data is stored in the PER storage unit 64 of the performance data storage unit 60, and the BIP data accumulation processing unit 46 is stored in the BIP counter buffer 24 of FIG. 1 in step 406 of FIG. The performance data of the temporarily stored overhead error is read and stored in the BIP compensator 66 of the performance data storage 60, for example, by performing the control operation as shown in FIG.

Thereafter, the performance data accumulating processor 40 performs the step 408 to set the cumulative timer counter flag signal SET1 for setting the performance data accumulating period, outputs it to the timer counter 52, and then ends.

Returning to FIG. 1 again, the operation of the performance data reporting processor 70 will be described. The performance data report processing unit 70 performs an operation in the flow as shown in FIG.

Referring to FIG. 6, when the second interrupt enable signal INT2 output from the interrupt period generation unit 50 is applied in step 600, the performance data report processing unit 70 proceeds to step 602 and performs the performance data storage unit 60. Read the performance data accumulated in the BPV storage unit 62, PER storage unit 64, and BIP storage unit 66 of the data, and report the performance data read in step 604 in a message format suitable for the upper processor, and reporting is completed. When the performance data of the performance data storage unit 60 is deleted. Thereafter, in step 606, the report timer counter signal signal SET2 for setting the report period is output as a set to the timer counter 52 of the interrupt period generating unit 50, and ends.

As described above, in the present invention, the counter buffer only counts the accumulated performance data without resetting, the performance data accumulation processing unit accumulates the valid performance data and deletes the invalid performance data, and the interrupt cycle generation unit accumulates. Since the period and report period are arbitrarily set, there is an advantage of ensuring reliability of performance data and increasing processing efficiency.

Claims (6)

A performance data detection device for maintenance of a transmission device, comprising: an interrupt period generating means for generating a first interrupt generation period signal for accumulating performance data and a second interrupt generation period signal for processing performance data; 1, 2nd, and 3rd performance data accumulated corresponding to the number of bipolar violation errors, parity bit errors, and overhead errors when the interrupt generation cycle signal is applied, indicating that the first performance data and the line are disconnected when the system is powered on. Accumulating performance data to control the interrupt cycle generating means by setting the storage processing and performance data accumulation period and the performance data reporting period as total accumulation values of the first, second, and third performance data in response to the non-limiting alarm value, respectively. The total accumulated values of the first, second and third performance data are respectively controlled by the processing means and the control of the data accumulation processing means. Performance data storage means for storing and performance data for processing and reporting the total accumulated values of the first, second, and third performance data stored in the performance data storage means when the second interrupt generation cycle signal is generated according to the format of the upper processor. Performance data processing apparatus, characterized in that configured as a report processing means. The method of claim 1, wherein the interrupt cycle generating means comprises: a timer counter for counting the performance data accumulation cycle and the performance data reporting cycle by setting control, and the counter of the timer is the performance data accumulation cycle and the performance data reporting cycle. And a timer interrupter outputting the first interrupt enable signal and the second interrupt enable signal in response. The method of claim 1, wherein the performance data accumulating means responds to the fact that the first performance data cumulative value corresponding to the number of bipolar violation errors is not the cumulative limit alarm value indicating that the first performance data and the line are disconnected when the system is powered on. A cumulative limit alarm indicating that the first cumulative processing unit stores the total cumulative value of the first performance data and the second performance data corresponding to the number of parity bit errors is the first performance data and the line is disconnected when the system is powered on. A second cumulative processing unit for storing and storing the total cumulative value of the second performance data in response to the non-value, and the first performance data and the line when the second performance data accumulated value corresponding to the number of overhead check errors is applied to the system. A third cumulative store which is stored as a total cumulative value of the third performance data in response to not being a cumulative limit alarm value indicating disconnection. Performance data processing apparatus characterized in that it constituted by Li. A method of accumulating performance data of a performance data detection device, comprising: reading performance data values corresponding to bipolar violation errors, parity bit errors, and overhead check errors stored in the first, second, and third counter buffers, respectively; A first process of determining whether the performance data is of the second process; a second process of clearing the first performance data value in response to the performance data in the determination of the first process; and not the performance data in the determination of the first process. In response to the third step of calculating the actual cumulative value by subtracting the cumulative value of the performance data value to the present from the previous cumulative value, and determining whether the actual cumulative value is greater than the cumulative limit alarm value indicating that the line is broken. And a fifth step of clearing the actual cumulative value if the actual cumulative value is greater than the cumulative limit alarm value in the fourth process. And a sixth step of storing the total accumulated value obtained by adding the previous accumulated value to the actual accumulated value in a predetermined storage area when the actual accumulated value is smaller than the cumulative limit alarm value. 5. The performance of claim 4, wherein the first, second, and third counter buffers perform cumulative counting until the performance data buffers are pooled in response to the number of bipolar violation errors, parity bit errors, and overhead check errors. How data is processed. A performance data accumulation processing method of a performance data detection device, comprising: a first process of generating a first interrupt generation cycle signal for performance data accumulation processing and a second interrupt generation cycle signal for performance data reporting processing, and the first interruption; In response to the generation cycle signal, it is determined whether the first performance data is read by reading the performance data values corresponding to the bipolar violation error, parity bit error, and overhead check error stored in the first, second, and third counter buffers, respectively. And a third process of clearing the first performance data value in response to the performance data in the determination of the second process, and the performance data value in response to the non-performance data in the determination of the second process. A fourth step of calculating the actual cumulative value by subtracting the cumulative value up to the present from the previous cumulative value, indicating that the actual cumulative value is disconnected from the line; A fifth process of determining whether the cumulative limit alarm value is larger than the cumulative limit alarm value, a fifth process of clearing the actual cumulative value if the actual cumulative value is greater than the cumulative limit alarm value in the fifth process, and the actual at the fifth process A seventh step of storing a total accumulation value of performance data obtained by adding the actual accumulation value to the previous accumulation value when the cumulative value is smaller than the cumulative limit alarm value; and in response to the second interrupt generation period signal; And an eighth step of reporting the upper processor by processing the total accumulated value stored in the storage area in a message format suitable for the upper processor.