KR0150071B1 - Message receiving interface circuit for network of packet transportation protocol - Google Patents

Abstract

The present invention relates to a message receiving inter-circuit circuit for receiving a message sent from an opposite node when a plurality of nodes or processors are connected to an interconnection network, when a node transmits and receives a message using a packet transfer protocol. A packet receiver for receiving data in a packet unit, a message receiver for recovering a message from a received packet unit data, and a memory space for using different buffers according to the packet type are provided. PCI local bus by reading the contents of buffer located in different area of DP-SRAM and DP-SRAM which overlaps packet receiving operation and access of buffer contents through PCI local bus in interconnection network. Or respond to a buffer access request from a PCI local bus It is composed of a PCI bus controller.

Description

Message receiving interface circuit for interconnection network of packet transmission protocol

1 is a diagram showing an example of a conventional omega network.

2 illustrates an example of a conventional generalized shuffle network.

3 is a view showing an example of a conventional hypercube connection network.

4 is an exemplary system of interconnection networks and nodes to which the present invention is applied.

5 is a diagram showing an internal structure of a message receiving interface circuit of a node according to the present invention.

FIG. 6 is a diagram showing the types of packets received by the message receiving interface circuit shown in FIG. 4. FIG.

7 is a flowchart for packet reception.

8 is a flow chart for receiving a message.

9 is a flowchart illustrating the operation of the PCI bus controller.

* Explanation of symbols for the main parts of the drawings

200A to 200N: Mode 210A to 210N: Processor (CPU)

300: interconnection network 310A to 310N: switch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a message receiving interface circuit, and more particularly, to a message receiving interface circuit that receives a message sent from an opposite node when a plurality of nodes or processors are connected to an interconnection network to send and receive messages using a packet transfer protocol between the nodes. It is about.

In general, when a large number of nodes or processors are connected to a packet transmission interconnect, messages from other nodes arrive at the node's message receiving interface circuit.

The message receiving interface circuit manages the messages until the delivered messages are processed by the processor.

The main function of the receiving interface circuit is to receive packets from the network and restore them into a message, and to store the restored message in a buffer or to a memory at a specified address.

It also generates an interrupt to notify the processor that a message has arrived.

Conventionally, there is a method in which a switch performs a path control by using a receiving address as a tag and using each digit of the address.

An example of the Omega network of FIG. 1 using this method is as follows.

Each switch selects an output fork using the corresponding bit in the receive address represented in binary.

If the bit is '0', the input port is connected to output port 0.

On the other hand, if the bit is '1', the input port is connected to the output port '1'.

Applying this, the path control process from the input terminal '000' indicated by the dotted line in FIG. 1 to the output terminal '101' is as follows.

The first switch selects output port '1' because the upper bit of the receive address '101' is '1'.

The next switch selects output port '0' because the second bit of the address is '0'.

The last switch selects output port '1' because the lower bit is '1'.

Therefore, it starts from the input terminal '000' and arrives at the output terminal '101'.

As a more general case compared to the above case, there is a generalized shuffle network shown in FIG.

In this case, as in the omega network, the receiving address is used as a tag, but unlike the omega network, the address of the random number (here b) is used instead of the address of the binary number.

Each switch selects an output port using the corresponding digit at the receive address.

If the digit is 'm', the input port is connected to the output port 'm'.

By applying this, a path control process from the input terminal '0 1' marked with a dotted line in FIG. 2 to the output terminal 'a-1 1' is as follows.

The first switch selects output port 'a-1' because the upper digit of the receive address is 'a-1' and the next switch selects output port 1 because the lower digit of the address is 1.

On the other hand, the hypercube network (Hypercube Network) shown in Figure 3 also uses a '2' binary address as a tag as in the Omega network.

In this case, switches adjacent to each other have only one bit of a different address.

Here, a three-dimensional hypercube connection network is described as an example.

The destination address is a 3-bit binary number and each bit corresponds to the three directions of the topology.

That is, the upper bits of the address correspond to the x direction, the middle bits to the z direction, and the lower bits to the y direction.

The switch compares each bit of the reception address with its own location address bit by bit, and if there are bits having different values, the switch controls the adjacent switch corresponding to one of the bits.

For example, the path control process from '000' to '101' of the 3D hypercube is applied as follows.

The switch located at '000' compares the receiving address '101' and its address bit by bit to find that the upper and lower bits are different.

At this time, select only upper bit and connect with '100' switch in x direction.

The '100' switch compares the receiving address bit by bit and connects them to the '101' switch in the y direction because the lower bits are different from each other.

An object of the present invention is to provide a message receiving interface circuit for receiving a message sent from a counterpart node when a plurality of nodes or processors are connected to an interconnection network, when a node transmits and receives a message using a packet transfer protocol.

In order to achieve the above object, a message receiving interface circuit according to the present invention is a packet receiver connected to an interconnection network for receiving packet data, a message receiver for recovering a message from the received packet data, and a packet. DP-SRAM which provides a memory space for using different buffers according to the form, and provides a dual access port to overlap the packet receiving operation and the access operation of the buffer contents through the PCI local bus in the interconnection network. And a PCI bus controller that reads contents of buffers located in different areas of the DP-SRAM in packet units and sends them to the PCI local bus or responds to a buffer access request generated in the PCI local bus.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

As shown in FIG. 4, the system to which the present invention is applied consists of an interconnection network 300 which is used as a path for message exchange between a plurality of nodes 200A to 200N and each node 200A to 200N. do.

The interconnection network 300 is composed of several switches 310A-310N interconnected, each switch 310A-310N providing a plurality of ports, each of which is separated from each other in input and output.

Ports of each switch 310A-310N are connected to a port 280 located at each node 200A-200N.

When a message is generated at each node 200A-200N, it is sent to each switch 310A-310N constituting the interconnect network 300. The message arrives at the desired nodes 200A-200N via various switches 310A-310N of the interconnect network 300.

Here, the nodes 200A to 200N include a processor 210A to 210N, a processor bus 220, a local bus bridge 230, and a local memory 270.

Here, the processor bus 22 connects the processors 210A to 210N, the local memory 270, and the local bus bridge 230 to each other.

The local bus bridge 230 connects the processor bus 220 and the local bus 240 with each other.

Referring to the operation according to the configuration, the processor 210A to 210N accesses the local bus 240 via the local bus bridge 230 to access the message receiving interface circuit 250 or the transmitting interface circuit 260.

On the contrary, when the local memory 270 is accessed by the message receiving interface circuit 250, the processor bus 220 is accessed via the local bus bridge 230.

The message transmission interface circuits 260 of the nodes 200A to 200N output a message 260 to the port 280 to be sent to other nodes at the request of the processors 210A to 210N.

Messages sent from the other nodes 200A to 200N are input to the message receiving interface circuit 250 via the port 280.

The message receiving interface circuit 250 according to the present invention is connected to the output port 251 of the interconnection network 300 as shown in FIG. 5 and receives a packet received from the nodes 200A to 200N. 252, a message receiver 257 for receiving the packets at the packet receiver 252 and restoring them into a message, a DP-SRAM 255 used as a buffer for storing the received message, and a request for the processor 210A to 210N. PCI bus controller which accesses the message stored in the DP-SRAM 255 or transfers the message temporarily stored in the DP-SRAM 255 to the local memory 270 through the Peripheral Communication Interface (PCI) bus. 260).

Referring to FIGS. 4 to 6, the operation according to the configuration of FIG. 5 is described. When the packet 400 is output from the output port 251 of the interconnection network 300, the packet receiver 252 checks parity on a fleet basis. If there is no error, enter the internal buffer.

Via the packet receiver 252, the packet is stored in a buffer of the DP-SRAM 255.

The packet receiver 252 inputs an information signal 254 for the received packet to the message receiver 257.

The message receiver 257 uses the packet information signal 254 to perform message recovery.

In this message restoration process, the number of packets composing a message, the mode of transmission of the message, and the like are checked.

The DP-SRAM 255 has a space and a buffer for storing several messages at the same time, and are stored in different buffers according to the transmission mode of the message.

The message receiver 257 is responsible for buffer and storage space management of the DP-SRAM 255 and uses the access control signal 256 of the DP-SRAM 255.

Depending on the transmission mode of the message, the message stored in the DP-SRAM 255 is transferred to the local memory 270 or accessed by the processors 210A to 210N.

The message receiver 257 may control the PCI master and target functions of the PCI bus controller 260 through the PCI bus control signal 259.

The PCI bus controller 260 acts as a PCI master when transferring messages from the DP-SRAM 255 directly to the local memory 270.

On the other hand, when the processor 210A to 210N accesses a message stored in the DP-SRAM 255, the PCI bus controller 260 operates as a PCI target.

The packet 400 input to the packet receiver 252 at the output port 251 of the interconnection network 300 is composed of a control fleet 410 and a data fleet 420 as shown in FIG.

Here, the control fleet 410 includes a packet type 411, a packet serial number 412, a packet length 413, and a transmitting node number 414.

Here, the role of each component of the control fleet 410 will be described.

The packet form 411 specifies the purpose or transmission mode of the packet. Examples of the transmission mode that can be specified are broadcast or emergency transmission.

The packet serial number 412 is assigned to each packet when a message is composed of several packets, and used for retransmission of a packet unit when an error occurs or calculation of a packet storage address in a message restoration process.

On the other hand, the packet length 413 may be variable, and at this time, one control fleet 410 and up to 16 data fleets 420 may be configured.

The packet length 413 defines the number of datalets 420 of the packet 400 and is used to accommodate the variable packet structure.

The transmitting node number 414 allows the receiving node to distinguish the transmitting node transmitting each message from each other when simultaneously transmitting messages to one node in multiple transmission modes.

The message receiving interface circuit 250 according to the present invention shown in FIG. 5 has three functions.

First, packet 400 is received at interconnection network 300 and performs parity check.

Second, restore the message in packet 400.

Third, the message is stored in the DP-SRAM 255 or moved to the local memory 270.

The dual packet reception process will be described with reference to FIGS. 4 to 7 as follows.

Since the control fleet 410 is located at the front of the packet 400, the packet receiver 252 detects the control fleet 410 at the output port 251 of the interconnection network 300 (step S111).

When the control fleet 410 is received in step S111, parity check is performed. If there is no error, the control fleet 410 is stored.

Since the number of dataplets 420 of the packet 400 is variable, the control fleet 410 is received in order to count the number of dataplets 420 and initialized to N = 0 (S112).

In step S113, it is checked whether the value of N has the same value as the packet length 413, if the value is the same, the present packet reception process is terminated, and when N has a value smaller than the packet length 413, the control fleet ( 410, and then waits for the dataple 420 (step S114).

When the data fleet 420 is received, parity check is performed on a fleet basis, and if there is no error, the data fleet 420 is stored in the packet buffer and the value of N is increased by 1 each time the data fleet is received (step S115), and the process returns to step S113.

That is, steps S114 and S115 are repeatedly performed until the shade of N has the same value as the packet length 413.

Meanwhile, the message receiver 257 restores the packet received by the packet receiver 252 into a message, and stores the packet in an appropriate buffer.

The message reception process will be described below with reference to FIGS. 4 through 6 and 8.

The packet receiver 252 receives the packet (step S211), and checks whether the packet type 411 is a data control packet (step S212).

Here, the data control packet constitutes a message together with one or more data packets, and the data control packet subsequently stores information about data packets to be received by the packet receiver 252.

The data packets are transmitted to the local memory 270 by the PCI bus controller 260, and the memory address used is transmitted to the message receiver 257 by the data control packet.

When the data control packet is received in step S212, the packet is stored in the message buffer, and the message storage address and the transmitting node number 414 are stored in an internal register (step S213).

Here, the message storage address is a start address of a message in which data packets constituting the message are stored.

After that, when the data packet is received (step S214), the message receiver 257 operates as follows.

First, the transmission node number stored in step S213 and the transmission node number 414 of the data packet are compared with each other (step S215).

If the comparison result is the same, the storage address of the data packet is calculated by the following formula (step S216).

Data packet address = (message storage address + packet serial number + packet length) In the above formula, the packet serial number 412 represents the order of packets constituting the message.

After calculating the address in step S216, the packet is stored in the data message buffer (step S217).

Packets stored in the data message buffer are transmitted to the PCI local bus 240 by the PCI bus controller 260 and finally stored in the local memory 270 of the designated address.

When the control packet is received in step S218, the control packet is stored in the message buffer and the message reception is finished (step S219).

The PCI bus controller 260 receives a message buffer access request from the processors 210A to 210N on the PCI bus 240 to access the buffer or to store packets stored in the data message buffer at a designated address of the local memory 270. Save function.

The operation of the PCI bus controller 260 will be described with reference to FIGS. 4 through 6 and 9.

When a request from the processors 210A to 210N occurs on the PCI bus 240, the PCI bus controller 260 starts operation (step S311).

Thereafter, if a PCI access request occurs and the data of the message buffer is desired, the data of the message buffer is read and supplied (step S312).

On the other hand, if there is no PCI access request, it is checked whether the data message buffer is empty (step S313).

If the data message buffer is not empty in step S313, the stored data is read in packet units to transmit the PCI local bus (step S314).

The difference between the message receiving interface circuit and the conventional receiving tag self routing method for the interconnection network of the packet transmission protocol according to the present invention as described above are as follows.

First, the switches of the network are connected in the form of a N-ary tree, and the closer the receiving side and the transmitting side, the shorter the path.

Second, it is used to connect some ports of the switch with the upper switches for the hierarchical structure of the network.

Third, a look-up table or complex control logic is required to directly use an address as a receive tag in such a switch and connection network, and the structure of the switch becomes very complicated or difficult to implement. To solve this problem, change the receiving address to tag and use this to perform the path control function of the switch. Thus, a simple structure can be maintained without adding a table or control logic to the hierarchical network and the switch.

In addition, since the process of converting a receiving address into a tag uses a simple algorithm, performance is comparable to that of using a receiving address as a tag.

The present invention is not limited to the above embodiments, and it is apparent that modifications are possible by one of ordinary skill in the art within the technical idea to which the present invention pertains.

Claims (1)

A packet receiver connected in an interconnection network for receiving packet data; A message receiver for recovering a message from the received packet unit data; DP-SRAM that provides memory space to use different buffers according to packet type, and provides dual access port to overlap packet receiving operation and access of buffer contents through PCI local bus in the interconnection network. ; And a PCI bus controller that reads contents of buffers located in different areas of the DP-SRAM in packet units and sends them to the PCI local bus, or responds to a buffer access request generated in the PCI local bus. Receiving interface circuit.