KR0150039B1 - Atm network interfacing apparatus - Google Patents

Abstract

The present invention relates to a high performance ATM network access device which is mounted on a host bus for accessing an external device of a host and connects the host to a network using an ATM protocol. The present invention relates to a buffer and a host bus signal for communication with the host 100. A host connection means 403 for performing a conversion function to a connection device internal signal; A shared memory 404 connected to the host access means 403 to temporarily store a packet transmitted from an ATM network / host; Division and recombination control means (405) connected to the shared memory (404) to perform a function of dividing cells into networks and transmitting them to a network or recombining cells received from a network into packets; Physical layer means (406) connected to the division and recombination control means (405) and performing matching with the ATM network (102) according to the characteristics of the physical layer; A control processor interconnected with the host connection means 403, shared memory 404, partition and recombination control means 405, and physical layer means 406 to perform functions such as initialization, status monitoring, signaling, and management. 407 is provided.

Description

ATM Network Access Device

1 is a diagram illustrating a network connection point of a general ATM network access device.

2 is a diagram illustrating a conventional packet memory structure.

3 is a diagram illustrating a conventional bus master structure.

4 is a diagram illustrating an internal interface configuration of an ATM network access apparatus according to the present invention.

5 is an exemplary system block diagram of an ATM network access device according to the present invention.

6 is a hardware block diagram of an ATM network access apparatus according to the present invention.

Figure 7 is a block diagram of an embodiment of a control processor according to the present invention.

8 is a block diagram of an embodiment of a host interface unit according to the present invention.

9 is a block diagram of an embodiment of a control memory unit according to the present invention.

10 is a block diagram of an embodiment of a packet memory unit according to the present invention.

11 is a block diagram of an embodiment of a physical layer unit according to the present invention.

12 is a packet transmission interface procedure according to the present invention.

13 is a packet receiving interface procedure according to the present invention.

14A and 14B show a transmission / reception control message format according to the present invention.

15 is a block diagram illustrating an internal block configuration of a video RAM according to the present invention.

* Explanation of symbols for main parts of the drawings

100: host computer system 101: ATM network connection device

102: Broadband public communication network (B-NT, ATM LAN)

103, 521: User-network interface reference point of broadband public telecommunication network

104, 408: host interface 201, 301: host bus interface

202, 404: packet memory

203, 405, 516: Split and Recombine Controllers

204, 304, 611: physical layer controller 205, 305, 612: optical transceiver

302: Split and Recombine Controllers and DMACs

303: first-in, first-out memory 401: host processor

402: network connection 403: host connection

406, 518: physical layer unit 407: control processor unit

408: control processor interface 409: packet memory interface

410: network interface 411: physical layer interface

500: data transfer function block 501: system management function block

502: signal processing function block 503: management function block

504: host bus control function block 505: packet memory

506: ATM interface function block

507: inter-processor communication (IPC)

508, 603: Direct Memory Access Controller (DMAC)

509 initialization function

The present invention relates to a high performance ATM network access device installed in a host bus for connecting a host external device and connecting the host to a network using the Asynchronous Transfer Mode (ATM) protocol.

Recently, due to the improvement of the performance of the host and the communication network to which the host is connected, communication bottlenecks have been shifted from the communication network to the network connection device, and studies on the implementation of such a high performance network connection device have been actively conducted.

In addition, the application of the communication network requires a real-time processing capability of a plurality of media having different characteristics such as video, voice, and data information in a simple packet data transfer application, but with the existing public network (eg X.25, frame relay, etc.) Local networks (eg, Ethernet, Token Ring, FDDI (Fiber Distributed Data Interface), etc.) transmit data in packet units, which causes problems in real-time traffic processing due to packet delay when transmitting multiple media in real time. In order to solve the above problems, standardization of new protocols such as Asynchronous Transfer Mode (ATM), which transmits packets by dividing packets into small and constant information sizes, that is, by cell unit, is actively adopted in International Telecommunications Union-Telecommunications (ITU-T). It's going on. In addition, the bandwidth that the protocol can provide to a network user may provide a user bandwidth of 155-622 Mbits / sec higher than 10 Mbits / sec in the existing Ethernet and 125 Mbits / sec in the FDDI.

User bandwidth in Ethernet and FDDI decreases the real bandwidth available per host as the number of hosts connected to the network increases because a large number of users packetize the media, but in ATM networks the bandwidth can be used in real time. It is possible to provide high quality multimedia service that requires characteristics.

On the other hand, due to the increased traffic as the number of terminals increases rapidly, the existing high-speed networks are interconnected, and the terminals connected to the network become high speeds, and a giga-class bandwidth for image-centric applications is required in the terminals, such as high-performance computing and distributed processing. New network protocols are emerging to provide gigabit bandwidth for applications. Currently, protocols capable of providing gigabit bandwidth include Fiber Channel (FC), High Performance Parallel Interface (HIPPI), and FDDI Follow on LAN (FFOL).

In contrast to the rapid change of the host and the communication network as described above, the progress of the performance improvement of the forwarding protocol and the network access device in the host is relatively slow. In other words, the existing network accessor functionally processes the data transfer function and the network protocol processing function for high speed data transfer between the host and the ATM network, and structurally, depending on whether the packet memory is located in the network access device or the host. The packet memory structure of FIG. 2 and the busmaster structure of FIG.

Advantages and disadvantages of the structure shown in FIGS. 2 and 3 are as follows.

In FIG. 2, packet memory 202 is controlled by split and recombine controller 203 and accessed by host 100 and split and recombine controller 203. When the host 100 delivers the packet to the packet memory 202, the division and recombination controller 203 divides the packet into cell units and transmits the packet to the network. The flow control and cell multiplexing functions are performed by the division and recombination controller 203. Will perform. Upon receipt of data, the multiplexed and received cells are reassembled in independently allocated buffers according to the virtual path / channel identifiers, and the partition and reassembly controller 203 delivers the reassembled packets to the host 100. .

The number of virtual channels that can be supported simultaneously in the ATM network access device 101 is limited by the capacity of the packet memory 202. The above structure can be applied in a server application in which a lot of resources requiring the use of the host bus 104 or a bus latency is an important factor. In addition, since the interface for connecting to the host is relatively simple, it is easy to implement. However, the network access apparatus of FIG. 2 has a disadvantage in that the price increases due to a memory for storing packets.

In the bus master structure, as shown in FIG. 3, the main memory of the host 100 is divided between the host 100 and the host memory 100 and the direct memory access controller (DMAC) 302 is not shared with the packet memory. It is structure to use.

The host 100 generates an identifier for the packet for data transmission, initializes the DMAC 302 of the network access device, and manages the memory used by the DMAC. When transmitting data, the DMAC 302 of the network access apparatus obtains a bus use right, divides the packet, and transfers the packet to the transmission first-in, first-out memory 303 on a cell-by-cell basis. Since the packet is divided into 53 octets and transmitted to the ATM network, the capacity of the transmission first-in, first-out memory 303 does not matter. In case of data reception, the DMAC 302 reads a cell from the reception first-in-first-out memory 303, separates the cell head, and reassembles the packet in the main memory of the host 100. The reception first-in-first-out memory 303 should be large enough to ensure minimum delay time because ATM data is received multiplexed on a cell-by-cell basis. Since the network access device uses the main memory of the host 100 as the packet memory, the cost burden is small according to the price of the transmit / receive packet memory, and the use of the host processor 401 can be minimized through DMAC. . In addition, the number of virtual channels that can be set at the same time can be adjusted as necessary.

However, since the bus master structure degrades performance when cell loss occurs, the bus master structure is applicable only when the bus delay time is predictable, and the implementation is complicated.

Existing commercially available boards have a problem that the overall data transfer performance is degraded due to the burden of processing the transmit / receive cells in software to process the partitioning and recombination functions using a high performance microprocessor.

Accordingly, the present invention devised to solve the conventional problems as described above, as well as the function of connecting a host to an ATM network such as a broadband public network, a broadband network termination device, or an ATM LAN. The purpose of the present invention is to provide a high performance ATM network access device having a general-purpose structure that is independent of a high performance host and a network protocol that can be used as a future access point in a gigabit network.

In order to achieve the above object, the present invention provides an ATM network access device for connecting a host computer system to an ATM (Asynchronous Transfer Mode) network, comprising: a buffer function for communication with the host computer system, and a host bus signal to the ATM. Host connection means for performing a function of converting an internal signal of the network connection device; Transmission packet memory means connected to the host access means, and temporarily storing a packet transmitted from the ATM network; A reception packet memory means connected to said host connection means for temporarily storing a packet transmitted from said host computer system; Division control means for dividing the packet stored in the transmission packet memory means in units of cells and transmitting it to the ATM network side; Recombination control means for recombining the packets received from the ATM network side and applying them to the received packet memory means; Physical layer connection means connected to the division control means and the recombination control means, and performing the ATM network matching function according to the characteristics of the physical layer; It is connected to the host connecting means, the transmitting packet memory means, the receiving packet memory means, and the physical layer connecting means, and receives a DMA (Direct Memory Access) transfer request from the host connecting means, and receives from the host computer system side. DMA control means for transferring a transmission packet of the received packet to the transmission packet memory means, or a received packet stored in the received packet memory means to a reception packet buffer of the host computer; And means connected to the host access means, the transmit and receive packet memory means, the split and recombine control means, the physical layer access means, and the DMA control means to control overall operations. do.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 15.

4 is an exemplary internal interface configuration of an ATM network access apparatus according to the present invention, and is designed to have a structure having five interfaces between functional blocks and functional blocks.

The five interfaces in ATM network accessor 101 are a bus for connecting to external peripherals at host 100, or a host interface 408 for interfacing with a channel, a network for connecting and a network for interfacing with physical media. For interface with the packet memory interface 409 and the control processor 407 for temporary storage of transmit / receive packets between the interface 410 and the physical layer interface 411 and between the network and the host interfaces 410 and 408. Has a control processor interface 412.

The interface is a characteristic of the network connection device, the part depending on the network to be connected is a part of the whole function, the remaining part can be used without change even if the connected network is different. In other words, even though different protocols such as Asynchronous Transfer Mode (ATM), Fiber Distributed Data Interface (FDDI), and Fiber Channel (FC) that provide 100-200Mbps bandwidth, host access and data processing functions are independent of network protocols. Therefore, the same structure can be implemented.

On the contrary, when various hosts are connected to the same network, only the part related to the host interface of the whole function is different, and since the remaining parts can be implemented in the same structure, the structure of the network access device according to the host 100 and the network protocol Changes can be minimized.

In the present invention, the partitioning and reassembly controllers 608 and 609 and the physical layer controllers are not processed by the general purpose processor. 611) to improve the cell processing performance by processing with dedicated hardware. In the structure of the network access device according to the location of the packet memory, the bus master structure is sensitive to the response time characteristic of the host bus 104, and as the network matching speed increases, the burden on the host bus 104 increases, resulting in poor performance. Since the packet memory structure transmitted through the host bus on a packet basis is easier to evolve into a high-speed network than the bus master structure transmitted to the host bus 104 on a cell basis, the packet memory structure is designed.

In addition, in order to minimize the burden of processing the upper protocol of the ATM of the host 100, a high-speed control processor is built in, so that the ATM network access device 101 processes the signals and management functions for the ATM network access to increase the processing performance of the entire protocol. . That is, the host 100 performs only an application function unique to the host 100, and the processing of the ATM protocol for accessing the ATM network 102 is performed by the ATM network access device 101 separately from the host 100. The burden on the host 100 for accessing the network 102 may be minimized. The control processor 701 has the advantage that it can be applied to the same structure when developing a network connection device in a high-speed network because the higher the network matching speed reduces the processing burden of the protocol of the host 100 is increased.

A detailed description of the interfaces follows.

First, the host interface 408 is a connection method between the host 100 and the ATM network connection device 101-a parallel bus (for example, VME Bus, EISA Bus, PCI Bus, Micro Channel, Turbo Channel, etc.), channel (SCSI). , HIPPI, etc.) adjacent to the host connection 403 including the bus signal conversion logic block 804 and transmit / receive control message buffers 600 and 601 for inter-processor communication in the ATM network access device 101. It is an interface between the packet memory 404 and the control processor unit 407. Since only the host connection unit 403 in the ATM network connection device 101 depends on the host 100, the host interface 408 is distinguished from the other functions that perform the network connection function in the host interface 408.

The packet memory interface 409 is an interface between the packet memory 404 and the host connection unit 403 and the control processor unit 407. The packet memory 404 has a function of temporarily storing a transmission packet for dividing a transmission packet transmitted from the host connection unit 403 or temporarily storing a reception packet for recombining a packet received from the ATM network 102. Separate areas for transmit / receive packets. The packet memory 404 is accessible by the host 100, the control processor 701 and the split and recombine controller 405.

The network interface 410 is an interface between the segmentation and recombination controller 405 and the adjacent packet memory 404 and the control processor 407. The segmentation and recombination controller 405 performs the ATM layer and ATM adaptation layer functions among ATM protocols under the control of the control processor 701, and divides the transmission packet stored in the packet memory 404 to transmit and receive a cell unit. Reassembles the cell into packets.

The physical layer interface 411 is the same interface as the Universal Test and Operations PHY Interface for ATM (UTOPIA) interface standardized in the US ATM Forum, and is an interface between the partition and recombination controller 405 and the physical layer unit 406. . The interface defines a standard interface between the ATM layer and the physical layer in the ATM protocol, and enables various physical media to be connected to the same ATM network access device 101. That is, the ATM network access device 101 may connect various physical media such as a single mode optical cable, a multi mode optical cable, a coaxial line, a shielded twisted pair cable, and the like in the physical layer interface 411.

The control processor interface 412 is an interface with the host connection 403, the packet memory 404, the segmentation and recombination controller 405, and the physical layer unit 406 adjacent to the control processor unit 407. The control processor 407 is a volatile memory SRAM 707 for storing a program for performing functions such as interprocessor communication with the host 100, a higher protocol, a signal, management, maintenance, and the like for storing a debugger and an operating system. A volatile memory 708, a serial communication controller, a timer 709, and the like.

5 is a block diagram of an embodiment of an ATM network access device 101 according to the present invention.

ATM network access unit 101 is implemented in the hardware 520, the partition and recombination layer function, ATM layer function, physical layer function of the ATM communication protocol in order to process a small and constant size cells at high speed in real time, the signal, management, Functions such as maintenance and communication between the host processor 401 and the on-board processor 407 of the network connection are performed by the software 519 using the on-board control processor.

The software subsystem 519 consists of data delivery 500, system management 501, signals 502, and management 503 blocks. The hardware subsystem 520 is comprised of a host bus control 504, a packet memory 505, and an ATM interface 506 block.

The system management function block 501 of the software unit system 519 is an initialization management 509 for initializing resources in the device upon initial power supply of the ATM network access device 101, process management, memory management, and failure and status. It consists of a maintenance 510 function, such as a monitoring function for monitoring. The management function block 503 is composed of layer management 514 for smoothly executing the ATM protocol, plane management 513, and TICK timer management 515 for driving a software timer. The signal management block 502 performs a procedure and a function for setting a virtual channel and a virtual path for data transmission, and the Q.2931 signal processing function 511 and Signaling ATM Adaptation Layer recommended by ITU-T. 512 signal ATM matching layer function. The data transfer function block 500 is transmitted through an IPC (Inter-Processor Communication) function and IPC for inter-processor communication between the host processor 401 and the control processor 701 of the ATM network access device 101. It consists of a Direct Memory Access Controller (DMAC) for delivering packets at high speed according to control commands.

The host bus control function block 504 of the hardware unit system 520 is connected to the host bus 104 so that a host processor (via a bus signal protocol conversion function for processing a host bus signal and a control message buffer 600 or 601) may be used. 401 and the control processor 701 of the ATM network access unit 101 performs a communication function. The packet memory function block 505 has a function of temporarily storing a transmission packet transmitted from the host connection unit 403 for divided transmission or temporarily storing the packet received from the ATM network 102 for recombination. Separated into areas for received packets.

The ATM interface function block 506 includes a function 516 for cell division and recombination, an ATM layer function 517, and a physical layer 518 for physical layer connection with the ATM network 102.

FIG. 6 is a hardware structure diagram of an embodiment of an ATM network access apparatus of the present invention, including a control processor 604, a host bus controller 602, a DMAC 603, a transmit / receive control message buffer 600, 601, and a transmit signal. / Receive control memories 607, 610, transmit / receive packet memories 605, 606, split controller 608, recombination controller 609, physical layer controller 611, and optical transceiver 612.

The host processor 401 stores the related control information in the transmission control message buffer 600 when a packet or a control message to be delivered to the ATM network access device 101 is prepared in the transmission buffer defined in the main memory of the host 100. The control message is composed of an address 4 octets, a message length 3 octets, and a control command 1 octet as shown in FIG. 14, and is transmitted using two 32-bit transmission control message buffers 600. When the host 100 writes the last control message byte to the transmission control message buffer 600, an interrupt of the transmission control message buffer 600 is required of the control processor 701 of the ATM network access device 101. When the control processor 701 receives the interrupt, the control processor 701 identifies the resource that requested the interrupt through the interrupt response. If the transmission control message buffer 600 is interrupted, the control information stored in the transmission control message buffer 600 is read to perform a function according to the control information. When the packet transmission command is received, the source address, the destination address, and the source address of the DMAC 603 are transferred from the host packet buffer to the transmission packet buffer defined in the transmission packet memory 605 of the ATM network access device 101. Set the forwarding packet length and forwarding mode.

Here, as a preferred embodiment of the DMAC 603, the built in Intel i960CA control processor 701 is used. When the initialized DMAC 603 receives the DMA transfer request signal from the host bus controller 602, it requests the bus processor the right to use the bus. Upon receiving the bus permission, the DMAC 603 transfers the transmission packet from the transmission packet buffer of the host 100 to the transmission packet buffer of the host connection device 101 according to the initialized contents. The DMAC 603 generates an interrupt for reporting the packet forwarding status to the control processor 701 when the packet is terminated or the packet forwarding is interrupted due to an error. When the control processor 701 receives a report from the DMAC 603 that the packet delivery is completed, the control processor 701 changes the indicator for the packet to be transmitted to the network in the packet preparation queue in the transmission control memory 607.

The segmentation controller 608 reads the indicator number from this queue if the packet ready queue is not empty (that is, if the packet to be sent is stored in the queue), links the indicator to the appropriate rate queue for packet segmentation, Multiplexing transfers the cell to the physical layer controller 611. After the transmission is finished, the division controller 608 stores the indicator number in the transmission completion queue. When the indicator number is filled while the transmission completion queue is empty, an interrupt is requested to the control processor 701 to inform the transmission completion.

When the recombination controller 609 receives the cell from the physical layer controller 611, it checks whether the virtual path / virtual channel identifier or the virtual channel / multiplexing identifier of the cell head is valid, and reads the recombination pointer from the related table if valid. The received cell is recombined in the received packet memory 606 using the recombination pointer. After the recombination is finished, the recombination controller 609 stores the indicator number of the received packet in the reception packet completion queue defined in the reception control memory 610. If the indicator number is filled when the received packet completion queue is empty, an interrupt request is sent to the control processor 701 to inform that the packet has been received. The control processor 701 initializes the DMAC for delivering the received packet to the host 100 after receiving the report from the recombination controller 609 through the interrupt, and then stores the host 100 in the reception control message buffer 601. ), Enter control information for packet forwarding. When the host 100 designates an operation mode of the host bus controller 602 as the burst transfer mode, a DMA transfer request signal is generated from the host bus controller 602 to the DMAC 603. Upon receiving the transfer request, the DMAC 603 requests the bus license from the control processor 701 and, upon receiving the permission, transfers the received packet from the received packet buffer of the ATM network access device 101 to the received packet buffer of the host according to the contents initialized. To pass.

A detailed block diagram of an embodiment of the control processor unit 604 of the present invention is shown in FIG.

In the present invention, it is designed using an i960CA processor of Intel Corporation, a high-performance embedded reduced-instruction computer, and performs functions that are difficult to implement in hardware in the ATM network access device 101.

The control processor 604 may include a control processor 701 for executing its own program, a decoder 704 in which logic for connection between the control processor 701 and a memory and a peripheral device is implemented, an execution program, data, and the like. SRAM 707 for storage of data, EPROM 708, memory that does not erase data even when power supply is interrupted for operating system and debugger storage, and serial interface for downloading compiled executables from an external monitor or development host And a serial communication controller and timer 709 for providing a TICK timer for driving a software timer, an Ethernet connection 710 for Ethernet communication with a development host, and an ATM connection 711 for processing and connecting an ATM network protocol. Host bus controller 712 for interfacing with host bus 104, control processor and ATM connection 711, and host bus controller 712. A clock oscillator for generating a clock signal to the bidirectional data driver 702, the unidirectional address driver 703, and the control processor 701 for fanout of the address and data buses. 700 and watchdog and reset timer 706 that provide reset, soft reset, and watchdog timer functions upon initial power up.

The control processor 701 is an initialization function of the ATM network connection device 101, a function of handling interrupts from the decomposition / recombination controllers 608 and 609 and the physical layer controller 611 performing the ATM protocol, the signal and management protocol, Perform functions such as maintenance. The control processor 701 also forwards the control message to the host 100 through the control message buffers 600 and 601 or interprets the received control message and executes the requested control command. If the control message is a message for packet delivery, the DMAC 603 embedded in the control processor 604 instructs packet delivery. The control processor 407 may be separated from other functions by the control processor interface 413, and the control processor 407 may perform a function performed by the control processor when the user does not require the control processor 407 according to user requirements. It can be done on the host side and can be left out.

An embodiment block diagram of the host connection unit 403 of the present invention is shown in FIG. 8, and the bus signal conversion logic 804 and the host 101 converting the host bus 104 signal into an internal bus signal of the host connection device. And a transmit / receive control message buffer 600,601 for transmitting a control message between the ATM network access device 101 and a transmit / receive first-in first-out memory 801,802 for delivering a packet for fast packet delivery.

The transmit / receive first-in, first-out memory (801, 802) is used for the purpose of preventing the performance degradation due to the difference in the packet transfer performance of the host 101 and the transfer performance of the ATM network connection device 101. The host bus controller 602 is connected to the EPROM 805, which is a nonvolatile memory, for storing information necessary to designate an operation mode at initial power-up, and initially initializes data from the EPROM to the host bus controller 804 only at initialization. Is passed.

The control message exchange between the host processor 401 and the control processor 701 of the ATM network connection device 101 is transmitted through the transmit / receive control message buffers 600 and 601. When the host processor 401 writes a control message for performing an operation in the transmission control message buffer 600, an interrupt is generated to the control processor 701 of the ATM network access device 101. Also. When the ATM network access device 101 writes a control message for performing a necessary operation in the reception message buffer 601, an interrupt occurs to the host processor 401. The transmit / receive message buffers 600 and 601 each consist of four mailboxes of 32 bits in length. The packet transfer between the host 100 and the ATM network access device 101 is performed at high speed by using a burst cycle that outputs address information only in a first bus cycle and only data in a subsequent bus cycle.

The DMAC 603 performs a packet transfer function between the first-in, first-out memory 801 of the host bus controller 602 and the transmit / receive packet memory 605, 606 of the ATM network access device 101 with a transfer performance of up to 59 Mbytes / sec. . The DMAC 603 is embedded in the control processor 701 and packets the control processor 701 and an external control, address, and data bus. Packet delivery using the DMAC 603 may be performed by an external request or may be requested to transmit data by software, and may have a flexibility of informing the control processor 701 of the DMAC 603 execution status through an interrupt. have.

9 is a block diagram of an embodiment of a control memory 607, 610 of the present invention.

The transmit / receive control memory 607, 610 has a data structure for storing the information for software performing the ATM protocol and the split controller / recombination controller 608, 609 for split transmission of packets and recombination of packets, and split controller / recombination. It is also used for communication between the controllers 608, 609 and software entities.

The transmission control memory 607 consists of a buffer indicator table, a virtual channel table, a packet preparation queue, and a transmission completion queue. The buffer indicator table stores the parameters for packet segmentation and is used to indicate the location of the packet in the transmit packet memory 605. The virtual channel table stores information about each virtual connection, and a value corresponding to the virtual channel is stored by software when establishing a connection. The packet preparation queue is used to queue the indicators of packets for segmentation. The transmission completion queue is used by the division controller 608 and stores the indicator number of the divided packet.

The reception control memory 610 includes a buffer indicator table, a virtual channel table, a virtual path table, a recombination table, a small usable indicator queue, a large usable indicator queue, a packet completion queue, and an exception handling queue. The buffer indicator table stores information for packet recombination and indicates the location of the packet buffer for recombination in the received packet memory 606. The virtual channel / path table stores the value of the virtual channel / path being connected and recombined. The recombination table stores the status and indicator number of the packet currently recombining in the recombination table. The small / large available indicator queue is used as a queue of available indicators for packet recombination. The packet completion queue is used to store an indicator of recombined packets. The exception handling queue is used by the recombination controller 609 to inform the software entity of the failure. Since the transmit / receive control memories 607 and 610 are instructed or reported by the control processor 701, and the division controller / recombination controller 608 and 609 and the control processor 701 simultaneously request a license. Arbitration function of the ATM control logic 705 is performed.

The ATM control logic 705 uses the unidirectional bus drivers 902a and 902b and the bidirectional bus drivers 901a and 901b so that the control processor buses 903 and 904 and the control memory buses 905, 906, 911 and 912 do not collide. To generate a control signal.

10 is a block diagram of an embodiment of a packet memory unit of the present invention.

The transmit / receive packet memories 605, 606 are used to store packet data for packet segmentation / recombination. Packet memories 605 and 606 have a 32-bit data bus width and are separated into transmit and receive packet memories 605 and 606. The transmit / receive packet memories 605 and 606 have three data structures for packet division, recombination, and packet data, operation and maintenance (OAM) cell data, and equal bit rate data. In the present invention, a video RAM 1501, which is a commercial chip, is used as the packet memories 605 and 606.

The video RAM 1501 is physically divided into a random access memory 1502 and a sequential access memory 1503 and, unlike commercial chips such as dual-port RAM, which cannot access a single cell simultaneously, has two independent ports. Have. Since the two ports are independently accessible, there is an advantage to increase the packet forwarding performance. It also has the advantage of larger capacity and lower cost than SRAM. The video RAM 1501 is accessed by the control processor 701 and the division controller / recombination controllers 608 and 609, and connects the data bus 903 to the video RAM used as the packet memories 605 and 606. 1002 and 1003 are independent, respectively, but address buses 904, 1001 and 1004 are generated via ATM control logic 705 for license arbitration and address multiplexing.

Here, as the preferred embodiments of the split and recombination controllers 608 and 609, commercially available SARA-S and SARA-R manufactured by Transwitch, Inc. are used.

The division controller 608 divides and transmits the packet stored in the packet buffer defined in the packet memories 605 and 606 in units of cells. Packets segmented by segmentation controller 608 are stored in a packet buffer designated as an available buffer indicator designated by control processor 701. The packet segmentation procedure of the stored packet is started by registering the buffer indicator number in the packet preparation queue. The partition controller 608 reads the indicator number from the packet preparation queue and links it with one of eight transmission rate queues corresponding to each virtual channel. Upon linking, packet fragmentation is performed according to the parameters of the buffer indicator buffer and the virtual channel table. The segmentation controller 608 divides the packet into 44/48 byte ATM cell payloads, and the associated ATM header, checksum, and AAL header (for AAL 3/4) is added to each cell's header and forwarded. For payloads containing the last part of the packet, an AAL trailer (for AAL 3/4) is filled at the end of the cell and delivered to the cell interface.

The recombination controller 609 receives the cell from the cell interface and recombines the packet buffer defined in the received packet memory 606. Upon receiving the first cell of the packet, either the large available indicator queue or the small available indicator queue is used to select a buffer indicator number for storing the recombination packet. The entry in the reassociation table is changed to associate the indicator number for the subsequent cell received from the virtual channel. ATM header checksum and AAL information is removed before being stored in the cell buffer. Subsequent cells are stored in the appropriate packet buffer until the cell containing the end of the packet is received. At the end of the packet reassembly, the indicator status information is changed and the software is notified by registering the indicator on the packet completion queue.

11 is a block diagram of a temporary example of the physical layer unit 406.

The physical layer controller 611 performs a SDH (Synhronous Disital Hierarchy) basic transmission function and a physical medium matching function of a sub-million layer of subscriber access of a user-network interface of a broadband public communication network. A signal having an SDH signal format is interfaced in 8 bits in parallel to perform STM-1 frame synchronization and descrambling, and then a section overhead (SOH) is extracted. Performance / alarm information on the SOH is processed in hardware in real time to be connected to the control processor 701, and other operational management channels are directly serially connected to enable communication with the outside. After STM-1 (Synchronous Transport Module-1) signal termination, AU-4 pointer analysis and VC4 path overhead processing are performed. At this time, performance check and alarm monitoring related to VC4 signal path are performed at the same time. In addition, we extract the valid cells through the alignment of ATM cells in the VC4 payload, the error checking of the header part, and the 1-bit error correction process, and interface them to the outside in an asynchronous manner through the internal first-in first-out memory. At this time, all of the receiving cells may be delivered or idle cells or unallocated cells may be removed and transmitted.

Since the physical layer controller 611 interfaces 8-bit in parallel with a signal having an SDH signal format, the 8-bit parallel data is converted into 1-bit serial data during transmission in order to match with the optical transceiver 612 interfaced with a 1-bit serial signal. There is serial / parallel conversion logic 1103, 1104 for the function of converting 1-bit serial data to 8-bit parallel data upon receipt.

The receive conversion logic 1104 has a function of extracting a clock signal from the serial data string received by the optical transceiver 612. In addition, the parallel / serial conversion logic 1103 is connected to the serial / parallel conversion and timing recovery logic 1104 to connect the serial bit string output from the parallel / serial conversion logic 1103 for testing purposes. The local loopback function inputs to the serial / parallel conversion logic 1104 through the local loopback pass 1106 and the bit string received from the network device that is point-to-point connected to the ATM network connection device 101 without outputting the same. A line loopback function is provided to the serial / parallel conversion logic 1104 through the line loopback path 1105 without returning to the hierarchical controller 611 to return to the ATM network 102.

The optical transceiver 612 receives an electrical serial signal from the physical layer controller 611 and converts it into an optical signal, or converts an optical signal received from an ATM network into an electrical serial signal and transmits it to the physical layer controller 611. Do this.

12 shows a transmission control message and a packet forwarding procedure between the host processor 401 and the control processor 701 of the ATM network access device 101 of the present invention.

When the host processor 401 receives a packet transmission request from an upper application, the host processor 401 transmits a control command 1 octet, message length 3 octets, and address as shown in FIG. 14A for packet transmission to the internal transmission control message buffer 600 of the host bus controller 602. Store 4 octets. Since the interrupt is generated when the control processor 701 of the ATM network access device 101 reads the control message, the host processor 401 instructs burst delivery and waits for the delivery completion of the delivered packet. Upon receipt of the delivery completion, it notifies the higher level application that the packet transmission was successful.

When the control processor 701 finds that a control message exists in the transmission control message buffer 600 by an interrupt, the control processor 701 reads the control message and performs the requested operation. If the message is for packet transmission, the control processor 701 initializes the DMA. Let's do it. The DMAC 603 receiving a DMA request from the host bus controller 602 reads a packet from the first-in-first-out memory 801 of the host bus controller 602 and delivers the packet to the internal packet buffer of the packet memory 605. Upon completion of packet forwarding, the DMAC 603 informs the control processor 701 with an interrupt.

Upon receiving the interrupt that the packet is delivered, the control processor 701 informs the host processor 401 that the packet has been successfully read in the reception control message buffer 601. When the control processor 701 indicates that the packet is prepared in the internal packet preparation queue of the transmission control memory 607, the division controller 608 divides the packet and transmits the packet to the ATM network 102 through the physical medium controller 611. .

13 shows a reception control message and a packet forwarding procedure between the host processor 401 and the control processor 701 of the ATM network access device 101 of the present invention.

The host processor 401 secures an area for receiving a packet, informs the buffer pointer of the received packet through the transmission control message buffer 600, and then receives a response from the control processor 701 of the ATM network access device 101. waiting. When the response is received, the upper application is notified that the buffer allocation procedure is completed. Informing the host bus controller 602 of the burst transfer when it informs via an interrupt that the packet is ready from the host bus controller 602. The host bus controller 602 informs the host processor 401 that the packet burst delivery is complete when the indicated packet burst delivery is completed. The host processor 401 which has received the burst transfer completion interrupt informs the control processor 701 of the ATM network connection device 101 that the reception has been completed through the transmission control message buffer 600. The host processor 401 then transmits to the host application. Deliver the received packet.

The control processor 701 of the ATM network access device 101 notifies the reception control message buffer 601 of the start of a reception packet forwarding procedure when the recombination controller 609 informs that the packet recombination is completed. An interrupt occurs when the control message is read from the host processor 401, so the interrupt service routine instructs the DMAC 603 to forward the received packet DMA. When the control processor 701 informs that the received packet delivery is completed from the DMAC 603, the control processor 701 waits for a message indicating that the packet has been successfully received from the host processor 401. If the packet reception is notified through the transmission control message buffer 600, the packet reception procedure is completed.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The present invention, which is configured and operated as described above, solves the problems of the existing network access device, and in addition to a function of connecting a host to an ATM network such as a broadband public communication network, a broadband network termination device, or an ATM LAN, in a later gigabit network. It can be used as a network connection device.

Claims (10)

An ATM network access device for connecting a host computer system to an ATM (Asynchronous Transfer Mode) network, comprising: a buffer function for communicating with the host computer system, and a function of converting a host bus signal into an internal signal of the ATM network access device. Host connection means for performing; Transmission packet memory means connected to the host access means, and temporarily storing a packet transmitted from the ATM network; A reception packet memory means connected to said host connection means for temporarily storing a packet transmitted from said host computer system; Division control means for dividing the packet stored in the transmission packet memory means in units of cells and transmitting it to the ATM network side; Recombination control means for recombining the cells received from the ATM network side into packets and applying them to the received packet memory means; Physical layer connection means connected to the division control means and the recombination control means, and performing the ATM network matching function according to the characteristics of the physical layer; It is connected to the host connecting means, the transmitting packet memory means, the receiving packet memory means, and the physical layer connecting means, and receives a DMA (Direct Memory Access) transfer request from the host connecting means, and receives from the host computer system side. DMA control means for forwarding the transmission packet of the transmission packet to the transmission packet memory means or the reception packet stored in the reception packet memory means to the reception packet buffer of the host computer; And means connected to said host access means, said transmit and receive packet memory means, said split and recombination control means, said physical layer access means, and said DMA control means to control overall operations. The ATM network connection device of claim 1, further comprising an optical transceiver connected between the physical layer connection means and the ATM network. The system of claim 1 or 2, wherein the means for controlling the overall operation comprises: a high performance control processor; A clock generator connected to the control processor to supply a clock signal; A bidirectional data driver connected to a data bus of the control processor to increase bus driving power; A unidirectional address driver connected to an address bus of the control processor to increase bus driving force; A decoder and an ATM control logic coupled to a control bus of the control processor to generate various control signals; An SRAM, an EPROM, a serial communication controller and a timer, and an Ethernet connection unit connected to the bidirectional data driver, the address driver, and the decoder to support program execution of a processor; An ATM connection unit connected to the bidirectional data driver, the address driver, and the ATM control logic to support protocol and physical medium matching for ATM network access; An EPROM coupled to the decoder and storing a network address; And a watchdog and a reset timer connected to the decoder and the ATM control logic to monitor operation of the high performance control processor and generate a reset signal for initialization. 4. The apparatus of claim 3, wherein the host connection means comprises: a bus signal conversion logic connected to a host bus for connecting an external device of the host computer system to convert the host bus signal into an internal bus signal; A transmit / receive first-in first-out memory and a transmit / receive control message buffer, coupled to the host bus, for transmitting control messages and packets with the host computer system; An internal bus of an ATM network connection device interconnecting the bus signal conversion logic, the transmit / receive first-in first-out memory and the transmit / receive control message buffer; And an EPROM for setting a mode of the host connection means upon initial power supply. 4. The ATM network access device according to claim 3, wherein the division control means and the recombination control means each have independent control memory means and packet memory means for enhancing cell processing performance. 6. The ATM network access device according to claim 5, wherein the division control means and the recombination control means are configured to have a direct communication channel with each other in order to retransmit the received congestion related cells. 4. The apparatus of claim 3, wherein the division control means comprises: a division controller which divides and transmits packets stored in the packet memory means in units of cells; A transmission control memory connected to the division controller through a transmission control memory data bus and a control memory address bus of the division controller and providing information for packet division and transmission buffer related information; And a signal connected to the partition controller, for arbitrating a request for access to the transmit control memory of the partition controller and a request for access to the transmit control memory from the high performance control processor and for controlling a bus driver to avoid collision with a control processor bus. And providing ATM control logic for outputting a transmission control memory control signal to the Xing transmission control memory. 4. The apparatus of claim 3, wherein the recombination control unit comprises: a recombination controller for recombining the cells received in units of cells into packets; A reception control memory connected to the recombination controller through a reception control memory data bus and a control memory address bus of the recombination controller, the reception control memory providing information for packet recombination and information related to the reception buffer; And a signal coupled to the recombination controller, for arbitrating a request for access of the receive control memory of the recombination controller and a request for access to the receive control memory from the high performance control processor and providing a signal to control a bus driver to prevent collision with a control processor bus. And an ATM control logic for outputting a reception control memory control signal to the reception control memory. The data transmission method of claim 3, wherein the transmission packet memory means and the reception packet memory means have a video RAM having two ports, each of which is independently accessible random access memory and sequential access memory. A bus is connected to a random access memory, a packet memory data bus of the partition controller and a recombination controller is connected to the sequential access memory, a packet memory address bus and a processor address bus of the partition controller and the recombination controller, and the transmission is performed. ATM control logic for generating a packet memory means and an address bus and a control bus of said received packet memory means. 10. The apparatus of claim 9, wherein the physical layer connection means comprises: a parallel / serial conversion logic connected to a transmit parallel byte bus of a physical layer controller and converting the parallel byte stream into a serial bit stream; Serial / parallel conversion logic coupled to the optical transceiver, for extracting a clock signal from the received serial bit stream and generating a parallel byte stream synchronized with the clock signal; The physical layer controller performing a function of carrying a cell in a predetermined frame for transmitting a physical layer connection to the ATM network or extracting a cell carried in the frame; A first-in, first-out memory connected to the physical layer controller and used as a temporary buffer for matching cell processing speeds of a recombination controller; And a control logic connected to the division and recombination controller and the physical layer controller and generating a signal for controlling a signal matching function for cell transfer and a first-in, first-out memory.