KR0147431B1 - Clipping and rounding arithmetic unit - Google Patents

Abstract

The present invention relates to a variable rounding point unsigned clipping / rounding operator. When the rounding point of input data that the existing structures cannot efficiently support is variable, the clipping / rounding operation can be easily implemented in hardware and high speed operation can be performed. It is composed of possible structure, it can support rounding point at every bit position of input data, and can output the desired valid data at all bit positions within input data. Smaller and faster computing device than conventional ones using only the rounding control unit of conditional 1 adder by separating the effective data unit and the rounding condition data unit around the rounding point from the input data without using barrel shifter control unit in the structure Configure Can.

Description

Clipping / Round Computing Unit

1 is a schematic structure of a clipping / rounding operator according to the present invention.

2 is an exemplary data diagram of a calculation block.

3 is a structure diagram of a 4-bit input conditional adder.

* Explanation of symbols for main parts of the drawings

1: Clipping Controller 2: Barrel Shifter

3 conditional 1 adder 4 rounding controller

TECHNICAL FIELD The present invention relates to a computing device, and more particularly, to a clipping / rounding computing device for clipping and rounding operations on unsigned data having a variable rounding point.

Conventional clipping / rounding operators are used for clipping / inputting input data based on a rounding point determined using a ROM (Read Only Memory), a programmable logic array (PLA), or an adder. Perform rounding operation. When performing rounding using such a ROM or PLA, the data for the clipping / rounding operation includes clipping / rounding including the number of valid data bits and the number of rounding bits below a rounding point to obtain valid data. It is entered into the rounding operator. Therefore, when the effective data bit number and the rounding condition bit number are extended, a very large ROM or PLA is required, and when the rounding point or the rounding condition is changed, the ROM or PLA has to be redesigned. In addition, an operation method of performing rounding by adding a predetermined value to a specific bit below a rounding point using an adder requires an adder that performs an operation for the number of bits inputted to obtain valid data. However, the rounding operation is an operation that simply adds 1 to the valid data part or passes it as it is, and there is a problem that it is difficult to efficiently adapt to the variable rounding point, which is inefficient in terms of calculation speed and design area.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems with the prior art. The present invention provides an efficient clipping / rounding operation apparatus capable of small area and high-speed processing for clipping / rounding of unsigned data having a variable rounding point. There is a purpose.

In order to achieve the above object, the present invention provides a computing device for clipping and rounding unsigned data having a variable rounding point, comprising: clipping control means for decoding the variable rounding point and outputting it as a shift control value; Shifting means for shifting input data in response to the shift control value to select and output valid data having an arbitrary number of bits and rounding condition data having an arbitrary number of bits; Rounding control means for outputting an addition control signal in response to the rounding condition data; And rounding addition means for outputting output data in response to the valid data and the addition control signal.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of a variable rounding point unsigned data clipping / rounding operator according to the present invention, in which 1 is a clipping controller, 2 is a barrel shifter, 3 is a conditional 1 adder and 4 is a rounding controller. Represent each.

As shown in the figure, the present invention provides a clipping controller 1 for decoding a variable rounding point for a bit to be rounded and outputting a shift control value of z bits, and input data (x, w) in response to the shift control value. , y) by shifting the barrel shifter 2 to perform the clipping operation by selecting valid data, and adding one to the valid data x 'in response to the rounding condition data y' outputted from the barrel shifter 2. 1 is added in response to the rounding controller 4 and the valid data x 'output from the barrel shifter 2 and the addition control signal for outputting an addition control signal for deciding whether or not to output the signal. It consists of a conditional one adder 3 which exports as data x '' or exports valid data x 'as output data x' 'as it is.

Here, each of the components constituting the input data will be described. First, w bits indicate the number of bits of data to be subjected to actual clipping and rounding operations. The x bit connected to the front of the w bit to be operated is the number of valid data bits. The most significant bit value of the w bit (the most significant bit is set in case the variable rounding point is located at the most significant bit of the data w bit to be operated on). 1 is filled with x by 1, and 0 is filled with 0 by x) and input to the barrel shifter 2 by the maximum number of valid data bits x. The y bits connected to the back of the w bits to be operated are the number of rounding bits. When the variable rounding point is located at the least significant bit of the data w bits to be operated, the maximum number of rounding bits (y 0 is added to the barrel shifter 2. Therefore, the barrel shifter 2 receives x + w + y and performs the shifting operation. x '' is the final output data of the clipping / rounding operator of the effective number of data bits (x).

FIG. 2 is an exemplary diagram of data in each step, and the operation of the present invention will be described in detail with reference to FIGS. 1 and 2.

First, the data to be rounded is 1101011101 (w is 10 bits), the number of valid data bits and the number of rounding bits is 4 bits (that is, x and y are 4 bits), and the variable rounding point is the least significant bit of the data to be rounded. Assume that we round at the fifth bit from. According to the assumption, the clipping controller 1 receives the variable rounding point and outputs a shift control value 101 to the barrel shifter 2 to decode and shift five times, and the barrel shifter 2 responds to the shift control value. The input data 111111010111010000 is shifted to the right to output valid data x'1010 and rounding condition data y'110 around the rounding point to the conditional 1 adder 3 and the rounding controller 4, respectively. .

Next, the rounding controller 4 performs a rounding algorithm arbitrarily determined by the user in response to the received rounding condition data y 'of 110 to pass 1 to the valid data obtained by the barrel shifter 2. An addition control signal for deciding whether or not to output is output to the conditional one adder 3. Here, the rounding algorithm is a truncation scheme for the fractional part below the rounding point, a round-to-nearest rounding to near number, a round-to-nearest-even rounding to near even number, and ROM rounding. Schemes and the like, such algorithms are well known as the prior art, and detailed description thereof is omitted here. Here, when a scheme of rounding to the nearest number is adopted as the rounding algorithm, an addition control signal having a logic level of 0 indicating no rounding, i.e. not adding 1 to valid data, is output to the conditional one adder 3.

3 is an adder structure diagram for a 4-bit input of a conditional 1 adder. The input bit is x '[0] of an input valid data x' and an adder control signal. Exclusive negative OR gate (5) output to 0], the remaining bits (x '[1], x' [2], x '[3]) of valid data, and three negatives each negatively ANDed with the addition control signal. Inputs the output signals of the AND gates 6 to 8, the remaining bits of valid data (x '[1], x' [2], x '[3]) and three negative AND gates (6 to 8). And three exclusive negative OR gates 9 to 11 each receiving the exclusive OR and outputting the output data (x '' [1], x '' [2], x '' [3]).

The valid data x 'of the input 1010 is not added according to the addition control signal, and the valid data 1010 is output as the final output data x' 'without change.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Accordingly, the present invention not only makes it possible to easily implement clipping / rounding operations in hardware even when the rounding point of the input data is variable, which existing structures cannot efficiently support, and provides a structure capable of high-speed computation. The rounding point may be supported at all bit positions of the input data, and the desired valid data may be selected and output at all bit positions within the input data. In the case where the rounding point of the input data is fixed, the effective data part and the rounding condition data part are separated from the input data around the rounding point in the input data without using the barrel shifter control part in the proposed structure, and the conditional one adder and the rounding are performed. By using only the control unit, the area is smaller than that of the existing computer, and there is an effect that a high-speed computer can be configured.

Claims (6)

A computing device for clipping and rounding unsigned data having a variable rounding point, comprising: clipping control means for decoding the variable rounding point and outputting it as a shift control value; Shifting means for shifting input data in response to the shift control value to select and output valid data having any number of bits and rounding condition data having any number of bits; Rounding control means for outputting an addition control signal in response to the rounding condition data; And rounding addition means for outputting output data in response to the valid data and the addition control signal. 2. The apparatus of claim 1, wherein the input data comprises first data of any number of bits of the valid data, second data for actual clipping and rounding operations, and third data of any number of bits of the rounding condition data. Clipping / rounding operation device characterized in that it comprises. The apparatus of claim 1, wherein the shifting means is a barrel shifter. 2. The first logical means of claim 1, wherein the rounding adding means outputs the least significant bit signal of the valid data as one input and the addition control signal as a type force and outputs the least significant bit signal of the output data after an exclusive OR operation. ; And as the one input of the valid data input signal preceding the sequence and the addition control signal as the type power, and the output value multiplied by the logical logic as each input, and the corresponding valid data input signal as the respective type power. And at least one second logic means for outputting said corresponding signal of said output data in an exclusive negative OR. The apparatus of claim 1, wherein the first data is filled with a value corresponding to a most significant bit of the second data. 3. The apparatus of claim 2, wherein the third data is filled with a value of zero.