KR0145077B1 - Method for forming a non-planar structure on the surface of a semiconductor substrate - Google Patents

Abstract

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Description

A method of forming a non-planar structure on a semiconductor substrate surface.

1 is a vertical cross-sectional view of a semiconductor substrate in which a nitride pattern is formed on the semiconductor substrate.

FIG. 2 is a vertical sectional view in which a trench is formed in a portion of the substrate where the substrate of FIG. 1 is not covered with a nitride capping layer. FIG.

3 is a vertical sectional view in which a uniform nitride layer is formed on the substrate of FIG.

4 is a vertical cross-sectional view after anisotropic etching to leave a nitride layer on the sidewalls of the trench in FIG.

FIG. 5A is a vertical sectional view in which field oxide is formed in the trench in FIG.

FIG. 5B is a detail of the trench sidewall of FIG. 5A.

FIG. 6 is a vertical sectional view in which a gate oxide layer and a polysilicon layer are formed on the structure of FIG. 5a.

7 is a perspective view of a transistor gate formed of a polysilicon layer.

8 is a vertical cross-sectional view of a complete transistor.

9 shows a modified embodiment showing a capacitor and a transistor formed by the method of the present invention.

* Explanation of symbols for main parts of the drawings

10: semiconductor substrate 12, 50, 60: silicon oxide layer

14, 20, 22: Night ride cap 24, 26: Trench

38, 40: field oxide layer 42, 42 ', 44, 44': birds beak

52: polysilicon layer 54, 76: gate

56,78: source 58, 80: drain

62: contact opening 64: plug

66: metal layer 70: capacitor region

72: active area 82: bit line contact

FIELD OF THE INVENTION The present invention relates generally to semiconductor structures, and more particularly to methods of forming nonplanar surfaces on semiconductor structures to increase surface area and fabricating MOS structures on these nonplanar surfaces.

Recent integrated circuits have made significant advances in process technology and photolithography technology, which have resulted in much more complex and highly integrated devices.

In order to realize such a high degree of directivity, current technology is providing submicron line formation to form various structures on integrated circuits.

However, the industrial need for high integration devices far exceeds the ability to be realized with current technology. This is partly due to the fact that conventional processes use planar technology with a two-dimensionally formed structure.

In order to increase the degree of integration with current process and photolithography techniques, process designers are turning to vertical integration techniques to more effectively use the available space. Some vertical integration techniques stack active devices on top of devices that are already being processed.

This stacking process requires the formation of a silicon layer on top of an already formed active device. At this time, a second level active circuit is formed in this second layer. This type of technology significantly increases the density, but besides the complexity of the process, problems arise in interconnection and contact hole formation between the different levels.

Another vertical integration technique that has been used successfully is to dig a trench, where trenches are formed in the substrate, where active circuits or capacitors are formed at the bottom and sides of the trench.

Trench technology is widely used in dynamic random access memory (DRAM) cells having an integration density of 1M bit or more.

The trench has a vertical wall trench or a V-type trench in VMOS technology.

Vertical integration technology increases the degree of integration, but current technology has its limitations.

Commonly used components in high-density circuits are MOS transistors and MOS capacitors.

In improving the operation of the capacitor, in order to increase the capacity, it is necessary to increase its surface area or to reduce the distance between nations.

In addition, in a non-inverting capacitor, the depletion capacitance can be increased by using an ion implanted region under the capacitor to provide a Hi-c capacitor.

However, because of the numerous operating parameters that are affected by this, the transistor needs some consideration. For example, a conventional MOS transistor has a width defined by the width of the source and train regions and a length defined by the channel length of the transistor.

The operating parameters of the transistor depend on this geometry.

During the fabrication of MOS transistors, a moat is formed in the substrate with a moat width corresponding to the transistor width. In this case, the gate oxide layer and the gate electrode are deposited on the substrate along the gate electrode width defined by the channel length, that is, the entire width of the transistor. In addition, source and drain regions are formed on both sides of the gate along the entire width of the transistor.

The size of the source and drain regions perpendicular to the gate is chosen to be large enough to make contact thereon. In a planar structure, more than two-dimensional space is required if a wider transistor is required. There are certain limitations to transistors with a finite size and are a function of width-length ratio. These are for example gain, speed and power processing capacities.

Because scale down degrades performance, there is a limit to scaling down the device. Therefore, vertically integrated process technology does not specifically specify transistors. Therefore, there is a need for a process technology that can increase the packing density for any given transistor without severely scaling down the device.

The present invention consists of a method of increasing the surface area of a semiconductor substrate.

The method includes a first step of forming a trench in the surface of a semiconductor substrate, the trench consisting of sidewalls and a bottom surface.

Sidewalls are formed around the active region. A sidewall protective layer is then formed on the trench and sidewall surfaces. And a layer of thermal oxide grows from the bottom up in the trench. During formation of the thermal oxidation layer, a bird's beak is formed which extends up between the sidewall and the sidewall protection layer, which merely extends over the sidewall. At this time, the sidewall layer of the sidewall portion that is not hidden is removed by the buzz bee which increases the surface area of the active region.

In another specific implementation of the present invention, the side walls are sloped upward from the top surface to the trench bottom to give a more arched edge for the active region.

The trench is formed by first depositing a protective capping layer on an oxidation resistant substrate and then patterning the protective capping layer to form a trench boundary. The trench is obtained by etching to a set distance in the substrate. The thickness of the capping layer can be varied so that the actual surface of the substrate at the trench boundary can be larger than the patterned surface area along the upper surface of the protective capping layer.

In another specific embodiment of the present invention, a transistor is formed over the active region by forming a gate oxide layer with a thickness set over the active region. The conductive layer is then formed over the gate oxide layer after patterning the bonding layer of gate oxide and conductive material to form a gate electrode. The gate electrode extends from one side of the active region to the other to form a channel region underlying it. Both ends of the gate electrode cross over the thermal oxide layer in the trench at least at one end of the gate electrode to increase the transistor width below the sidewalls and the transistor width. Source and drain regions are formed inside the channel.

In another specific embodiment of the present invention, a MOS capacitor is formed in the active region. MOS capacitors are made by forming a capacitor oxide layer on a substrate and an upper electrode thereon. A conductive connection is given to the active region in contact with the portion of the active region underlying the capacitor oxide layer to give the second electrode of the inverting capacitor.

DETAILED DESCRIPTION OF EMBODIMENTS The present invention will be described in detail with reference to the accompanying drawings for a thorough understanding of the invention.

In the preferred embodiment of FIG. 1, a vertical cross-sectional view of a substrate 10 made of silicon is shown. A silicon oxide layer 12 having a thickness of about 300 degrees is formed on the upper surface of the substrate 10. The silicon oxide layer 12 is formed on the substrate by thermal oxidation treatment in an oxidizing atmosphere at a temperature of about 1000 ° C. After formation of the silicon oxide layer 12, a layer of silicon nitride (Si ₃ N ₄ ) is deposited on the top surface of the oxide layer 12 by a proprietary CVD technique. The growth of Si ₃ N ₄ is carried out at a temperature of about 800 ° C.-900 ° C. for a set time.

A photoresist (PR) layer is then formed on the top surface of the Si ₃ N ₄ layer and then patterned to create a nitride cap 14 having two open regions 16 and 18 formed on both sides. Open regions 16 and 18 abut on both sides from ride cap 14 to nitride cap 20 and 22, respectively.

Referring to FIG. 2, after formation of the nitride caps 14, 20 and 22, the open regions 16 and 18 are etched with fluorine etching which is substantially anisotropic etching.

As a result, trenches 24 and 26 are formed on both sides of the nitride cap 14 in the open regions 16 and 18, respectively. The depths of trenches 24 and 26 are 2000 microseconds-5000 microns. Trench 24 has a beveled edge 28 adjacent to nitride cap 14, and trench 26 has a beveled edge 30 adjacent to nitride cap 14. Edges 28 and 30 may be substantially vertical, but inclined edges are preferred for fabricating transistors as described in the preferred embodiments.

In a preferred specific implementation, trenches 24 and 26 are formed with sloped edges 28 and 30 to have a sloped profile. This slope has an angle that is a function of the etching process. Etching is preferably plasma etched using LAM 580 equipment with 600watt.v through a flat plate approximately 0.5 cm apart.

The pressure is 0.5 Torr with a flow rate of C ₂ F ₆ gas at a flow rate of 50 cc / min along the CHF ₃ gas at a flow rate of 15 cc / min. The total etching time is about 2.5 minutes.

However, it can be seen that by varying the flow rate and power of the gas and the plane spacing, the angle can be changed.

3, after the formation of trenches 24 and 26, a uniform layer of silicon nitride 32 is deposited on the substrate by CVD techniques. Silicon nitride layer 32 is approximately 2500 mm thick. The substrate is then subjected to anisotropic etching (SiF ₆ ) to remove the portion of the layer 32 covering the planar surface as shown in FIG. This effectively removes the silicon nitride layer 32 from the top surface of the nitride cap 14 and the bottom of the trenches 24 and 26. Anisotropic etching also etches some of the top surface of the nitride cap 14. The nitride layer 34 of the sidewalls of silicon nitride remains on the beveled edge 30 and the nitride layer 36 of the sidewalls remains on the beveled edge 28.

In a preferred specific implementation, etching is performed using LAM 580 equipment having flat plates spaced 1.5 cm apart at 0.2 Torr pressure and 100w power. SiF ₆ gas has a flow rate of 50 cc / min along He gas at a flow rate of 10 cc / min. The etching time is about 2 minutes.

In FIG. 5A, after formation of the nitride layers 34 and 36 of the sidewalls, the substrate consumes silicon at the bottom to form SiO ₂ , and an oxide layer 38 at the bottom of the trench 26 and 24. It is subjected to a steam oxidation process at about 900-1000 ° C. to form 40.

Oxide layers 38 and 40 provide an isolation function, which is commonly referred to as field oxide. The area between the field oxides is generally referred to as a mote, and the structure provides an active area, and the field oxide layers 38 and 40 are isolated between various components on the substrate to form an active device in the active area. To provide.

While forming the field oxide layers 38 and 40 by the oxidation process, the oxide is formed at a faster rate upwards than the downward direction of the silicon, with the silicon at the fastest rate in the center of the trenches 24 and 26. Consumed. In addition, the oxidation rates at the contact areas of the bottoms of the trenches 24 and 26 and the nitride sidewall layers 36 and 34 are respectively slower than at the center of the trenches.

During the oxidation process, the edges of the nitride sidewall layers 34 and 36 are lifted by the oxidation process. This is referred to as the channeling effect, and oxygen is drawn up between the silicon and nitride sidewall layers 34 and 36. This results in the formation of a buzz beak 42 underneath the nitride sidewall layer 34 and a buzz beak 44 underneath the nitride sidewall layer 36. The buzz bees 42, 44 are formed up along the inclined edges 28, 30 but extend above the inclined surfaces 28, 30. The extent to which the beads bees 42 and 44 extend upward along the inclined surfaces 28 and 30 is controlled to enable the substrate 10 to be subjected to a vapor oxidation process. In a preferred specific implementation, oxide layers 38 and 40 are about 7000 mm thick.

In FIG. 5A, a detail of the buzz beet 44 formed under the nitride sidewall layer 36 is shown with the same reference numerals. The original location of the trench 24 bottom and the nitride sidewall layer 36 proximate to it is indicated by the dotted line. It can be seen from the dashed line that the end of the sidewall oxide layer, indicated by reference numeral 46, is lifted from the lowest portion of the inclined edge 28. The edge 46 in the actual lift results in an arched surface 48 formed between the nitride sidewall layer 36 and the field oxide layer 40.

As explained below, this curved surface is very important in terms of the deposition of a homogeneous layer thereon. It should be noted that the bead beacon 44 does not extend to all of the inclined edges 28. It is necessary to have a beveled edge 28 area not covered by oxide.

Referring to FIG. 6, after the field oxide layers 38 and 40 are grown, boiling phosphoric acid is used to remove silicon nitride, and HF is removed to remove the oxide layer 12 until pure silicon is introduced. Is used. After the silicon nitride and oxide layer 12 are removed downward until pure silicon enters, a dummy strip oxide layer (not shown) is grown on the silicon to a thickness of about 1000 microns.

The strip oxide growth step has the effect of rounding the corners referred to as 47 and 49. This is due to the fact that the operation of growing the strip oxide layer to 1000 kW thick consumes about 500 kW of silicon on a flat surface. The sharp edges, however, are rich in oxygen, which is useful for the oxidation process, resulting in more silicon consumption compared to silicon consumption on flat surfaces and faster oxidation.

After the strip oxide layer is formed on the substrate surface, the substrate is wet etched with about 50% over etching to remove the strip oxide layer. 50% over etching is important in that it removes the buzz bee 42, 44 portion. This is due to the fact that a wet etching operation must be performed to remove the thermal oxide layer obtained even after the time required for etching 1000 kPa. However, over etching results in the removal of the buzz bee (42) (44) and the end of the buzz bee (42) (44) is recessed along the side walls (28) 30. This results in bead bees 42 'and 44', which increases the exposure of silicon to the sidewalls 28 and 30, resulting in an increase in the total surface area.

Afterwards, the silicon oxide layer 50 is grown by a thermal oxidation process on the substrate to a thickness of about 200 microseconds, which functions as a gate oxide of the MOS transistor.

Polysilicon layer 52 is then deposited by CVD techniques on oxide layer 50 to a thickness of about 4000-5000 mm 3. The conductive surface of silicon extending between the field oxide layers 38 and 40 and below the remaining sloped edge portions 28 and 30 gives a non-planar surface. Therefore, for any given X-Y size of the substrate surface, the total surface area is increased between the virgin bees 42 and 44. Due to the process, the edge of the active region between the sidewalls 28 and 30 and the top surface is considered arched. As the distance between the side walls 28 and 30 decreases, the entire surface becomes similar to a rounded bulge.

Referring to FIG. 7, after the polysilicon layer 52 is formed, the gate of the transistor is lengthened to give a contact surface on top of the buzz bees 42, 44 and the field oxide layers 38, 40. Notice that it is extended and patterned.

The transistor gate is indicated by reference numeral 54. After the gate 54 is formed, the source and drain junctions are ion implanted with impurities of a type opposite to that of the substrate 10. For example, if substrate 10 is a p-type conductor, n-type impurities will be implanted into both substrates of gate 54. This is a conventional self-alignment process whereby the edge of gate 54 is aligned with the S / D junction with respect to the channel region of the transistor, where the channel region lies under the gate 54.

However, any process may be used to form the S / D of the transistor and the gate electrode 54. The transistor source is indicated at 56 and the drain is indicated at 58. It can be seen from the perspective of FIG. 7 that the overall width of the transistor increases with remaining sloped edge portions 28, 30 extending downward from the substrate surface. This forms a bulge on the surface on which the gate electrode 54 is placed. At some point in proximity to the buzz bees 42 and 44, the gate electrode 54 will be formed along the contour of the substrate, thereby increasing the length of the gate, i.e., the transistor width. It can be seen that the sloped edges 28 and 30 actually give an arched surface rather than a vertical edge. Vertical edges are not desirable for transistor gates because fields at sharp edges have a significant impact on transistor operating parameters.

In FIG. 8, after the formation of the gate electrode 54 and the source and drain 56, 58, the transistor is covered with the intermediate level oxime layer 60, and then the contact opening 62 contacts the intermediate level oxide layer 60. And a conductive plug 64 is formed in the opening. Metal layer 66 is then formed on the surface of mid-level oxide layer 60 and patterned to provide a conductive connection between other circuits on the substrate.

In general, it is desirable to make a contact to the gate electrode 54 over the field oxide layer 38 or 40.

9 is a plan view of a modification method for forming a transistor, and the transistor is shown with a capacitor in a one transistor memory cell structure. The device is manufactured by forming a mode formed by the interface 68 included in the capacitor region 70 and the active region 72. Capacitor region 70 may be undoped to form an inverted capacitor or ion implanted to form a depleted capacitor. Active region 72 is used to form transistors. The mode formed by the interface 68 is manufactured similar to the above-described process described in FIGS. The interface 68 consists of an edge of a buzz bee similar to the buzz bee 42, 44. The trench is therefore formed outside the interface 68 and the field oxide layer is formed outside this. After the capacitor region 70 and the active region 72 are formed, a first polysilicon layer is formed thereon to cover the capacitor region 70 and the active region 72 to be exposed. The first polysilicon layer is formed outside of the interface 74. An intermediate level oxide layer is then disposed over the substrate and the active region 72 is exposed again. A gate oxide layer is then formed and a second polysilicon layer is deposited. The second polysilicon layer is patterned to form the gate conductor 76. Source implant 78 is then exposed between gate 76 and capacitor region 70, and source 78 is masked to gate electrode 76 and interface 74.

Source ion implantation 78 connects the lower plane of the capacitor, either the ion implanted region or the inverted region. The drain 80 is formed opposite the source by the gate electrode. Thereafter, a bitline contact 82 is formed. The interface (68) forms an increased surface area that benefits the capacitor, where the capacitor oxide lies below the first polysilicon layer and the first polysilicon layer above the gate oxide layer provides an increased surface area. .

The vertical cross section of the capacitor region 70 after the step formation is shown similarly to FIG. In summary, the process of forming a semiconductor device on a surface that is not planar with respect to the silicon surface has been described. The process involves forming a nitride mask to make the active region of the substrate. A trench is then formed along the side of the nitride mask and a uniform sidewall nitride layer is deposited along the sidewall of the trench.

A field oxide is then grown from the bottom side of the trench such that a buzz bee is formed at the nitride end lower end of the sidewall to lift the nitride end of the sidewall. The buzz beak partially extends over the trench's sloped edges so that the sloped edges remain in silicon. The nitride cap is then removed leaving a conductive surface with increased surface area between the buzz bee interface. Then a semiconductor structure, such as a transistor gate, can be placed in the active region and create a transistor with increased width.

Claims (3)

A method of increasing the surface area of an active region on a semiconductor substrate, the method comprising: forming a protective cap of a predetermined thickness resistant to an oxidation process for a selected surface on a substrate to form a two-dimensional interface, a bottom surface and a first surface; Forming a trench in the surface of the substrate having a sidewall extending downward from the periphery of the two-dimensional boundary of the substrate, forming a protective layer of silicon nitride on the sidewall of the trench, protecting the sidewall and the nitride The outermost edge of the buzz beak defining a second boundary below the first two-dimensional boundary such that a buzz bee is formed on each sidewall extending upward from the bottom of the trench along the sidewalls between the cap layers. Thermally growing a thermal oxide layer in the trench upwards from the bottom surface such that the birds beak extends over the sidewalls, Removing the silicon nitride layer and the protective cap on the sidewalls, and thermally oxidizing the strip oxide layer on the top surface of the active region and the exposed semiconductor material on the sidewalls to consume the semiconductor material to form the strip oxide layer. And removing the strip oxide layer by wet etching so that wet etching continues while the time required to remove the strip oxide layer thickness is exceeded, the surface area of the active region being determined by the first 2. Consisting of the surface area within the dimensional interface and the surface of the sidewall portion not covered with the thermal oxidation layer, and the semiconductor material is consumed at a faster rate to round the edges at the junction between the upper surface and the sidewall of the active area, effectively increasing the surface area. Side walls away from the upper surface of the active area And a portion of the buzz beak is removed such that the buzz beak is recessed downward along the surface area of the active area on the substrate. The method of claim 1 wherein the semiconductor material is silicon and the strip oxide layer is silicon oxide. The method of claim 1, wherein the wet etching is performed for a time of overetching the strip oxide layer by 50%.