KR0143985B1 - Apparatus for outputting moving vector in digital image processor of hdtv - Google Patents

Abstract

The present invention relates to a means for outputting a motion vector in a digital image processor such as an HDTV. In particular, the present invention relates to a motion vector output apparatus capable of outputting not only a motion vector in a frame unit but also a motion vector in a field unit. It is about.

According to the present invention, the n-stage front flip-flop unit 12 and the n-stage multiplexer unit 13, the n-stage rear flip-flop unit 14, and the n-stage selector unit 15 are connected via 2n stages. The odd-field MAE (OMAE) and even-field MAE (EMA) obtained by the hole of even, the even PE logic part 16 and the n-stage summation logic part 17, and the summation result are n-1 comparator parts ( 19) outputs the final motion vector (MV), frame MAE (FMA), odd field MAE (OMA), and even field MAE (EMA) in units of frames in comparison with each other.

Description

Motion vector output device in digital image processor such as HDTV

FIG. 1 (a) is a reference diagram showing a screen search area when a motion vector obtained by a BMA is obtained from a digital image processor.

(b) is a reference diagram representing a reference area in relation to (a).

2 is a reference diagram showing a flow table of basic data for a 32 × 32 pixel search area and a 16 × 16 pixel reference area in a conventional digital image processor.

3 is a system circuit block diagram of a conventional digital image processor.

4 is a search region and a reference region of a digital image processor having field unit motion vector output means according to the present invention.

5 is a flow table of basic data according to the present invention.

6 is a system circuit diagram of a digital image processor having field unit motion vector output means according to the present invention.

* Explanation of symbols for main parts of the drawings

12,22: shear flip-flop portion 13,23: multiplexer portion

14,24: rear flip-flop portion 15: selector portion

16: PE Logic Part 17: Total Logic Part

18,28: control logic 19: comparator

20: multiplexer 21: address generator

25 PE section 26 Comparator

27: test pattern decoder

The present invention relates to a means for outputting a motion vector in a digital image processor such as an HDTV. In particular, the present invention relates to a motion vector output apparatus capable of outputting not only a motion vector in a frame unit but also a motion vector in a field unit. It is about.

In digital image processors such as HDTVs and video phones, motion estimation is performed on an image. Most of the motion estimation is a block matching algorithm (BMA).

This BMA method compares one block of the current frame with each block of the previous frame, finds the most similar block, and finds a motion vector for the position.

For example, by comparing a block of the current frame as shown in (b) in the screen search area of the previous frame as shown in FIG. The most similar block is found in the search area of the n-1) th frame to obtain the motion vector of the part.

FIG. 3 is a conventional circuit system for outputting a motion vector by a flow table of basic data for reference frame data of 16x16 blocks as shown in FIG. 2. The operation is as follows.

The multiplexer 20 is a signal for controlling the output of the n-stage multiplexer unit 23 with n-1 front end flip-flop units 22 when the tester signal TS and the address signal output from the address generator 21 are applied. Outputs

The n-stage multiplexer section 23 selectively outputs the data sequence signals P and P 'input according to the signals applied from the control logic 28 and the n-th stage front flip-flop section 22.

The n-stage PE section 25 subtracts and absolutes the testing vector input (TVS) or data order signal C inputted through the output of the n-stage multiplexer section 23 and the n-1 rear flip-flop sections 24. Value operation, accumulator processing.

The comparator 26 compares the output of the n-stage PE section 25 with the output of the test pattern decoder 27 and outputs a motion vector MV.

Here, n corresponds to n = 6 because the block of the reference region is 16 × 16 blocks, and the outputs of the front flip-flop unit 22 and the multiplexer unit 23 are controlled by the control logic 28. C in the data order shown in FIG. 2 is pixel data of the reference region, P and P 'are pixel data of the search region, and PE0-PE15 of the PE section 25 are MAE (Mean absolute) in the X-axis direction, respectively. error), and the comparator 26 compares this with the output of the test pattern decoder 27 to obtain a motion vector MV.

In this case, MAC = MAE = ∑∑ | a (m, n) -b (m, n) |.

MAE: Mean Absolute Error

However, the conventional motion vector output device as described above requires a large amount of calculation to obtain a motion vector (MV) in units of frames, and it is difficult to perform real-time processing due to a delay to the final output processing due to the use of a complicated circuit. Since there is a problem and only a motion vector in a frame unit can be obtained, when two units are required to be processed in a field unit, two devices must be used in parallel to obtain a good processing efficiency.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to generate and output both a unit of motion and a unit of frame motion vector by systolic array means when outputting a motion vector. To provide a field-based motion vector output device that can simplify the operation and improve its compatible use and processing efficiency.

In order to achieve the above object, the present invention provides an n-1 stage front flip-flop unit enabled by a signal output from control logic and a data order search region enabled by a signal output from the front flip-flop unit. N-stage multiplexer section for selectively outputting signals SW1 and SW2, n-stage rear flip-flop section for buffering data sequence signal r, the data sequence signal r and the data sequence search region signal When (SW1, SW2) is input, n for generating data for obtaining odd field MAE (OMAE) and even field MAE (EMA) by the data order signal r and the data order search area signals SW1, SW2. A 2n-stage hole, an even PE logic unit, and 2n-stages for generating an odd field MAE (OMAE) and an even field MAE (EMA) from respective data output from the n-stage selector unit. Hole, even PE logic part The outputs of the n-stage logic logic unit for summing the odd-field MAE (OMAE) and the even-field MAE (EMA), and the outputs of the n-1 stage comparator unit and the summing logic unit are compared with each other. And a n-1 stage comparator for outputting a final motion vector (MV), a frame MAE (FMA), an odd field MAE (OMA), and an even field MAE (EMA).

Hereinafter, a motion vector output device according to the present invention will be described in detail with reference to the accompanying drawings.

6 is a system circuit diagram of a digital image processor having field unit motion vector output means according to the present invention, wherein the block size is 8x8, i.e., a motion vector output device in a block corresponding to n = 8. The value changes depending on the size of the block.

The front flip-flop portion 12 of the n-1 stage is enabled by a signal output from the control logic 18.

The n-stage multiplexer section 13 is enabled by the signal output from the front flip-flop section 12 to selectively output the data order search region signals SW1 and SW2.

The rear flip-flop unit 14 of the n-1 stage buffers the data order signal r.

The selector section 15 of the n-stage selects the data order signal r and the data order search area signals SW1 and SW2 when the data order signal r and the data order search area signals SW1 and SW2 are input. Generate data for finding odd-field MAE (OMAE) and even-field MAE (EMA).

The 2n-stage hole and even PE logic unit 16 obtains the odd-field MAE (OMAE) and the even-field MAE (EMA) from the respective data output from the n-stage selector unit 15.

The n-stage logic part 17 adds the odd-field MAE (OMAE) and even-field MAE (EMA) output from the 2n-stage hole and the even PE logic part 16, respectively.

The n-1 stage comparator unit 19 compares each of the outputs of the 2n stage holes and the even logic logic units 17 of the n stages of even PE logic unit 16 with each other to obtain a final motion vector (MV) in units of frames, The frame MAE (FMA), odd field MAE (OMA) and even field MAE (EMA) are output.

Here, the eight-stage multiplexer section 13 to which the data order search area signals SW1 and SW2 used in the flowchart of the basic data as shown in FIG. 5 is applied, the seventh stage flip-flop section 12, and seven to which r is applied. At the output of the rear flip-flop unit 15 of the stage, an eight-stage selector unit 15 (S1-S8) for generating holes and even data PE0odd-PE7odd and PE0even-PE7even, respectively, and the eight-stage selector unit 15 Subtracting and absolute value calculation of PE0odd-PE7odd, PE0even-PE7even, and accumulator-processing holes, even 16 (2 × 8) stage PE logic section 16, and this hole, even 16 stage PE logic The outputs of the eight-stage summing logic portion 17 (SM0-SM7), which sequentially add the respective outputs of the negative portions 16 (PE0odd-PE7odd and PE0even-PE7even), are compared with each other, and the final motion vector (MV) in units of frames and And a seven-stage comparator unit 19 (CP1-CP7) for outputting the frame MAE (FMA), odd field MAE (OMA), and even field MAE (EMA).

In the system having the motion vector output device of the present invention as shown in FIG. 6, the screen area to be searched is divided into even and odd numbers as shown in FIG. 4A, and the unit of reference area is allocated as shown in FIG.

At this time, block units are set to 8 pixels x 8 pixels, and search screen areas are set to 16 pixels x 16 pixels, respectively.

Also, the motion vector output device for the PEO and the PEE is operated according to the flow data of the basic data in FIG. 5 related to the hole and even PE based on the search screen area and the reference area range as described above.

Here, PEO stands for PE ODD and PEE stands for PE EVEN.

Therefore, when the selection and control signals (r, SW1, SW2) according to the flow table in FIG. 5 are applied to the motion vector output device, the holes shown in FIG. 5 are made through the eight-stage selector (S: S1-S8). Selected by even 16-speed PE logic parts (PO0-PO7, PE0-PE7) and data by control signals (r, SW1, SW2) are applied respectively. , PE0-PE7) subtract, absolute value calculation, and accumulator processing from the two input vectors on the selector section 15 to generate summed outputs of the respective columns of FIG. 5 so that odd field MAE (OMA) and even field MAE ( EMA), and the 8-stage total logic part (SM0-SM7) is the odd-field MAE (OMA) and the even-field MAE (EMA), which are outputs of holes and even 16-step PE logic parts (PO0-PO7, PE0-PE7), respectively. Summing up to obtain the frame MAE (FMA) for each of the selector sections 15.

In addition, the seven-stage comparator unit CP1-CP7 is a hole, the holes of even 16-stage PE logic units (PO0-PO7, PE0-PE7), even data output and the output of the eight-stage sum logic unit (SM0-SM7) In comparison, a PEE having a smaller MAE (FMA) in units of frames and a motion vector replaced with MAE of a sum logic are added and output.

That is, the first stage comparator CP1 of the seven stage comparator units CP1-CP7 of FIG. 6 is the PE logic of the first and second stages among the 16 stage PE logic units PO0-PO7 and PE0-PE7. The output of PE0) and the output of the first-stage summation logic SM0 among the eight-stage summation logic unit SM0-SM7 are the outputs of the third and fourth-stage PE logics PO1 and PE1 and the second-stage summation logic ( Compared with the output of SM1), the motion vector (MV) is output by adding the motion vector replaced by the PE logic and the sum logic of the MAE (FMA) of the frame unit smaller than the frame unit. The MAE (FMA) outputs the PE logic with the smaller values, the frame MAE (FMA), odd field MAE (OMA), and even field MAE (EMA) of the sum logic.

Similarly, the second stage comparator CP2 has the outputs of the fifth and sixth stage PE logics PO2 and PE2 among the sixteen stage PE logic sections PO0-PO7 and PE0-PE7 and the eight-stage summation logic SM0-SM7. ), The motion vector in which the MAE (FMA) of the frame unit is replaced with the PE logic and the MAE of the summation logic by comparing the output of the third stage summation logic SM2 with the output of the first stage comparator CP1. And outputs the motion vector (MV), and the frame MAE (FMA) of the frame unit is smaller than the PE logic and sum logic logic MAE (FMA), odd field MAE (OMA), even field MAE ( EMA).

Hereinafter, the operation of the third stage, the fourth stage, the fifth stage, the sixth stage, and the seventh stage comparator CP3-CP7 is the same as that of the second stage comparator CP2, and the seventh stage, which is the last comparator The comparator CP7 outputs MAE (FMA), holes, even MAE (OMA, EMA), and motion vectors (MV) in units of frames obtained as a result of the final comparison.

The motion vector output device as described above is configured to process motion vectors and the like in the X-axis direction in the screen navigation area shown in FIG. 4, but the circuit means for processing the motion vectors in the Y-axis direction is the system. After replacing by parallel array means, the outputs of the last two comparators CP7 of the two circuits are compared with each other again to achieve circuit means for selecting the lowest value of MAE.

In addition, in the motion vector output device as described above, the motion vector of each frame such as MV, FMA, OMA, and EMA can also obtain the motion vector of the field unit. Expected and compatible use for.

For example, when the input images are continuous, a similar value is obtained by comparing holes, even fields, motion vectors, and motion vectors in units of frames, and when the images suddenly change, the difference between these values becomes large.

In this case, the motion vector can be selectively operated.

The present invention is advantageous in that it is possible to obtain a motion vector of a field unit or a frame unit in a digital image processing such as HDTV, which can increase the utilization efficiency of such a system well.

Claims (1)

N-1 stage front flip-flop section 12, which is enabled by a signal output from control logic 18, is enabled by a signal output from the front flip-flop section 12, the data order search area signal ( N-stage multiplexer section 13 for selectively outputting SW1, SW2, n-1 stage rear flip-flop section 14 for buffering data order signal r, the data order signal r and the data When order search area signals SW1 and SW2 are input, data for obtaining odd field MAE (OMAE) and even field MAE (EMA) by the data order signal r and the data order search area signals SW1 and SW2. 2n-stage selector section 15 for generating a, and 2n-stage holes for generating odd field MAE (OMAE) and even-field MAE (EMA) from respective data output from the n-stage selector section 15 , The even PE logic section 16, the 2n-stage holes, each of the output from the even PE logic section 16 N-stage summing logic section 17 for summing up Sufield MAE (OMAE) and even-field MAE (EMA), and 2n-stage hole, even PE logic section 16 and n-stage summing logic section 17 To the n-1 stage comparator unit 19 for outputting the final motion vector (MV), frame MAE (FMA), odd field MAE (OMA), and even field MAE (EMA) in units of frames by comparing the respective outputs with each other. Motion vector output device in digital image processor such as HDTV