KR0143200B1 - Controlled gain transistor amplifier without dc shift or signal phase reversal in load current - Google Patents

Abstract

Signal phase inversion as well as DC shift in the load current of the gain control transistor amplifier can be eliminated by using a gain control transistor amplifier of the type having the following means. The gain control transistor amplifier, which eliminates signal shifts as well as DC shift, applies an input signal voltage between the first and second transistors connected as first emitter coupled differential amplifiers and the base electrodes of the first and second transistors. The third and fourth transistors connected as first current splitters including means for interconnecting the emitter electrodes of the third and fourth transistors connected to the collector electrodes of the first transistors; Between the fifth and sixth transistors connected as a second current splitter including an interconnection between the emitter electrodes of the fifth and sixth transistors connected to the collector electrode, and the base electrodes of the third and fourth transistors; Control signal voltages between the fifth and sixth transistors, the base electrodes of the third and fourth transistors, and the base electrodes of the fifth and sixth transistors. Means for applying, an operating potential to the first interconnect between the collector electrodes of the third and sixth transistors, and an operating potential to the second interconnect between the collector electrodes of the fourth and fifth transistors. And at least one of the operation potential applying means includes a means including an output load. Signal phase inversion can be eliminated with improved following means. Means for applying an input signal voltage between the seventh and eighth transistors connected as the second emitter coupled differential amplifier, the base electrodes of the seventh and eighth transistors, and the collector electrodes of the seventh and eighth transistors; Signal phase inversion can be eliminated by having means for connecting separately to the first interconnect and the second interconnect.

Description

[Name of invention]

Gain Controlled Transistor Amplifier with No DC Change or Signal Idol Inversion in Load Current

[Brief Description of Drawings]

1 is a schematic diagram of a gain control amplifier for the prior art having a constant quiescent load current despite a change in gain in response to a change in the value of a control signal that sets the value of the amplifier gain,

2 is a schematic diagram of a gain control amplifier improved from FIG. 1 as an embodiment of the present invention;

3 is a schematic diagram of a gain control amplifier improved from FIG. 1 as another embodiment of the present invention;

4 is a schematic diagram of a gain control amplifier improved from FIG. 2 as another embodiment of the present invention;

5 is a schematic diagram of a gain control amplifier that improves FIG. 3 as yet another embodiment of the present invention.

[Technical Field]

The present invention relates to gain-controlled transistors (Controlled-Gain Transistor Amplifiers) having a constant quiescent load current despite a change in gain in response to a change in the value of the control signal.

Background of the Invention

In general, the gain of an emitter-coupled differential amplifier consisting of first and second transistors of a particular conductivity type is obtained by supplying the collector current of the first transistor to the first control current splitter. Similar to the first control current splitter, by supplying the collector current of the second transistor to the second control current splitter, controlling the first and second control current splitters using the same control signal, and a current splitter for applying to the load Controlled by cross-coupling the output currents, thereby obtaining a constant quiescent load current despite a change in gain in response to a change in value of the control signal. Each control current splitter receives a control voltage between their base electrodes and has a split current flowing through the interconnect between their emitter electrodes, the current of which flows through their respective collector electrodes. And a pair of emitter coupled transistors each having split shares. The third, fourth, fifth and sixth transistors of the splitters are similar in structure to each other, adjacent to each other in an integrated circuit, and of similar conductivity type to the first and second transistors. Prior art of gain control amplifiers is disclosed in US Pat. No. 4,471,311, entitled DETECTOR CIRCUIT HAVING AGC FUNCTION, filed September 11, 1984. It is also disclosed in US Pat. No. 4,928,074, filed May 22, 1990, entitled Sato and many others AUTOMATIC GAIN CONTROL CIRCUIT.

However, such a gain control amplifier has a problem in that an increase gain with an incident phase inversion occurs due to a control voltage oscillating based on a zero generated as a control voltage between base electrodes decreases to zero potential. This property is extremely undesirable for any application. For example, in an Automatic Gain Control (AGC) system, under certain conditions, this phase reversal characteristic is not desirable to increase the gain rather than reduce the gain of the AGC under strong signal conditions. Cause failure. Accordingly, a problem of a gain control amplifier having a constant stop load current according to a change in gain has been recognized, and an object of the present invention is to influence the result of the applied driving supply voltage without losing the characteristics of the constant stop load current according to the change in gain. It is to provide a gain control amplifier that does not lose any range in the received output voltage.

[Summary of invention]

The present invention is implemented by improving the gain control transistor amplifier having a constant stop load current even though the gain changes in response to the control signal voltage. The gain control transistor amplifier includes first and second transistors connected as first emitter coupled differential amplifiers, means for applying an input signal voltage between the base electrodes of the first and second transistors, and a first current splitter. And third and fourth transistors connected as a interconnection between the collector electrode of the first transistor and the emitter electrodes of the third and fourth transistors, and connected as a second current splitter and the collector of the second transistor. Fifth and sixth transistors comprising an interconnection between an electrode and emitter electrodes of the fifth and sixth transistors, between base electrodes of the third and fourth transistors and the base of the fifth and sixth transistors Means for applying a control signal voltage between the electrodes and a first interconnect between the collector electrodes of the third and sixth transistors And means for applying a drive potential and means for applying a drive potential by second interconnection between collector electrodes of said fourth and fifth transistors. At least one of the means for applying the driving potential includes an output load. Improvements in the gain control transistor amplifier include: means for applying an input signal voltage between the seventh and eighth transistors connected as a second emitter coupled differential amplifier, and the base electrodes of the seventh and eighth transistors; Means for separating and connecting the first and second interconnections and the collector electrodes of the seventh and eighth transistors.

Detailed description of the invention

FIG. 1 shows NPN transistors connected as an emitter coupled differential amplifier configuration for requesting collector currents at a rate set by an input signal voltage which is a power supply S1 applied between base electrodes of NPN transistors Q1 and Q2. Q1 and Q2) are shown. Emitter electrodes of Q3 and Q4 to receive the emitter currents of Q3 and Q4, respectively, with a ratio set by the gain control voltage, which is the power supply S2 applied between the base electrodes of the NPN transistors Q3, Q4. The collector electrode of Q1 is connected to the node N1 in between, and Q1 divides each emitter current split by the NPN transistors Q3 and Q4 connected as the first current splitter. It is supplied to the collector electrode through the node N1. The ratio set by the gain control voltage, which is the power supply S2 applied between the base electrodes of the NPN transistors Q5 and Q6, between the emitter electrodes of Q5 and Q6 so as to receive the emitter currents of Q5 and Q6, respectively. The collector electrode of Q2 is connected to node N2 at which Q2 is coupled to each node by the emitter currents split by NPN transistors Q5 and Q6 connected as a second current splitter. It is supplied to the collector electrode through the furnace.

The resistor R1 is connected between the node N3 between the collector electrodes of Q3 and Q6 and the drive supply voltage terminal where the DC voltage supplies B1, B2, B3 and B4 are determined by series connection. R1 provides a common collector load for Q3 and Q6. The resistor R2 is connected between the node N4 between the collector electrodes of Q4 and Q5 and the driving supply voltage terminal determined by the series connection of the DC voltage supplies B1, B2, B3 and B4.

Similar constant currents are required from node N5 and node N6 connected to the emitter electrodes of Q1 and Q2 as shown in FIG. The NPN transistors Q9 having the emitter resistor R3 set the conditions for requesting a constant collector current from the node N3 by receiving the bias voltage from the DC voltage supply B1 as the base electrode. The NPN transistors Q10 having the emitter resistor R4 set a condition for requesting a constant collector current from the node N4 by receiving a bias voltage from the DC voltage supply B1 to the base electrode. Resistor R0 coupled between node N5 and node N6 provides an emitter-degeneration resistor coupled to Q1 and Q2. This arrangement avoids the direct potential drop across the emitter degeneration resistor R0 and maintains the drive voltage range.

In another embodiment, if only DC voltage supply B1 provides a sufficiently high voltage, rod N5 and rod N6 may be connected to ground potential through respective resistors rather than Q9 and Q10. In another embodiment, resistor R0 is connected to the middle tap (Center-Tap) and a constant current is required from the middle tap rather than the constant currents required from node N5 and node N6. Another such embodiment includes the special case where half of the intermediate tap resistor R0 has a substantially zero resistance value.

In some cases, when the voltage VS1 supplied from the power supply S1 is zero potential, the collector currents of Q1 and Q2 cause the same stop or direct current current values. And when VS1 has a value other than zero potential, the collector currents of Q1 and Q2 represent the equipotential and opposite pole changes -VS1 / R0 and VS1 / R0. Here, the resistance value of the resistor R0 is R0. (The relatively small base currents of transistors Q1, Q2, Q3, Q4, Q5 and Q6 will be ignored in a simple analysis of driving. Thus, the emitter currents of each of these transistors are substantially equal to collector currents. The same amount of current will be assumed.) When the voltage VS2 supplied from the power source S2 is zero potential, Q3 and Q4 require -VS1 / required by Q3 and Q4 supplied in equal amounts as the respective emitter currents. R0 collector current is assigned, and Q5 and Q6 also allocate the -VS1 / R0 collector current required by Q2 to Q5 and Q6 supplied in equal amounts as the respective emitter currents. The -VS1 / 2R0 emitter current of Q3 and the VS1 / 2R0 emitter current of Q6 require the collector signal current required by Q3 and Q6 and the VS1 / 2R0 collector signal current of Q6 respectively. The sum of collector signal currents required by Q3 and Q6 is a current flowing through the common collector load resistor R1 of Q3 and Q6, and the value of the current is 0, which is the sum of the collector signal currents of Q3 and Q6. According to Ohm's law, the voltage across R1 during these driving conditions is a zero signal voltage. The -VS1 / 2R0 emitter current of Q4 and the VS1 / 2R0 emitter current of Q5 require the -VS1 / 2RO collector signal current of Q4 and the VS1 / 2RO collector signal current of Q5 respectively. The sum of collector signal currents required by Q4 and Q5 is a current flowing through the common collector load resistor R2 of Q4 and Q5, and the value of the current is 0 which is the sum of the collector signal currents of Q4 and Q5. According to Ohm's law, the voltage across R2 during these driving conditions is a zero signal voltage. When the direct voltage supplied by the power supply S1 has a positive value, the collector signal current value required at Q1 supplied as the emitter current by Q3 increases to (1 + δ) (-VS1 / 2R0), and Q4 The value of the collector signal current required at Q1 supplied as the emitter current by? Decreases to (1-?) (-VS1 / 2R0). In addition, the value of the collector signal current required in Q2 supplied as the emitter current by Q5 increases to (1 + δ) (VS1 / 2R0), and the collector signal current required in Q2 supplied as the emitter current by Q6. The value of decreases to (1-δ) (VS1 / 2R0). The collector signal currents required at Q3 and Q6 are substantially the same as the emitter signal currents (1 + δ) (−VS1 / 2R0) and (1-δ) (VS1 / 2R0) of Q3 and Q6 respectively. In accordance with Ohm's law, the combined current (-δ VS1 / R0) of the collector signal currents required at Q3 and Q6 drops across the collector load resistor (R1) shared by Q3 and Q6 to (-δ VS1R1 / 2R0). It causes. Here, the resistance value of the resistor R1 is R1. The collector signal currents required at Q4 and Q5 are substantially the same as the emitter signal currents (1-δ) (-VS1 / 2R0) and (1 + δ) (VS1 / 2R0) of Q4 and Q5. The combined current (δ VS1 / R0) of the collector signal currents required at Q4 and Q5 according to Ohm's law causes the voltage drop to (δ VS1R2 / R0) through the collector load resistor (R2) shared by Q4 and Q5. Becomes Here, the resistance value of the resistor R2 is R2. As mentioned in the background of the invention described above, the polarities of the signal voltages through the collector load resistors R1 and R2 are undesirably inverted when the direct voltage supplied by the power supply S1 becomes an ohmic potential value. . The share of the collector signal current demand of Q1 supplied as the emitter current of Q3 is reduced to (1-δ) (-VS1 / 2R0), and the share of the collector signal current request of Q1 supplied as the emitter current of Q4 is ( 1 + δ) (−VS1 / 2R0). Also, the share of the collector signal current request of Q2 supplied as the emitter current of Q5 is reduced to (1-δ) (VS1 / 2R0), and the share of the collector signal current request of Q2 supplied as the emitter current of Q6 is ( 1 + δ) (VS1 / 2R0). The collector signal currents required at Q3 and Q6 are substantially the same as the emitter signal currents (1-δ) (−VS1 / 2R0) and (1 + δ) (VS1 / 2R0) of Q3 and Q6. According to Ohm's law, the combined current (δ VS1 / R0) of the collector signal currents required at Q3 and Q6 drops to the voltage of (δ VS1R1 / R0) through the collector load resistance (R1) shared by Q3 and Q6. . Here, the resistance value of the resistor R1 is R1. The collector signal currents required at Q4 and Q5 are substantially the same as the emitter signal currents (1 + δ) (−VS1 / 2R0) and (1-δ) (VS1 / 2R0) of Q4 and Q5. In accordance with Ohm's law, the combined current (-δ VS1 / R0) of the collector signal currents required at Q4 and Q5 is passed through the collector load resistor (R2) shared by Q4 and Q5 to the voltage of (-δ VS1R2 / R0). Descend. Here, the resistance value of the resistor R2 is R2.

In FIGS. 2 and 3, the NPN transistors Q7 and Q8 are applied to the input signal voltage that the power supply S1 applies between their respective base electrodes as well as between their respective base electrodes of Q1 and Q2. It is similar to NPN transistors Q1 and Q2 connected as an emitter coupled differential amplifier configuration for requiring collector currents with a ratio determined by. The emitter circuits of Q7 and Q8 are largely the same as the emitter circuits of Q1 and Q2. That is, like the resistor R0, the resistor R7 is connected between the node N7 and the node N8 to which the emitter electrodes of Q7 and Q8 are connected, respectively, and the NPN transistors Q11 and Q12 are connected to Q9 and Q10. Requiring the same constant collector currents from node N7 and node N8 as required from node N5 and node N6, and having emitter degeneracy resistors R3 and R4 for Q9 and Q10; Likewise, it has emitter degeneration resistances R5 and R6 for Q11 and Q12. Q7 and Q8 require collector currents (-VS1 / R0 and VS1 / RO) when VS1 has a value other than zero potential. In FIG. 2, collector electrodes of Q7 and Q8 are connected to node N3 and node N4, respectively. When the direct voltage supplied by the power supply S1 has a positive potential value, according to the principle of superposition, the signal voltage drop through the collector load resistor R1 due to the combined collector signal current demands of Q3 and Q6 ( -δ VS1R1 / R0) is increased by the component of the signal voltage drop -VS1R1 / R0 due to the collector signal current demand of Q7. Therefore, R1 results in a signal voltage drop of VR1 = (1 + δ) (VS1R12 / R0). The polarity sensitivity of VR1 becomes negative at one range or more at the total -1 of δ. The component of the signal voltage drop (δ VS1R2 / RO) through the collector load resistance (R2) due to the combined collector signal current requests of Q4 and Q5 results in the signal voltage drop VS1R1 / R0 Increased by ingredients Therefore, R2 results in a signal voltage drop of VR2 = (1 + δ) (VS1R1 / R0). The polarity sensitivity of VR2 becomes positive in the range of -1 to the total -1 of δ.

In FIG. 3, the collector electrodes of Q7 and Q8 are connected to node N4 and node N3, respectively. When the direct voltage supplied by the power supply S1 has a positive potential value, according to the principle of superposition, the signal voltage drop through the collector load resistor R1 due to the Q3 and Q6DML coupled collector signal current demands ( The component of -δ VS1R1 / R0) is increased by the component of the signal voltage drop VS1R1 / R0 due to the collector signal current demand of Q8. Therefore, R1 results in a signal voltage drop of VR1 = (1-δ) (VS1R1 / R0). The polarity sensitivity of VR1 becomes positive in the range of 1 or more in the total -1 of δ. The component of the signal voltage drop (δ VS1R2 / R0) through the collector load resistance (R2) due to the combined collector signal current requests of Q4 and Q5 causes the signal voltage drop due to the collector signal current demand of Q7 -VS1R1 / R0. It is increased by the component of. Therefore, R2 results in a signal voltage of VR2 = (-1 + δ) (VS1R2 / R0). The polarity sensitivity of VR2 becomes negative in one or more ranges from the total -1 of δ.

As a further guarantee for the polarity sensitivity inversion of the controlled signals, a resistor R7 will be made, so that the resistance value R7 of the resistor R7 is somewhat less than the resistance value R0 of the resistor R0. Have Therefore, the final signal attenuation available for the gain control amplifier will be somewhat reduced. This effect will be used as an advantage in delayed AGC systems. 4 and 5 are individual variations of the gain control amplifiers of FIGS. 2 and 3, in which the common base amplifiers NPN transistors Q13 and Q14 are connected in series to each of the emitter coupled differential amplifiers NPN transistors Q7 and Q8. . The base electrodes of Q13 and Q14 are biased similarly to the base electrodes of Q3, Q4, Q5 and Q6, so that emitter follower operation of Q13 and Q14 results in emitter follower operation of Q3, Q4, Q5 and Q6. Position the collector potentials of Q7 and Q8 similarly as the collector potentials of and Q2. This fact somewhat demonstrates that the gains of the emitter coupled differential amplifier pairs Q7 and Q8 match the gains of the emitter coupled differential amplifier pair Q1 and Q2. Rather than recognizing a second emitter coupled amplifier using transistors Q7 and Q8 independent of transistors Q1 and Q2 of the first emitter coupled amplifier, replace Q1 and Q7 with a single split-collector transistor, Q2 and Q8 may be replaced by one second split-collector transistor. The first and second split-collector transistors are emitter coupled and are driven by a power supply of an input signal voltage applied between the base electrodes of each transistor. Such equivalent circuits are entitled HIGH-GAIN DIFFERENTIAL AMPLIFIER, filed U.S. Patent No. 4,216,436, filed by Lefferts on August 5, 1980, and LOW OFFSET CMOS COMPARATOR CIRCUIT, filed U.S. Patent No. 4,602,168, filed July 22, 1986. Is disclosed.

One of ordinary skill in the art of circuit design recognizes that the collector load connected to node N3 and the collector load connected to node N4 may be configured not only as clearly shown in FIGS. You can do it. Modifications of the circuit described are possible by the output signal being adopted as single-ended rather than balanced, with one of the collector loads connected directly to the operating voltage supply or substantially free of impedance. It is replaced by

Although the present invention has been described with particular emphasis on the design of bipolar transistors that are particularly well applied, they may also be implemented in equivalent field effect transistor (FET) circuits. As a more particular example, an emitter coupled differential amplifier using a bipolar transistor in integrated circuit technology of coupled bipolar transistors and metal oxide semiconductor transistors can be source coupled using field effect transistors without departing from the spirit of the invention provided herein. It can be replaced by a differential amplifier.

Those skilled in the art of transistor design and those skilled in the above description will be able to design many alternative embodiments of the present invention and should bear in mind the above facts when interpreting the scope of the appended claims. do.

Claims (5)

An input signal between the first, second, third, fourth, fifth, and sixth transistors having respective base electrodes, emitter electrodes, and collector electrodes, and base electrodes of the first and second transistors; Means for connecting said first and second transistors as a first emitter coupled differential amplifier comprising means for applying a voltage, and the emitter electrodes of said third and fourth transistors connected to a collector electrode of said first transistor; Means for connecting said third and fourth transistors as a first current splitter comprising an interconnection therebetween and including means for applying said control signal voltage between base electrodes of said third and fourth transistors; Interconnecting the emitter electrodes of the fifth and sixth transistors connected to the collector electrodes of the second transistor and using the base electrodes of the fifth and sixth transistors. A second current splitter comprising means for applying said control signal voltage to said first sixth transistor and means for connecting said drive potential to a first interconnect which is between collector electrodes of said third and sixth transistors. And at least one of the means for applying and the means for applying the driving potential to the second interconnect between the collector electrodes of the fourth and fifth transistors comprises an output load. A gain control transistor amplifier always having a constant load current in spite of a change in gain corresponding to a control signal voltage; And seventh and eighth transistors each having a base electrode, an emitter electrode, and a collector electrode, and means for applying the input signal voltage between the base electrodes of the seventh and eighth transistors. Means for connecting the seventh and eighth transistors as a second emitter coupled differential amplifier comprising means for separately connecting collector electrodes of an eighth transistor to the first and second interconnects; Gain control transistor amplifier, characterized in that. 2. The apparatus of claim 1, wherein the means for separately connecting collector electrodes of the seventh and eighth transistors to the first interconnection and the second interconnection connect the collector electrodes of the seventh and eighth transistors to the first interconnection. Gain control transistor, characterized in that it is of a type that connects separately to said second interconnect. 3. The apparatus of claim 2, wherein the means for separately connecting collector electrodes of the seventh and eighth transistors to the first interconnection and the second interconnection comprises: an emitter electrode connected to the collector electrode of the seventh transistor; A ninth transistor having a base electrode and a collector electrode connected to said first interconnection, an emitter electrode connected to a collector electrode of said eighth transistor, a base electrode and a collector electrode connected to said second interconnection; And a means for applying a similar direct bias voltage to the base electrodes of the third, fourth, fifth, sixth, ninth, and tenth transistors. . 2. The apparatus of claim 1, wherein the means for separately connecting collector electrodes of the seventh and eighth transistors to the first interconnection and the second interconnection comprises: collecting collector electrodes of the seventh and eighth transistors of the second Gain control transistor, characterized in that the interconnection and the first interconnection type are individually connected. An emitter electrode according to claim 4, wherein means for connecting the collector electrodes of the seventh and eighth transistors separately to the first interconnection and the second interconnection is connected to the collector electrode of the seventh transistor. And a ninth transistor having a base electrode and a collector electrode connected to the second interconnection, an emitter electrode connected to the collector electrode of the eighth transistor, and a collector electrode connected to the first interconnection. And a means for applying a similar direct bias voltage to the base electrodes of the third, fourth, fifth, sixth, ninth, and tenth transistors. Transistor amplifier.