KR0141190B1 - Fabrication method of mosfet for high breakdown voltage - Google Patents

Abstract

A method of manufacturing a MOS transistor having a high breakdown voltage is disclosed. A pad oxide film, a polysilicon layer, and a silicon nitride film are stacked on a semiconductor substrate, the silicon nitride film is etched to expose the polysilicon layer corresponding to the first to fourth regions on the substrate, and then the second region adjacent to the channel region. The first impurity region is formed in part of the second region and the third region, and the second impurity region is formed in the remaining region of the second and third regions and the channel region of the first region and the fourth region. Subsequently, a third impurity region is formed in the remaining regions of the first and fourth regions, a field oxide film is formed in the first to fourth regions, and the silicon nitride film, the polysilicon layer, and the pad oxide film are removed. Forming a gate oxide film on the resultant, forming a gate polysilicon layer, and then forming a fourth impurity region in a region between the first region and the second region and a region between the third region and the fourth region, A fifth impurity region is formed adjacent to the third impurity region.

According to the present invention, by maintaining the concentration distribution from the channel to the drain at low, medium and high concentrations, the voltage applied to the drain is effectively dispersed, and the increase in operating resistance is suppressed by adding the medium concentration region. can do.

Description

Manufacturing method of high breakdown voltage MOS transistor

1A to 4B are cross-sectional views of a process for explaining a method of manufacturing a driving IC which is generally used.

5A to 8B are cross-sectional views of a process for explaining a method of manufacturing a high breakdown voltage MOS transistor according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a MOS transistor capable of withstanding high voltage.

As an example of a semiconductor device requiring high breakdown voltage, a driving IC used in a liquid crystal display device may be mentioned. In general, since the driving IC must be connected to a peripheral device, a high breakdown voltage, a high operating voltage, a high driver current, and a low on state resistance are required. Etc. are required. In order to satisfy such requirements, the driving IC is generally designed to have a low resistance doped diffusion resistor, but the lower the concentration of the lightly doped diffusion layer, the higher the breakdown voltage, but the driving current capability and operating voltage. Will be lowered. In addition, the low concentration of the diffusion layer causes an increase in the operating resistance (Ron), which causes a problem that must increase the size of the chip.

An example of a MOS transistor manufacturing process currently used for manufacturing a general driving IC will be described with reference to FIGS. 1A to 4B.

1a, 2a, 3a, and 4a show mask patterns, and 1b, 2b, 3b, and 4b show vertical cross-sectional views of regions across each mask pattern A-A '.

FIG. 1A illustrates a first mask pattern ml for forming a silicon nitride film pattern.

Referring to FIG. 1B, a pad oxide film 12 is grown on the semiconductor substrate 10. Subsequently, after the silicon nitride layer 14 is formed on the pad oxide layer 12, the silicon nitride layer is etched using the first mask pattern ml to expose the first to fourth regions a to d. do.

Referring to FIG. 2A, the first mask pattern may include a second mask pattern m2 for defining the first impurity region 20 and a third mask pattern m3 for defining the second impurity region 22. Layout added to (ml).

Referring to FIG. 2B, a field oxide layer 16 is formed in the first to fourth regions a to d using the silicon nitride layer 14 as a mask, and then the silicon nitride layer 14 and the pad oxide layer are formed. Remove (12). Subsequently, the first impurity for adjusting the internal pressure and the second impurity for channel blocking are implanted into the substrate 10 using the second mask pattern m2 and the third mask pattern m3. It diffuses to form the first impurity region 20 and the second impurity region 22.

Referring to FIG. 3A, the fourth mask pattern m4 for forming the gate polysilicon layer 26 is added to the first to third mask patterns ml to m3.

Referring to FIG. 3B, an oxide film is formed on the resultant product in which the first and second impurity regions 20 and 22 are formed, a polysilicon layer is laminated on the oxide film, and then the fourth mask pattern m4 is formed. ) To form the gate oxide film 24 and the gate polysilicon layer 26.

Referring to FIG. 4A, the fifth mask pattern m5 for defining the third impurity region 28 is added to the first to fourth mask patterns ml to m4.

Referring to FIG. 4B, a third impurity for forming a source and a drain region on the resultant product on which the gate polysilicon layer 26 is formed is formed on the substrate 10 using the fifth mask pattern m5. After ion implantation, it is diffused to form a third impurity region 28 corresponding to the source and the drain. Subsequently, the guard ring 30 is formed by ion implantation of the fourth impurity into an outer region of the second impurity region 22 for channel blocking.

According to the conventional method described above, the first impurity of the opposite conductivity type to the substrate is ion implanted at low concentration. As described above, the ion implanted low concentration diffusion layer slightly increases the breakdown voltage but decreases the driving current capability and the operating voltage. Let's do it. In addition, such a low concentration diffusion layer causes an increase in operating resistance (Ron), which causes a problem that the size of the chip must be increased.

Accordingly, it is an object of the present invention to provide a method for manufacturing a MOS transistor which can suppress an increase in operating resistance and at the same time realize a high breakdown voltage.

The present invention to achieve the above object,

Stacking a pad oxide film, a polysilicon layer, and a silicon nitride film on a semiconductor substrate, etching the silicon nitride film to expose the polysilicon layer corresponding to the first to fourth regions on the substrate, and a second adjacent channel region Forming a first impurity region by ion implanting a first impurity of a conductivity type opposite to the substrate into a portion of the region and a portion of the third region, the remaining regions of the second and third regions adjacent to the first impurity region, and Ion implanting a second impurity of a conductivity type opposite to the substrate into partial regions of the channel side of the first and fourth regions to form a second impurity region, and remaining regions of the first and fourth regions adjacent to the second impurity region Implanting third impurities of a conductive type such as a substrate into the third impurity region, diffusing the first to third impurities after the ion implantation, and simultaneously forming the silicon nitride film. Forming a field oxide film in the first to fourth regions using a mask, removing the silicon nitride film, the polysilicon layer, and the pad oxide film; growing an oxide film on the resultant and patterning the oxide film to form a gate oxide film And depositing polysilicon on the gate oxide layer and then patterning the same to form a gate polysilicon layer, in a region between the first region and a second region, and in a region between the third region and the fourth region. Ion implanting a fourth impurity of conductive type such as a substrate to form a fourth impurity region, and a fifth impurity of conductive type such as a substrate in a fifth impurity region adjacent to the third impurity region and corresponding to a guard ring region It provides a MOS transistor manufacturing method comprising the step of ion implantation and diffusion of impurities.

At this time, the second impurity is injected at a higher concentration than the first impurity, and the third impurity is injected at a higher concentration than the second impurity.

Meanwhile, when the first and third impurities are n-type, the ion implantation conditions are adjusted to have an implantation energy of 100 to 200 (keV) and a dose of 3,0El 2 to 1.0El 3 (ions / cm 2). When the first and third impurities are P-type, the ion implantation conditions are adjusted to have an implantation energy of 50 to 150 (keV) and a dose amount of 1.0 El 3 -1.0 El 4 (ions / cm 2). Further, when the second impurity is n-type, the ion implantation conditions are implantation energy of 70 to 180 (keV) and dose amount of 1.0 El 3 to 1.0 El 5 (ions / cm 2), and when the second impurity is P type, The ion implantation conditions are adjusted by the implantation energy of 50 to 150 (keV) and the dose amount of 1.0 El 4 to 2,0 El 5 (ions / cm 2). When the fourth and fifth impurities are n-type, the ion implantation conditions are injection energy of 40 to 80 (keV) and dose amount of 1.0 El 5 to 1.0 El 6 (ions / cm 2). In the case of P type, the ion implantation conditions are adjusted by the implantation energy of 40 to 80 (keV) and the dose amount of 1.0 El 5 to 1.0 El 6 (ions / cm 2). In addition, the field oxide film is preferably formed after annealing first in a nitrogen atmosphere at a temperature of 950 to 1050 캜.

As described above, according to the present invention, by maintaining the concentration distribution from the channel to the drain at low / medium / high concentration, it effectively disperses the voltage applied to the extraordinary, and operates by adding a medium concentration region. The increase in resistance can be suppressed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5A to 8B are cross-sectional views of a process for describing an embodiment of a method for manufacturing a high breakdown voltage MOS transistor according to the present invention.

5a, 6a, 7a. And Fig. 8A shows a mask pattern, and Figs. 5B, 6B, 7B, and 8B show vertical cross-sectional views of regions crossing C-C 'of each mask pattern.

5A shows a first mask pattern pl for forming a silicon nitride film pattern.

Referring to FIG. 5B, a pad oxide film 102 is grown on the semiconductor substrate 100 for stress relaxation. Subsequently, a polysilicon layer 104 is laminated on the pad oxide film 102 using low pressure vapor deposition (LPCVD), and then a silicon nitride film 106 is laminated on the polysilicon layer. In this case, the pad oxide film 102 is preferably formed to have a thickness of 500 to 900 GPa, the polysilicon insect 104 to 1000 to 1500 GPa, and the silicon nitride film 106 to have a thickness of 1500 to 2000 GPa. Subsequently, the silicon nitride film 106 is reactive by using a first mask rubbing pl to expose the polysilicon insects 104 corresponding to the first to fourth regions 91 to 94 on the substrate 100. It is etched by ion etching (RIE) method.

FIG. 6A is a layout in which a second mask pattern p2 for defining the first impurity region 108 is added to the first mask pattern pl.

Referring to FIG. 6B, a first impurity of a conductivity type opposite to that of the substrate is applied to a portion of the second region 92 and a portion of the third region 93 adjacent to the channel region by using the second mask pattern p2. Ion implantation forms the first impurity region 108. At this time, the first impurity is injected at low concentration. For example, when the body 1 impurity is n-type phosphorus (P), ion implantation energy of 100 to 200 (keV) and 3.0 El 2 to 1.0 El 3 (ions / cm 2) When the first impurity is P-type boron (B) under the conditions of the dose amount of (), the ion is supplied under the conditions of the ion implantation energy of 50 to 150 (keV) and the dose amount of 1.0 El 3 to 1.0 El 4 (ions / cm 2). It is preferable to inject.

FIG. 7A illustrates a third mask pattern p3 for defining the second impurity region 110 and a fourth mask pattern p4 for defining the third impurity region 112. Layouts added to pl and p2).

Referring to FIG. 7B, a region surrounding the silicon nitride film, that is, the second impurity region adjacent to the first impurity region 108, is formed using the third mask pattern p3. The second impurity region (I) is implanted into the remaining regions of the third regions 92 and 93 and the second impurities of the opposite conductivity type to the substrate in the partial regions on the channel side of the first and fourth regions 91 and 94. 110). At this time, the second impurity is injected at a higher concentration than the first impurity, but is injected at a low concentration and a medium concentration of high concentration. For example, when the second impurity is n-type phosphorus (P), 70 to 180 (keV). Ion implantation energy) and a dose amount of 1.0 El 3 to 1.0 El 5 (ions / cm 2), when the second impurity is P-type boron (B), ion implantation energy of 50 to 150 (keV) and 1.0 E14 It is preferable to perform ion implantation under the condition of a dose amount of ˜2.0 El 5 (ions / cm 2).

Subsequently, a third impurity of a conductive type such as a substrate is applied to the remaining regions of the first and fourth regions 91 and 94 adjacent to the second impurity region by using the fourth mask pattern p4. Ion implantation forms the third impurity region 112. In this case, the third impurity may be ion implanted under the same condition as the first impurity.

Referring to FIG. 8A, the fifth mask pattern p5 for defining the fourth impurity region 118 and the sixth mask pattern p6 for forming the polysilicon gate pattern may include the first to fourth mask patterns ( pl to P4).

Referring to FIG. 8B, the silicon nitride film 106 is used as a mask while diffusing the impurities implanted in a furnace at 1000 ° C. with respect to the resultant ion implanted first to third impurities. A field oxide film 113 having a thickness of 5000 to 9000 Å is grown in the first to fourth regions 91 to 94. At this time, it is preferable to perform annealing in nitrogen atmosphere of the temperature of 950-1050 degreeC before forming the said field oxide film first. Subsequently, the silicon nitride film 106, the polysilicon layer 104, and the pad oxide film 102 are removed, and then the gate oxide film 114 for the high voltage transistor is grown to a thickness of 500 to 1000 Å and the sixth mask pattern ( p6) is wet etched so that the oxide film 114 remains only in the high voltage transistor region. On the other hand, the gate oxide film for the low voltage transistor is grown to a thickness of 100 to 150 kV, the polysilicon layer is deposited to a thickness of 3000 to 4500 kV, doped with impurities, such as POCl ₂ , and then the sixth mask pattern p6. The polysilicon layer is etched to form the gate polysilicon layer 116. In addition, the substrate may be formed in the region between the first region 91 and the second region 92 and the region between the third region 93 and the fourth region 94 by using the fifth mask pattern p5. The fourth impurity of the conductive type as described above is ion-implanted and the source and drain 118 are formed through a diffusion process.

Subsequently, a fifth impurity of the same conductivity type as a substrate is ion-implanted into the fifth impurity region 120 adjacent to the third impurity region 112 and corresponding to the guard ring region, and then a guard ring is formed through a diffusion process. . At this time, the fourth impurity and the fifth impurity are implanted at a higher concentration than the second impurity. For example, when the fourth and fifth impurity are n-type arsenic (As), ions of 40 to 80 (keV) are used. Under the conditions of the implanted energy and the dose amount of 3.0 El 5 to 1.0 El 6 (ions / cm 2), when the fourth and fifth impurities are boron (B) of P type, ion implantation energy of 40 to 80 (keV) and 1.0 E 15 It is preferable to perform ion implantation on condition of the dose amount of -1.0El6 (ions / cm <2>).

As described above, according to the present invention, since the concentration distribution of the current path from the channel region to the drain region is formed in a low concentration / medium concentration / high concentration step, the voltage applied to the drain is between the substrate and the first impurity region. Are distributed at the p / n junction, the boundary point between the first impurity and the second impurity, and the boundary point between the second impurity and the fourth impurity, so that the maximum value of the horizontal electric field distribution can be lowered and high operating voltage can be realized. In addition, the increase in the operating resistance can be suppressed by adding a medium concentration region as compared with the related art.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea to which the present invention pertains.

Claims (10)

Stacking a pad oxide film, a polysilicon layer, and a silicon nitride film on a semiconductor substrate; Etching the silicon nitride film to expose the polysilicon layers corresponding to the first to fourth regions on the substrate; Forming a first impurity region by ion implantation of a first impurity of a conductivity type opposite to the substrate in the second region and the third region adjacent to the channel region; A second impurity region is formed by ion implanting a second impurity of a conductivity type opposite to the substrate in the remaining regions of the second and third regions adjacent to the first impurity region and a portion of the channel side of the first and fourth regions. Doing; Forming a third impurity region by ion implanting a third impurity of a conductive type such as a substrate into the remaining regions of the first and fourth regions adjacent to the second impurity region; Diffusing the first to third impurities after the ion implantation and simultaneously forming a field oxide film in the first to fourth regions using the silicon nitride film as a mask; Removing the silicon nitride film, the polysilicon layer, and the pad oxide film; Growing an oxide film on the resultant and patterning the oxide film to form a gate oxide film; Depositing polysilicon on the gate oxide layer and then patterning the same to form a gate polysilicon layer; Ion implanting a fourth impurity of a conductive type such as a substrate into a region between the first region and the second region and a region between the third region and the fourth region to form a fourth impurity region, and the third impurity And implanting and diffusing a fifth impurity of a conductive type such as a substrate into a fifth impurity region adjacent to the region and corresponding to the guard ring region. The method of claim 1, wherein the concentration of the second impurity is higher than that of the first impurity. The method of claim 1, wherein the concentration of the fourth impurity is higher than that of the second impurity. The method of claim 1, wherein when the first and the third impurity is n-type, the ion implantation conditions are implantation energy of 100 to 200 (keV) and dose amount of 3.0 El 2 to 1.0 El 3 (ions / cm 2) MOS transistor manufacturing method. 2. The method of claim 1, wherein when the first and third impurities are P-type, the ion implantation conditions are 50 to 150 (keV) of implantation energy and 1.0 El 3 to 1.0 El 4 (ions / cm 2) of dose. MOS transistor manufacturing method. The method of claim 1, wherein when the second impurity is n-type, the ion implantation conditions are implantation energy of 70-180 (keV) and dose amount of 1.0El3 ~ 1.0El5 (ions / ㎠) MOS) transistor manufacturing method. The method according to claim 1, wherein when the second impurity is P-type, the ion implantation conditions are implantation energy of 50 to 150 (keV) and dose of 1.0 El 4 to 2.0 El 5 (ions / cm 2). MOS) transistor manufacturing method. The method of claim 1, wherein when the fourth and the fifth impurity is n-type, the ion implantation conditions are 40 to 80 (keV) implantation energy and 3.0 El5 to 1.0 El6 (ions / ㎠) dose amount MOS transistor manufacturing method. The method of claim 1, wherein when the fourth and the fifth impurity is P-type, the ion implantation conditions are 40 to 80 (keV) of implantation energy and 1.0 El5 to 1.0 El6 (ions / ㎠) dose amount MOS transistor manufacturing method. The method of claim 1, wherein the field oxide film is formed by first annealing in a nitrogen atmosphere at a temperature of 950 to 1050 캜.