KR0138792B1 - Data transmission circuit - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a data transmission circuit for transmitting message data, and more particularly, to a data transmission circuit suitable for a BCH codec.

2. Technical problem to be solved by the invention

When the overhead of the control unit for controlling the transmission unit of the BCH codec is large, a malfunction occurs because the control unit fails to process the transmission interrupt request from the transmission unit in a timely manner.

3. Summary of Solution to Invention

Interrupts are implemented in a plurality of block units to prevent malfunctions by reducing overhead caused by interrupts in the control unit.

4. Important uses of the invention

Transmitter of BCH codec

Description

Data transmission circuit

1 is a block diagram of a data transmission circuit according to the present invention.

FIG. 2 is a detailed circuit diagram of the block storage unit 12 shown in FIG.

3 is a detailed circuit diagram of the first register 26 shown in FIG.

4 is an operation timing diagram of the present invention.

* Explanation of symbols for main parts of the drawings

10: CPU12: Block storage unit

14: control signal generator 16: transmitter

18, 20: 1st, 2nd counter 22: status signal generator

24: encoder 26-30: No. 1-112 register

32: multiplexer 33-38: NAND gate

40-44: Latch circuit

The present invention relates to a data transmission circuit for transmitting message data, and more particularly, to a data transmission circuit suitable for Bose-Chaundhuri-Hocquenghem codes CODEC.

Section 4 of EUROCOM D1 typically specifies the use of the (31,21) BCH codecs for error control of signaling messages in trunk signaling of the transmission system. Looking at the encoding format of the (31,21) BCH codec, the codeword length is composed of 21 bits of message data and 10 bits of redundancy bits. The (31,21) BCH codec transmits and receives data to and from the communication counterpart in 32-bit data bits, including 31-bit codeword and 1-bit parity bit.

There is a patent application No. 92-22470 data transmission circuit filed on November 26, 1992 in the Republic of Korea by the present applicant as a transmitter of the (31,21) BCH codec suitable for the provision of Eurocom D1 as described above. The transmission unit of the (31,21) BCH codec disclosed in the above-mentioned patent application No. 92-22470 receives and processes data in block units from a control unit. Receive and process. At this time, a CPU (Central Processing Unit) is used as the control unit, and a block of data is transmitted to the transmission unit by a transmission interrupt from the transmission unit.

However, in this case, if the overhead of the controller is large, a delay may occur because the interrupt cannot be processed in a timely manner. For example, when the BCH codec as described above is applied to the signaling channel of a circuit-type exchanger, when one controller is responsible for four channels, that is, four BCH codecs at a rate of 32 Kbps, the interruption cannot be processed at the right time. There is a problem that a malfunction occurs in retransmitting a block that has been processed and transmitted.

Accordingly, an object of the present invention is to provide a data transmission circuit capable of preventing a malfunction by reducing the overhead caused by the interrupt of the controller.

Another object of the present invention is to provide a data transmission circuit that can implement an interrupt in a plurality of block units to reduce the overhead caused by the interrupt of the controller.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a data transmission circuit according to the present invention. When the present invention is applied to the patent application No. 92-22470 described in the present invention, the control unit responds to one transmission interrupt in response to one block interruption. An example of the case of transmission is shown. In FIG. 1, the central processing unit (CPU) 10, as a controller, applies the response signal INT_ACK to the control signal generator 14 in response to the entry and exit of TX_INT through the transmission interrupt from the control signal generator 14, Eight block data are stored in the address signal ADDRO-ADDR2 and the storage signal. By sequentially storing in the block storage areas of the block storage unit 12, the first block termination signal EOB1 is cooled and applied to the control signal generation unit 14. Reference numeral DATA denotes an 8-bit data bus of the CPU 10. The block storage unit 12 is composed of FIFOs (First In-First Out) each having a block storage area for storing blocks of 21 bits of data, and generates control signals by generating status signals indicating the storage state of the block storage areas. The generator 14 is applied. The block storage unit 12 includes an available flag signal A_FLG indicating that four or more block storage areas are emptied, an empty flag signal E_FLG indicating that the block storage areas are emptied, and A full flag signal F_FLG, which indicates that the block storage areas are all empty, is generated as status signals, among which the available flag signal A_FLG and the empty flag signal E_FLG are applied to the control signal generator 14. When the present invention is applied to the patent application No. 92-22470 as described above, the block storage unit 12 is the register unit of FIG. 1, the detailed configuration of which is shown in FIG. The latch 110 of the 100 is to be replaced. Therefore, in the case of applying the present invention, the register unit 100 of Patent Application No. 92-22470 may be constituted only by the parallel shift register 120. The control signal generator 14 detects the storage state of the block storage unit 11 from the available flag signal A_FLG and the empty flag signal E_FLG, and generates a transmission interrupt signal TX_INT when four or more block storage areas are empty. In response to the first block end signal EOB1, the second block end signal EOB2 and the load signal LOAD are repeatedly generated corresponding to each block until the block storage areas are all freed. And the transmitter 16. The transmitter 16 loads the data stored in each block storage area of the block storage unit 12 one block at a time when the load signal LOAD is input in the state enabled by the second block end signal EOB2 (31). (21) Send after BCH encoding. The transmission unit 16 corresponds to the transmission unit of the BCH codec (31, 21) improved as a data transmission circuit in the above-described patent application No. 92-22470, and the register unit 100 of the patent application No. 92-22470 The rest of the configuration and operation are the same as that of the data transfer circuit of Patent Application No. 92-22470, except that it is changed to consist only of the parallel shift register 12.

2 is a detailed circuit diagram of the block storage unit 12 of FIG. The twelve first to twelfth registers 26-30 perform block data applied from the CPU 10 in a state of being enabled by the first to twelfth enable signals LOAD_ENO_LOAD_EN11 sequentially generated from the encoder 24. Address signal ADDRO-ADDR2 and storage signal of (10) Provides a block storage area for latching and storing one block each. The first counter 18 stores the storage signal from the CPU 10. The number of times of input is counted and the counted data is output as the storage pointer WR_PNT. The second counter 20 counts the number of occurrences of LOAD by the load signal from the control signal generator 14 and outputs the counted data read pointer RD_PNT. The state signal generator 22 stores the stored signal And status signals indicating a storage state of the first to twelfth registers 26-30 through the load signal LOAD, the storage pointer WR_PNT and the read pointer RD_PNT, that is, the above-mentioned adaptive flag signal A_FLG and the empty flag signal. E_FLG and the full flag signal F_FLG are generated. The encoder 24 generates the first to twelfth enable signals LOAD_ENO-LOAD_EN11 for encoding the storage pointers WR_PNT to enable the first to twelfth registers 26-30 one by one. The multiplexer 32 selects the first to twelfth registers 26-30 one by one by the read pointer RD_PNT, and outputs them to the block data transmitter 32 stored in the corresponding register.

The first through twelfth registers 26-30 of FIG. 2 are configured in the same manner. For example, the detailed circuit diagram of the first register 26 is shown in FIG. 3. In FIG. 3, the first enable signal LOAD_ENO is commonly input to one input terminal of the NAND gate 34-38, the other input terminal is respectively input one of the address signals ADDRO-ADDR2, and the output terminals are respectively latch circuits 40. FIG. -44) is connected to enable terminal EN. The storage signal is supplied to the clock terminal of the latch circuit 40-44. Are commonly applied, and the data input terminals D0-D7 of the latch circuits 40 and 42 and the data input terminals D0-D4 of the latch circuit 44 are commonly connected to the data bus DATA, and the latch circuit 40 The data output from the output terminals Q0-Q7 of 42 and the output terminals Q0-Q4 of the latch circuit 44 are together applied to the multiplexer 32 as 21 bits of parallel data.

4 is an operation timing diagram of the present invention. For convenience, FIGS. 4A and 4B are illustrated, but FIGS. 4A and 4B are connected to each other.

An operation example of FIGS. 1 to 3 according to the present invention will now be described in detail with reference to the operation timing diagram of FIG.

First, when the transmission interrupt signal TX_INT is activated in the control signal generator 14 and is generated, the CPU 10 receives an interrupt request by the transmission interrupt signal TX_INT, and in response, sends the control signal INT_ACK to the control signal generator. It is applied to (14). At this time, the transmission interrupt signal TX_INT is disabled at the rising edge of the response signal INT_ACK as shown in FIG. After applying the response signal INT_ACK to the control signal generator 14, the CPU 10 stores the eight block data in the block storage 12. In this case, since the data bus DATA is 8 bits, the CPU 10 stores one block three times in the block storage unit 12. That is, one block of 21 bits is stored in the block storage unit 12 by sequentially storing 8 bits, 8 bits, and 5 bits in the block storage unit 12. At this time, the block storage unit 12 can store and read in units of 21 bits by moving the write pointer WR_PNT by the first counter 18 when the third address signal, that is, ADDR2 is activated.

After storing all eight blocks in the block storage unit 12 by the above operation, the CPU 10 generates the first block termination signal E0B1 as shown in FIG. The first block end signal E0B1 generated by the CPU 10 is the same signal as the block end signal EOB provided to the (31, 32) BCH codec transmitter of Patent Application No. 92-22470 described above. Then, the control signal generator 14 inputs the first block termination signal E0B1 to generate the second block termination signal E0B2 and applies it to the transmitter 16 as shown in FIG. The second block end signal E0B2 replaces the block end signal E0B provided to the (31, 32) BCH codec transmitter of Patent Application No. 92-22470. Accordingly, the conventional (31, 32) BCH codec transmitter can perform the conventional functions invariably despite the change of the peripheral circuit.

In addition, the load signal LOAD generated by the control signal generator 14 replaces the load signal Load1 of the (31,32) BCH codec transmitter of Patent Application No. 92-22470 and its form is the same as the load signal Load1. The second block end signal E0B2 and the load signal LOAD are repeatedly generated corresponding to every block as shown in FIG. 4 until the empty flag signal E_FLG of the state signal generator 22 is activated.

On the other hand, at the time t2 of FIG. 4, the available flag signal A_FLG of the control signal generator 14 is activated, which is 4 times after the CPU 10 stores 8 blocks in the block storage 12. As it is read, it means that there are eight empty registers in the data storage unit 12. At this time, the available flag signal A_FLG changes its state at the rising edge of the load signal LOAD. In this way, when the available flag signal A_FLG is activated at time t2, the control signal generator 14 activates TX_INT as a transmission interrupt, thereby storing the next eight blocks in the block storage unit 12 in the CPU 10. A send interrupt request is made. Data stored in the block storage unit 12 by the CPU 10 is read by the transmission unit 16 and transmitted after BCH encoding. In order to prevent delay, the data is stored only until all the block storage areas of the block storage unit 12 are empty. The CPU 10 may process the interrupt and store the next block data in the block storage unit 12. That is, since there are four blocks of data that have not been read yet in the current block storage unit 12, it is possible to have a long time margin for four block processing times. In FIG. 4, when INT_EN is inactivated by the interrupt enable signal, the interrupt signal TX_INT, which is the transmission, is inactive even if the available flag signal A_FLG is active. Then, when the block storage unit 12 is all empty, the second block end signal E0B2 and the load signal LOAD are repeatedly generated.

Therefore, the CPU 10 only needs to process the interrupt only once every 8 blocks, but the post-interrupt processing time can be afforded for a longer time than the conventional interrupt has to be processed for every block.

As described above, the present invention implements a plurality of block-level interrupts to reduce the overhead caused by interrupts of the control unit, thereby preventing malfunction.

Claims (2)

A data transfer circuit comprising: a plurality of registers each providing a block storage area for latching and storing block data each having a predetermined number of bits by one block by a storage signal, and counting the number of times of applying the storage signal. A first counter for generating data as a storage pointer, a second counter for counting the number of occurrences of the load signal, and generating the counted data as a read pointer, and the block from the storage signal and load signal, the storage pointer and the read pointer. An available flag signal indicating that storage areas have been emptied more than the preset number, an empty flag signal indicating that the block storage areas are all emptied, and a full flag signal indicating that the block storage areas are full, and storing the registers. Generated as status signals indicating status Is a state signal generator, an encoder enabled by the full flag signal to encode the storage pointer to enable the registers one by one, and the read pointer to select the registers one by one and stored in the corresponding register. A multiplexer for outputting block data, a controller for sequentially storing a predetermined number of block data in a block storage area of the registers in response to an input of a transmission interrupt signal, and generating a first block termination signal, and a second block termination signal. A transmitter for loading data stored in each block storage area of the registers one block at a time enabled by the load signal, encoding the data according to a preset format, and transmitting the encoded flag signal; And low of the registers from an empty flag signal. When a state is detected and the block storage areas are emptied for a predetermined number or more, the transmission interrupt signal is generated and applied to the controller, and the second block end signal and the load signal are supplied to the block storage area in response to the first block end signal. And a control signal generator which is repeatedly generated corresponding to each block until all of them are empty and applied to the transmitter. A data transfer circuit comprising: first to twelfth registers each providing a block storage area for latching and storing one block of 21-bit block data by a storage signal, and counting and counting the number of times of applying the storage signal; A first counter for generating the stored data as a storage pointer, a second counter for counting the number of times the load signal is generated, and generating the counted data as the read pointer, and storing the stored signal and the load signal, the storage pointer and the read pointer. An available flag signal indicating that the block storage areas have been emptied more than the preset number, an empty flag signal indicating that the block storage areas are all emptied, and a full flag signal indicating that the block storage areas are full, Status signal generator which generates as status signals indicating the storage status And an encoder enabled by the full flag signal to encode the storage pointer to enable the registers one by one, and selecting the registers one by one by the read pointer to output the block data stored in the register. A multiplexer, a control unit for sequentially storing eight block data in a block storage area of the registers in response to an input of a transmission interrupt signal, and generating a first block termination signal; and enabled by the second block termination signal. When the load signal is input in the state, the transmission unit loads the data stored in each block storage area of the registers one block by (31, 21) BCH encoding, and transmits it, and the available flag signal and empty The storage state of the registers is sensed from the flag signal so that the four block storage areas When it is emptied, the transmission interrupt signal is generated and applied to the controller, and the second block termination signal and the load signal are repetitively corresponding to every block until the block storage areas are all empty in response to the first block termination signal. And a control signal generator which is generated and applied to the transmitter.