KR0138713B1 - Reference voltage generator - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generator for supplying a reference voltage required by a comparison circuit and used in a memory device. The present invention relates to a reference voltage generator that eliminates the need for an option process each time the external power supply voltage changes.

Description

Reference voltage generator

1 is a circuit diagram of a conventional reference voltage generator.

2 is a circuit diagram of a reference voltage generator according to an embodiment of the present invention.

3 is a graph showing the dependence of the reference voltages generated in the circuits of FIGS. 1 and 2 on the external power supply voltage.

* Description of the symbols for the main parts of the drawings *

11: Start-up circuit section 12: Reference voltage generation section

13: First Current Mirror 14: Second Current Mirror

15: variable resistance

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generator for supplying a reference voltage required by a comparison circuit for a memory device. In particular, the present invention relates to a reference voltage using CMOS to control a resistance value that changes as an external power supply voltage changes. The present invention relates to a reference voltage generator that eliminates the need for option processing each time the external power supply voltage changes.

FIG. 1A shows an example of a conventional reference voltage generator, which is composed of a startup circuit 11 and a reference voltage generator 12. The startup circuit 11 is always connected to the node N2 by Vcc. The reference voltage generator 12 is operated by keeping it below -VTP. When the power supply voltage Vcc drops down by the threshold voltages of the PMOS transistors MP3 and MP4, Vcc-2VTP is transmitted to the node N1, and the node N2 has a higher value than Vcc-VTP. The PMOS transistor MP5 is turned on to drop the node N2 to the level of Vcc-VTP. When power is supplied and the reference voltage generator 12 is operated, the node N2 is not lowered than Vcc-VTP, so the start-up circuit 11 does not play a role.

On the other hand, since the PMOS transistors MP1 and MP2 of the reference voltage generator 12 have the same gate-source voltage, when the channel width and channel size of the transistor are the same, the current flowing through the transistors MP1 and MP2 has the same value. Will have

Since the NMOS transistors MN1 and MN2 operate in the saturation region, the following equation is satisfied.

V ₁ = V _GS1 = V _GS2 + IR ₁ → Equation 1

V _GS1 = V _TN + (2I / β ₁ ) ^1/2 → Equation 2

V _GH2 = V _TH + (2I / β ₁ ) ^1/2 → Equation 3

By solving the above equations 1, 2, and 3 together, V1 can be obtained as follows. Therefore, the reference voltage (V1 is), V ₁ = V _TH + {(2 / tox) / (R ₁ · με)} (L ₁ / W ₁ ) ^1/2 [(L ₁ / W ₁ ) ₁ / ^2- (L ₂ / W ₂ ) ^1/2 ] → Equation 4.

In Equation 4, L ₁ and L ₂ are the channel sizes of MN1 and MN2, W ₁ and W ₂ are the channel widths of MN1 and MN2, tox is the thickness of the gate oxide, and μ and ε are the movements of electrons, respectively. And the dielectric constant of the gate oxide.

As shown in the above equation, the reference voltage V1 has a value independent of the power supply voltage.

FIG. 1B is a circuit for generating a reference voltage higher by IR ₂ than the reference voltage V1 by adding a resistor R2 to FIG. 1A, and has a relationship as shown in Equation 5 below.

V _ref1 = V ₂ + IR ₂ → equation 5

Here, in Equation 5, when the current flowing through the PMOS-type current mirror in Fig. 1b is I, a voltage of IR ₂ is generated in R ₂ according to Ohm's law, and V _ref1 is an algebraic sum of V ₁ and IR ₂ . Appears.

When the conventional reference voltage generator is used, a problem arises in that a fixed resistor must be separately installed to cope with a resistance value that changes as the external power supply voltage changes.

Accordingly, an object of the present invention is to provide a reference voltage generator capable of generating a desired reference voltage regardless of a change in external power supply voltage.

In order to achieve the above object, the present invention implements the reference voltage generator using a variable resistor that actively responds to a change in the external power supply voltage.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.

2 is a circuit diagram of a reference voltage generator according to an embodiment of the present invention, which is controlled by a power supply voltage Vcc and starts up circuit part 11 for controlling generation of a reference voltage by transmitting or discharging a current to the reference voltage generator. And a reference voltage generator 12 including a variable resistor 15 whose value is constantly changed in accordance with the potential difference between the power supply voltage and the ground voltage.

Since the PMOS transistor MP16 operates in the linear region, the resistance of the channel has a relation as shown in equation (6).

Here, if Equation 6 is derived, PMOS transistor MP16 of FIG. 2 operates in an unsaturated linear region where I _ds also increases as V _ds increases.

V _gs ≥ V _TP

V _ds ≤ V _gs -V _TP

I _ds = β [(V _gs -V _TP ) -V _ds ] V _ds ---------- ①

Satisfies the relationship.

Equation ① is

--------- ②

Is transformed into

here, Is the resistance of the PMOS transistor MP16,

---------- ③

Can be written as:

Summarizing the above equation ③,

---------- ④

Can be written as:

Here, when (V _gs -V _ds ) is obtained, the gate, source, and drain potentials of MP16 in FIG. 2 are V _g , V _s , and V _d , respectively.

V _gs = V _g -V _s ---------- ⑤

V _ds = V _dd -V _s ---------- ⑥

And satisfying the relation of, and V _g = 0 V, V _s = V _ref2 , V _d = V ₁ ,

V _gs = -V _ref2 ---------- ⑦

V _ds = V _1- V _ref2 ---------- ⑧

It becomes

When equations (7) and (8) are combined and solved, V _gs -V _ds = -V ₁ .

Here, since the resistance is positive, the negative value is meaningless.

Eventually, if V _gs -V _ds = V ₁ and insert it into the above equation ④,

Can be derived.

Where β =-.

t _ox L

Since the value of V _TP increases as the back bias potential increases, the resistance of the PMOS transistor MP16 increases in proportion to the power supply voltage. Thus, the β value of the PMOS transistor MP16, that is, the channel size and width, is increased. By adjusting, the desired reference voltage can be easily obtained.

Here, the actively responding variable resistor refers to the PMOS transistor (MP16) 15 of FIG. As can be seen, since β and V ₁ are fixed constants, and R _MP is a variable of V _{TP which} is the threshold voltage of the PMOS transistor, the resistance value of the PMOS transistor MP16 is changed according to the change of the external voltage. It changes and acts as a variable resistor.

3 is a graph showing the dependence of the reference voltage generated in the circuits of the prior art and the present invention on the power supply voltage.

As described above, in a conventional reference voltage generator using a resistor, when a product having a different external power supply voltage is implemented in a single design, an optional treatment is required to change the resistance value. CMOS implementation eliminates the need for optional processing on output.

Claims (3)

A start-up circuit operated by a power supply voltage and outputting a start potential below a predetermined level for preventing turn-off; A reference voltage of a semiconductor memory device comprising a reference voltage generating means composed of a first current mirror and a second current mirror between a power supply voltage terminal and a ground voltage terminal and driven by a start potential of the start-up circuit to generate a reference voltage; In the generator, And a variable resistor connected between the first current mirror and the second current mirror in the reference voltage generating means to automatically change a resistance value in proportion to a change in an external voltage to generate a predetermined reference voltage. A reference voltage generator for a semiconductor memory device. The method of claim 1, The variable resistor is a reference voltage generator of the semiconductor memory device, characterized in that provided using a MOS transistor. The method according to claim 1 or 2, The variable resistor is a reference voltage generator of the semiconductor memory device, characterized in that provided using a PMOS transistor.