KR0138376B1 - Error monitoring apparatus and method thereof - Google Patents

Abstract

The present invention relates to an error monitoring apparatus and method for reducing the processor burden by reducing the number of bits of error data in a digital recording and reproducing system,

By converting the error data value counted for a certain period to the exponent to reduce the number of bits of the detected error data to be transmitted to the processor, to reduce the burden on the processor to speed up the system.

Description

Error monitor device and method

1 is a block diagram of a conventional error monitor apparatus.

2 is a diagram showing the relationship between the number of error data and the number of bits for indicating the same by a conventional method.

3 is a block diagram of the error monitor apparatus of the present invention.

4 is a detailed circuit diagram of the error monitor apparatus of the present invention.

5 is a timing diagram of a basic signal according to the driving of the present invention.

6 is a timing diagram of a signal for processing error data according to the present invention.

7 is a view showing the relationship between the number of error data and the output data according to the present invention.

The present invention relates to an apparatus for processing errors in a digital recording and reproducing system, and more particularly, to an error data processing apparatus and method for reducing the burden on a processor by reducing the number of bits of error data.

In the conventional digital recording and reproducing apparatus, the error monitoring method is operated in such a manner that a counter counts all the number of errors for a section to be detected and supplies it to the processor.

As shown in the conventional error data processing apparatus shown in Fig. 1, the counter 11 composed of n JK flip-flops counts the number of errors in a certain section and according to the number of errors counted by the method. The bits are output as shown in the relationship between the number of error data shown in FIG. 2 and the number of bits for indicating them. The counter 11 counts an input error during the interval to detect the error, and assuming that the error continues to occur during the interval, a clock C _n is formed and output from the clock C ₁ . In this case, the number of countable errors is 2 ⁿ when the number of JK flip flops constituting the counter 11 is n.

The error data processing method according to the above method burdens the processor due to the large amount of error data transmitted to the processor, and also stores unnecessary data in the memory even when the processor does not use all of the transmitted error data. There is a problem that must be done.

In order to solve the above problems, the error monitor apparatus and method of the present invention converts the error data value counted for a certain period into an exponent and reduces the number of bits of the detected error data and transmits it to the processor, thereby reducing the burden on the processor. Has its purpose.

In order to achieve the above object, the error monitor apparatus of the present invention

An error counter for counting the number of error monitor devices that have occurred,

Clock forming means for forming a third clock formed of one clock correspondingly from the value of the counted error data, and

An error detection means for converting the number of error data into an exponent using the third clock and latching the error data value converted into the exponent to a processor;

Error data detection method

A third clock forming step for forming a third clock from counted error data;

A fourth clock forming step of forming an added data by OR-processing the formed clock; And

And a data conversion step for converting the added data to an exponent corresponding to the error data.

The method of monitoring the error by transmitting the number of errors monitored in the digital recording / reproducing system to the CPU through the interface for a predetermined period is

Counting the number of errors generated during the predetermined period and generating the count value in binary;

Converting the generated count value of the binary number into the number of bits of significant digits capable of displaying and generating the converted information in binary; and

And transmitting the converted binary number to the CPU as error monitor information.

Hereinafter, an embodiment of an error monitoring apparatus and method of the present invention will be described in more detail with reference to the accompanying drawings.

3 is a block diagram of the error monitor apparatus of the present invention.

4 is a detailed circuit diagram of the error monitor apparatus of the present invention.

5 is a timing diagram of a basic signal according to the driving of the present invention.

6 is a timing diagram of a signal for processing error data according to the present invention.

7 is a view showing a relationship between the number of error data and the output data according to the present invention.

The error monitor apparatus processing apparatus of the present invention shown in FIG. 3 and FIG. 4 is

N JK flip-flops (first, second, third, ..., nJK flip-flops 411 to 415) determined according to the number of error data to be counted for counting the number of error data generated. Error counters (31, 41),

N D flip-flops (first, second, third) to form a third clock formed of one pulse having a narrow width from a clock representing error data supplied and counted by the counters 31 and 14. ,… nD flip-flops 421 to 425}, and clock forming means 32 and 42 for forming a third clock from the value of the counted error data, and

Error detection means (33, 45) for converting the number of error data into an exponent using the third clock and latching the error data value converted into the exponent to the processor;

The basic signals shown in FIG. 5 are

The first clock, which is the default clock,

A second clock having a period twice the base clock,

A predetermined period (T) indicating a predetermined period to be detected,

A synchronization signal for representing the period T,

An error signal that is high when there is an error in synchronization with the second clock and low when there is no error,

A latch signal for latching an error value counted during the predetermined period T, and

The error every predetermined period T is composed of a reset signal for resetting the counter 31 to newly count.

The signals shown in FIG. 6 are signals for processing error data according to the present invention.

A clock C ₁ formed from the first JK flip-flop 411,

A clock C ₂ formed from the second JK flip-flop 412,

A clock C ₃ formed from the third JK flip-flop 413,

A clock C ₄ formed from the fourth JK flip flop;

A clock Cn formed from the nth JK flip-flop 415,

The third clock formed of a pulse having a narrow width corresponding to the first change (low to high) of the clock (C ₁ to Cn) is detected.

The clock in response to this detection the (low-high), the first clock variation (D ₁₎ which is formed by the first 1D flip-flop 421 of the (C _1),

A clock D ₂ formed by the second D flip-flop 422 in response to detecting an initial change in the clock C ₂ ,

A clock D ₃ formed by the 3D flip-flop 423 in response to detecting an initial change of the clock C ₃ ;

A clock D ₄ formed by the _fourth D flip-flop in response to detecting an initial change in the clock C ₄ , and

And a clock Dn formed by the nth D flip-flop 425 in response to detecting an initial change of the clock Cn.

The clock (D ₁₎ a fourth clock which is formed by adding the clock (Dn) from _{(D 1 + 2 ... n)} ,

A clock E indicating the number of errors counted by the counter 41, and

The value of the error counted by the clock forming means 32 is composed of a clock M which is finally output by the error detecting means 33.

The drive of the error monitor apparatus of the present invention according to the above configuration

If the counter 41 counts an input error during the period T to detect the error on the basis of the second clock, and assumes that the error continues to occur during the period T, the counter shown in FIG. The clock Cn is formed and output from the clock C ₁ . In this case, the number of countable errors is 2 ⁿ when the number of JK flip flops constituting the counter 41 is n. The clock (from C ₁ Cn) formed by the above method is input to the clock forming means 32, the clock formation unit 32 illustrated in the Figure 6 from the input clock (from C ₁ Cn) the 3 clocks (clock (to form Dn) from D _1. Dn) is a clock which is formed shorter is the period of the clock corresponds to the clock (in the C ₁ Cn), that the clock in the third clock formed (D ₁ ( when converted to Cn) by an index in C _1, the clock (when the Cn) formed in a C ₁ to solve the problem of formation is delayed for a predetermined time. the formed third clock (from D ₁ Dn) are OR The fourth clock D _{1 + 2... N} is formed and output through the gate 34, and the error detecting unit 33 uses the fourth clock D _{1 + 2.} The number of error data is counted, the counted value is latched and transmitted to the processor, and the number of D flip-flops is an error to be detected. If the number of data is N, it consists of log ₂ ^{N + 1} .

The error monitoring method of the present invention according to the configured error monitor apparatus counts the number of error data generated during the interval designated by the counter 31 in the data counting step, and counts the error data in the third clock forming step. In order to smoothly process, a third clock is formed in which the clock representing the error data and the generated time point are the same and the width of the clock is small. Converting the formed third clock into added data using an OR gate 34 in a fourth clock forming step, and converting the added formed data into an index corresponding to the error data in the error data converting step and outputting the converted data; Detects with

In the above method, the error is monitored by transmitting the number of errors monitored in the digital recording / reproducing system to the CPU through the interface for a predetermined period.

Counting the number of errors generated during the predetermined interval and generating the count value in binary;

Converting the generated count value of the binary number into bit number information of significant digits capable of displaying and generating the converted information in binary; And

Transmitting the converted binary number as error monitor information to the CPU;

The count value of the binary number formed in the step of counting the number of errors generated during the predetermined interval and generating the count value in binary is converted into bit number information of a significant digit that can indicate this, and the converted information is converted again. The error data monitored is transferred to the CPU in such a way that it is converted to binary and the binary converted by the method is transmitted to the CPU as error monitor information.

The data value formed by this method is represented by the following equation.

Clock (D _{1 + 2 ... n} ) = Clock (D ₁ ) + Clock (D ₂ ) + Clock (D ₃ ) +. … + Clock (Dn)

T-1

Clock (D _n ) = C _n

The error data detected by the above method takes 3 bits according to the conventional method as shown in FIG. 7, whereas the error data represented by the present invention has 2 bits, and 7 bits of error data. Is 3 bits and error data corresponding to 12 bits can be represented by 4 bits, which can be seen to increase exponentially. That is, if the maximum number of error data to be counted is N, and the error detection value to be detected in the present invention is X, the relationship between N and X is expressed by the following equation.

(For example, if the error detection value is a 4-bit value)

(When N = 0) N = X

(When N ≠ 0) 2 ^X-1 ≤ N 2 ^X

Accordingly, the error data processing apparatus of the present invention converts the error data value counted for a certain period into an exponent, reduces the number of bits of the detected error data and transmits the result to the processor to reduce the burden on the processor, thereby speeding up the system speed. There is a remarkable effect.

Claims (8)

An error counter for counting the number of error data generated; Clock forming means for forming a third clock formed of a clock corresponding to the counted error data value; And And error detection means for converting the number of error data into an exponent by using the third clock and latching the error data value converted into the exponent to the processor. The method of claim 1, wherein the clock forming means An error monitor device characterized by comprising several D flip flops. The method of claim 2, wherein the D flip-flop When the number of error data to be detected is N, Error monitoring device characterized in that consisting of log ₂ ^{N + 1} . An error counter for counting the number of error data generated; Clock forming means for forming a third clock formed of a clock corresponding to the counted error data value; And error detecting means for converting the number of error data into an exponent using the third clock and latching the error data value converted into the exponent to the processor. A data counting step of counting error data; A third clock forming step for forming a third clock from the counted error data; A fourth clock forming step of forming a fourth clock representing the added data by OR-processing the formed clock; And And a data conversion step for converting the added data to an exponent corresponding to the error data. The method of claim 4, wherein The third clock formed in the third clock step is And a clock having the same count as the counted error data and having a same time point and having a smaller width of the clock. The method of claim 4, wherein The fourth clock formed in the fourth clock forming step is An error monitoring method characterized by the following equation. Third clock (D _{1 + 2 ... n} ) = clock (D ₁ ) + clock (D ₂ ) + clock (D ₃ ) +. … + Clock (Dn) T-1 Clock (D _n ) = C _n The method according to any one of claims 4 to 6, Detection of error data by the above method When the maximum number of error data to be counted is N, and the error detection value to be detected is X, the relationship between N and X is expressed by the following equation. (E.g., when the error detection value has a 4-bit value) (When N = 0) N = X (When N ≠ 0) 2 ^X-1 ≤ N 2 ^X A method for monitoring an error by transmitting the number of errors monitored in a digital recording / reproducing system to a CPU via an interface for a predetermined period, Counting the number of errors generated during the predetermined interval and generating the count value in binary; Converting the generated count value of the binary number into bit number information of significant digits capable of displaying and generating the converted information in binary; And And transmitting the converted binary number as error monitor information to the CPU.