KR0137830Y1 - Black level compensation circuit - Google Patents

Abstract

The present invention compensates for the black level that occurs when the video card is changed or the mode is changed in the monitor, and the black raster pattern is removed by adjusting the clamp signal pulse width used in the monitor. .

The black level compensation circuit devised in the present invention is able to contribute to the advanced product by using the method of blocking the black level by changing the amplitude and pulse duration of the conventional clamp pulse signal.

Description

Black Level Compensation Circuit

(A) of FIG. 1 is a video signal diagram having a composite signal component.

(b) is a waveform diagram of a horizontal deflection sawtooth wave.

(c) is a conventional clamp signal timing diagram.

(d) is a clamp signal timing diagram in the present invention.

(e) Black Raster pattern showing horizontal retracement.

2 is a compensation circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

10: back porch 20: horizontal synchronous signal pulse

30: front porch 40: horizontal blanking signal pulse

45: pulse switching circuit

50: Complementary Darlington Circuit

60: start-up circuit 70: control circuit

T1: Horizontal return time T2: Conventional clamp gate return time

T3: Clamp Gate Return Time

The present invention relates to a circuit for compensating for black levels occurring in a raster during a period in which the scanning line of the monitor is horizontal retraced.

In general, a method of restoring an image on a monitor is as follows.

The video signal containing the image information is determined according to the amplitude. The white level with the signal size of 12.5% represents the color of white, and the black level with the signal level of 67.5% represents the color of black.

If the video signal is located at a white level with a signal size of 12.5% between the grid of the picture tube and the cathode, the imager emits light while the black level signal with a signal size of 67.5% is used for the imager. The light is cut off by cutting off.

The horizontal synchronous signal pulse 20 for adjusting the raster of the video signal in the monitor has a magnitude of 25% in the amplitude of the video signal, which is dark black because the video signal exceeds the black level signal at a level of 67.5% or more. do. A normal video signal should maintain a white level at a level of 12.5% to prevent loss of the picture carrier. If the video signal level becomes zero, loss of the picture carrier occurs. In fact, in order to adjust the size of a raster on a monitor, it is necessary to sample the video signal into a signal of a certain size. To this end, the horizontal synchronous signal pulses 20 are loaded on the video signals, and the horizontal blanking signal pulses 40 are loaded between the horizontal synchronous signal pulses 20. However, the horizontal synchronous signal pulse 20 is not loaded exactly at the center of the horizontal blanking signal pulse 40, and the front porch 30 and 1.6 μs of the back porch 10 are loaded simultaneously with the horizontal blanking. The back porch 10 mounted on the signal pulse 40 is generated before the horizontal deflection sawtooth wave (the first b degree) reaches the maximum point, so that the electron beam of the imaging tube before the electron beam reaches the right edge of the screen from the left side of the screen. This turns off, resulting in a black raster as shown in FIG.

Therefore, as shown in (b) of FIG. 1, when the retrace time is not longer than the time of adding the horizontal synchronous signal pulse 20 and the front porch 30 ((d) of FIG. 1), as shown in (d) of FIG. The black raster pattern does not occur. Accordingly, an object of the present invention is to provide a circuit for reducing the return time by extending the clamp gate pulse time T1 of the clamp signal as shown in (d) of FIG. 1 and thus removing the black raster.

Looking at the configuration of the present invention with reference to Figure 2 as follows.

The control circuit 70 for receiving a clamp signal as shown in (c) of FIG. 1 and converting it into a clamp signal as shown in (d) of FIG. 1 includes a pulse switching circuit 45 for switching the clamping signal, and the signal. Complementary multi-arlington circuit 50 for amplifying to a high value, a startup circuit 60 for applying a voltage to the grid and increasing a positive voltage, and a zener diode (D3) for voltage regulation It is done.

The pulse switching amplifier 45 is turned off by a resistor R1 (R2), a capacitor C1, and a shaped clamp signal that shapes a clamp signal to be applied, and outputs an output resistor R3 to the collector. Comprising this connected transistor (Q1), the complementary multi-arlington circuit 50 is connected to the complementary multi-arlington to output a signal from the collector of the transistor Q1 of the pulse switching amplifier circuit 45 with a high gain value. Transistors Q2 and Q3 and resistors R4 and R5 that shape the signals of the transistors Q2 and Q3. In addition, the startup circuit 60 connects a plurality of zener diodes D1 and D2 in series to the collector output of the transistor Q3 of the complementary multi-arlington circuit 50 to apply a startup voltage to the grid.

Hereinafter, the operation of the present invention will be described in detail with reference to FIG. 2.

The applied clamp signal is converted into a longer pulse duration by a circuit composed of resistors R1 and R2 and capacitor C1 and applied to the base terminal of transistor Q1.

The transistor Q1 is an npn type transistor, and a pulse applied to the base end of the transistor is turned on at a high level pulse and turned off at a low level. Therefore, the transistor Q1 is turned on when a pulse having a longer pulse duration is applied. The level is output.

The collector of transistor Q2 increases the signal size and duration by the voltage difference between the base and emitter of npn-type transistor Q2 brought to the low level by transistor Q1. The type transistor Q3 is turned on.

The clamp signal applied to the transistor Q1 while passing through the complementary multi-arlington circuit 50 composed of the transistors Q2 and Q3 has a magnitude and pulse duration increased as shown in FIG. Is applied to the grid.

In addition, the startup circuit 60 applies a startup voltage and a positive voltage to the grid, and is inactive after startup, and the zener diode D3, which operates as a voltage regulator, does not have an output voltage. In this case, all the fluctuations in voltage are applied to the resistor R5.

Therefore, the circuit devised in the present invention has the effect of contributing to the improvement of product quality and the high quality by removing the black raster generated from the monitor.

Claims (1)

In the circuit for removing the black raster pattern appearing on the monitor, the pulse switching amplifier circuit 45 includes a series resistor R1 that shapes an applied clamp signal, and a parallel resistor R2 whose one end is grounded, respectively. And a pulse switching amplifier circuit 45 including a capacitor C1 and a transistor Q1 connected on and off by a shaped clamp signal and having an output resistor R3 connected to the collector; In order to output the signal from the collector of the transistor Q1 of the pulse switching amplifier 45 with a high gain value, the transistor Q2 and the transistor Q3 are complementary in two stages of the transistor Q3 of the multi-arlington circuit 50. Zener diode (D1) (D2) is connected in series to the collector output of the control circuit including a start-up circuit (60) for outputting to the grid output control circuit for extending the clamp gate pulse time (T1) of the clamp signal (70) Black level compensation circuit comprising: a.